Features• Based on the BlueNRG-1 Bluetooth low energy system on chip• Associated STSW-BLUENRG-DK (BlueNRG-1 development kit software

package) including firmware and documentation• Up to +8 dBm available output power (at antenna connector)• Excellent receiver sensitivity (-88 dBm)• Very low power consumption: 7.7 mA RX and 8.2 mA TX at +0 dBm• Bluetooth® low energy compliant: supports master, slave and simultaneous

master-and-slave roles• New integrated balun BALF-NRG-02D3 which integrates a matching network

and harmonics filter• 3 user LEDs• JTAG debug connector• Pre-programmed as network processor• Board size: 60 x 40 mm.• Part of the AutoDevKit™ initiative• RoHS and WEEE compliant

DescriptionThe AEK-COM-BLEV1 evaluation board is based on the BlueNRG-1 low powerBluetooth® smart system on chip, compliant with the Bluetooth® specification.

The evaluation board can be connected to a microcontroller via a 12-pin oralternative 9-pin male connector for SPI, serial interface or I²C communication.

The BlueNRG-1 device is supplied with the network processor software loaded andready to process Bluetooth commands. The software image (DTM_UART.hex) isavailable in the BlueNRG design kit.

The STSW-AEKBLE firmware provides a straightforward demonstration of the AEK-COM-BLEV1 board functionality used in conjunction with the AEK-MCU-C4MLIT1evaluation board with microcontroller.

Product summary

Bluetoothcommunication boardbased on theBlueNRG-1

AEK-COM-BLEV1

Firmware for AEK-COM-BLEV1 testing STSW-AEKBLE

Bluetooth® low energysystem-on-chip BlueNRG-1

Setup for BlueNRG kits STSW-BLUENRG-DK

50 Ω, conjugate matchbalun to BlueNRGtransceiver, withintegrated harmonicfilter

BALF-NRG-02D3

Applications

FactoryAutomation

Bluetooth LowEnergy

MobilityServices

Bluetooth communication board based on BlueNRG-1

AEK-COM-BLEV1

Data brief

DB4125 - Rev 1 - February 2020For further information contact your local STMicroelectronics sales office.

www.st.com

1 Loading firmware onto the BlueNRG-1 chip

Follow the procedure below to restore the factor firmware on the BlueNRG-1 device.

1.1 Hardware and software requirements

• ST-LINK/V2 programmer/debugger, which is connected through the evaluation board JTAG port• STSW-LINK007 - ST-LINK/V2 firmware upgrade• STSW-LINK009 - ST-LINK/V2 Windows driver• STSW-BNRG1STLINK - ST-LINK utility required to burn the code in the BlueNRG-1• STSW-BLUENRG-DK - design kit containing the Flash image for the BlueNRG-1. After installing the design

kit, go to the installation directory ([Firmware ]>[BLE_Examples]>[DTM]>[BlueNRG-1]) to find the“DTM_UART.hex” file

1.2 Firmware burning procedure

Step 1. Connect the ST-LINK/V2 to the PC via USB and to the AEK-COM-BLEV1 evaluation board JTAG port

Step 2. Run the BlueNRG-1 ST-LINK Utility

AEK-COM-BLEV1Loading firmware onto the BlueNRG-1 chip

DB4125 - Rev 1 page 2/12

Step 3. From the top menu, select [Target]>[Settings] and ensure the following parameters are set:– Frequency: 4.0 MHz– Mode: Normal– Port: SWD

Figure 1. BlueNRG-1 ST-LINK Utility settings

Step 4. Press [OK] to confirm

Step 5. From the main menu, select [Target]>[Connect] to connect the programmerThe ST-LINK/V2 LED starts blinking

Step 6. From main menu, select [Target]>[Program Verify]

AEK-COM-BLEV1Firmware burning procedure

DB4125 - Rev 1 page 3/12

Step 7. Press [Browse] and select DTM_UART.hex from the disk to download it

Figure 2. DTM_UART.hex file downloading

AEK-COM-BLEV1Firmware burning procedure

DB4125 - Rev 1 page 4/12

Step 8. Press [Start] to Flash the image onto the BlueNRG-1 memory

Figure 3. BlueNRG-1 ST LINK Utility device memory

Step 9. From the main menu, select[]>[Target]>[Disconnect] to disconnect the programmer

AEK-COM-BLEV1Firmware burning procedure

DB4125 - Rev 1 page 5/12

2 Block diagram

Figure 4. AEK-COM-BLEV1 block diagram

AEK-COM-BLEV1Block diagram

DB4125 - Rev 1 page 6/12

3 Schematic diagrams

Figure 5. AEK-COM-BLEV1 schematic diagram (1 of 4)

GN

D

8

VBAT3

2 DIO10

4

I2C2_CLK

3

1u_0402

TEST

SPI_

CS

RF0SXTAL1 21

L1

15p_0402

I2C2_DAT

A23

1

DIO

12

JTMS-SWTDIO

DIO7

1918

C6

32

TEST

DIO

11

3 DIO9DIO8

25R

ESET

N

DIO

3

DIO

1

SMPS

FILT

1

27

150n_0402

BALF-NRG-0

ADC

2

DIO

13

DIO

3D

IO2

10

29D

IO13

100p_0402

SPI_

IN

33

DIO

0

XTAL_HS

DIO

14SP

I_C

LKD

IO0

L3

Q2

15p_0402

C5

DIO6

FXTAL0 17

100n_0402

FXTAL1

XTAL_LS

23SXTAL0

J2

C4

Q1

TXDA1

4

2

B11

22

U1

C3

SPI_

CS1

/RXD

DIO

14

RES

ETN

11

C14

22p_0402

C1

RF1 VBAT2

22p_0402

JTCK-SWTCK

2

2nH_0402

U12

C2

7 VBAT3DIO5 D3

VBLUE1

SMA connector

169

2

ADC

2

DIO

1

TEST

1

20

VBAT2VB

AT1

DIO

11

C11

DIO

12

DIO8

L5

DIO4

VBAT1

C12

DIO7B2

5 DIO7DIO6

24

28VD

D1V

2

12 13

BlueNRG-1

1

DIO6

C15

26SM

PSFI

LT2

31 30D

IO12

DIO

2

RES

ETN

DIO4

DIO5

D1

SPI_

OU

TD

IO13

14AN

ATES

T1AD

C1

15AD

C1

ANAT

EST0

/DIO

146

DB

4125 - Rev 1

page 7/12

AEK

-CO

M-B

LEV1Schem

atic diagrams

Figure 6. AEK-COM-BLEV1 schematic diagram (2 of 4)

1

470_0402R28

VBLUE VBLUE1R24

Bypass4

1u_0402

GREEN

+5V

2

Gnd

7

100k_0402

Jumper 2

22

11

R55

JP5

VBLUE1TEST

C23

2u2_0402

3

1

33n_0402

Vin

JP1

U3

C22

DL4

C24

6

N.C.Vout

Vinh

LDS3985PU33R

2

VBLUE

3

Gnd5

2u2F-16V-0603

C26R25

0R_0603

0R-1206

DB

4125 - Rev 1

page 8/12

AEK

-CO

M-B

LEV1Schem

atic diagrams

Figure 7. AEK-COM-BLEV1 schematic diagram (3 of 4)

8

R7I2C2_CLK

2

5

TXD

SPI_CLK

0R0_06036

TP3TP2GND

1

0R0_0603

R3

R6

0R0_0603

R1

12

V2

TXD

8

CN2

CN1

RXD

0_0402

12345

DIO7

0_0402

DIO6

DIO12 0_0402

0_0402

CN3R13

R14R15

SPI_OUT

I2C2_DAT

4

VBLUE +5V

0R0_0603

0R0_0603

R10

0R0_0603 R9

1

RESETN

R4

R2

4

3

0R0_0603

R70R0_0603

SPI_IN

10

6

9

3

7

+5V

SPI_CS

V3R6

RESETN

R5

R8

2

V1

9 0R0_0603

0R0_0603

0R0_06035

V4

7

0R0_0603

RXD 11

TP1GND GND

Header 5

DIO13 R160_0402

12345

TEST1

0_0402

DIO14

ADC1 0_0402

0_0402

CN4R17

R19R18

Header 5

ADC2 R20

DB

4125 - Rev 1

page 9/12

AEK

-CO

M-B

LEV1Schem

atic diagrams

Figure 8. AEK-COM-BLEV1 schematic diagram (4 of 4)

C18

VBLUE1

C20C16

VBLUE1

1u_0402 100n_0402

C19VBAT2

C17

VBLUE1

VBAT1

100n_0402

C21VBAT3

1u_0402 100n_0402 1u_0402

DIO

6

YELLOW

R32

DL1

510_0402

100_0402

SW1

VBLUE

100k_0402

10n_0402

RESETN

RESET

R26

R29GND

C25

DIO0

11

VBLUE

5

19

JTCK-SWTCK8

CN7

4

SWD

18

7

1415

GND

23

6

1

RESETN

9JTMS-SWTDIO

DIO1

20

Male Connector2x10 HDR straight

JTAG

13

17

ST Link: 3.0-3.6V, 5V tolerantIAR J-Link: 1.2-3.6V, 5V tolerant

DIO

7

RED

R33

DL2

680_0402

DIO

14

BLUE

R40

DL3

680_0402

1012

16

DB

4125 - Rev 1

page 10/12

AEK

-CO

M-B

LEV1Schem

atic diagrams

Revision history

Table 1. Document revision history

Date Version Changes

19-Feb-2020 1 Initial release.

AEK-COM-BLEV1

DB4125 - Rev 1 page 11/12

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AEK-COM-BLEV1

DB4125 - Rev 1 page 12/12