bm-cremson starterkit lime-v1 03 - farnell element14 · 2010-04-30 · h l 17.73 hz 17.553 to 17.73...

Lime

CREMSON-STARTERKIT-LIME Rev. 1.03

Feb 2007

1.03

Lime Evaluation Board

Revision 1.03

© 2007 Fujitsu Microelectronics Europe

MB86276 Evaluation Board Manual

of 18 Revision 1.03


Warranty and Disclaimer To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH restricts its warranties and its liability for Lime Evaluation Board and all its deliverables (e.g. software include or header files, application examples, target boards, evaluation boards, engineering samples of IC’s etc.), its performance and any consequential damages, on the use of the Product in accordance with (i) the terms of the License Agreement and the Sale and Purchase Agreement under which agreements the Product has been delivered, (ii) the technical descriptions and (iii) all accompanying written materials. In addition, to the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH disclaims all warranties and liabilities for the performance of the Product and any consequential damages in cases of unauthorised decompiling and/or reverse engineering and/or disassembling. Note, the Lime Evaluation Board and all its deliverables are intended and must only be used in an evaluation laboratory environment. 1. Fujitsu Microelectronics Europe GmbH warrants that the Product will perform substantially in

accordance with the accompanying written materials for a period of 90 days form the date of receipt by the customer. Concerning the hardware components of the Product, Fujitsu Microelectronics Europe GmbH warrants that the Product will be free from defects in material and workmanship under use and service as specified in the accompanying written materials for a duration of 1 year from the date of receipt by the customer.

2. Should a Product turn out to be defect, Fujitsu Microelectronics Europe GmbH’s entire liability and

the customer’s exclusive remedy shall be, at Fujitsu Microelectronics Europe GmbH’s sole discretion, either return of the purchase price and the license fee, or replacement of the Product or parts thereof, if the Product is returned to Fujitsu Microelectronics Europe GmbH in original packing and without further defects resulting from the customer’s use or the transport. However, this warranty is excluded if the defect has resulted from an accident not attributable to Fujitsu Microelectronics Europe GmbH, or abuse or misapplication attributable to the customer or any other third party not relating to Fujitsu Microelectronics Europe GmbH.

3. To the maximum extent permitted by applicable law Fujitsu Microelectronics Europe GmbH disclaims

all other warranties, whether expressed or implied, in particular, but not limited to, warranties of merchantability and fitness for a particular purpose for which the Product is not designated.

4. To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH’s and its

suppliers´ liability is restricted to intention and gross negligence. NO LIABILITY FOR CONSEQUENTIAL DAMAGES To the maximum extent permitted by applicable law, in no event shall Fujitsu

Microelectronics Europe GmbH and its suppliers be liable for any damages whatsoever (including but without limitation, consequential and/or indirect damages for personal injury, assets of substantial value, loss of profits, interruption of business operation, loss of information, or any other monetary or pecuniary loss) arising from the use of the Product.

Should one of the above stipulations be or become invalid and/or unenforceable, the remaining stipulations shall stay in full effect


Revision 1.03 of 18


Document Revision History Revision Number Date Description of changes

1.00 25/10/05 Preliminary 1.01 06/01/06 First Version for Board Revision PA6 1.02 09/01/07 Added note for proprietary board designs and errata, general

information update and minor corrections 1.03 19/02/07 Corrected GMODE table

Evaluation Board Revision History Revision Number Date Description of changes

PA5 30/11/05 First Board Version PA5 PA7 13/01/06 Revised version

- adds SW102 for Lime reset - changes thermal pins to VCC18


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CONTENTS

Warranty and Disclaimer..................................................................................2

1 Overview.....................................................................................................5

2 MB86276 ‘Lime’ Features...........................................................................5

3 System Components ..................................................................................6

4 Layout and Interface Location ....................................................................7

5 Power Status LED’s....................................................................................8

6 Configuration DIP Switches ........................................................................9

6.1 CLKSEL0/CLKSEL1 ............................................................................10 6.2 CPU Mode ...........................................................................................10 6.3 General Purpose Mode Pins................................................................11

7 Interfaces and connectors ........................................................................12

7.1 Connectors between CPU board and graphic board ...........................12 7.2 Interface for the digital RGB output .....................................................15 7.3 Interface for LVDS out .........................................................................15 7.4 Interface for the digital RGB input........................................................16 7.5 Interface for the digital YUV422 input ..................................................16

8 Schematic Lime Evaluation Board (PA7)..................................................17

9 Important Notes for Proprietary Board Designs ........................................17

10 Errata ........................................................................................................17

11 Worldwide Headquarters and Disclaimer..................................................18


Revision 1.03 of 18


1 Overview The CREMSON-STARTERKIT-LIME is a low-cost multifunctional evaluation board for Fujitsu’s MB86276 ‘Lime’ Graphic Controller. The board is a part of a modular system and is connected to the ‘CREMSON-STARTERKIT-CPU-Modul’ board as a simple target board for both software development and testing, allowing design engineers to begin with software development immediately before their proprietary (final) target system is available.

2 MB86276 ‘Lime’ Features • CMOS 0.18μm technology

• Internal and memory frequency : 133MHz

• Base-clock for display clocks : 400.9MHz

• Display resolutions typically from 320x240

• 6 layers of overlay display (windows)

• Alpha Plane and constant alpha value

• Digital Video input (various formats

• Video Scaler (up/down scaling)

• Brightness, Contrast, Saturation control

• RGB digital output (8bit x 3)

• Built-in alpha blending, anti-aliasing

• Rendering Engine for various kinds

• Texture Mapping Unit for 2D polygon

• Bit-Blt Unit for transfers up to 4096x4096

• Alpha Bit-Blt and ROP2 functions

• External 32-bit SDRAM interface for

• Parallel host interface (FR, SH3, SH4)

• New additional serial control interface

• Internal and external DMA support

• I2C interface and GPIO inputs/outputs

• Supply voltage 3.3V (I/O), 1.8V (Internal)

• BGA-256 Package (1.27mm pitch)

• Typical power consumption < 1.0W

• Temperature range -40..+85 °C


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3 System Components This diagram provides a functional overview of the system (note that it does not give a true representation of the physical board – e.g. the FPGA device is actually two FPGA’s).

Figure 1 Functional Block Diagram The main components and interfaces of the CREMSON-STARTERKIT-LIME evaluation board:

Lime Graphic Controller 64Mbytes SDRAM Video outputs

o 2 x DVI o 2 x RGB digital o 2 x LVDS

Video inputs o Digital RGB666 o Digital YUV422 (ITU656) o CVBS o S-Video

Others o Xilinx FPGA’s o Test LED’s o Configuration settings


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4 Layout and Interface Location The location of the various interfaces of the board (the outline of which is shown below) is best determined using the current schematics (in this document) and the physical board’s silkscreen markings. Locate the connector’s ID (e.g. X703) in the schematics and then check the silkscreen markings on the physical board.

Figure 1 Interfaces of the Lime evaluation board


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5 Power Status LED’s LED’s are connected to the power nets of the board and therefore an illuminated LED shows the availability of its corresponding power net. The power LED’s are located at the lower right corner of the board, the Reset LED under the external SDRAM and the FPGA power LED near the video input.

LED Function Description

D105

Reset

(Red) Reset level active

D106

1.8V supply

(Green) 1.8V power supply

D107

3.3V supply


D108

5.0V supply


D700

3.3V supply

(Red) 3.3V power supply

Table 1 Power Status LED’s

Figure 2 Power Status LED's


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6 Configuration DIP Switches The table shows DIP switches SW100 and SW101 of the Lime evaluation board. These should be configured according to the intended host CPU interface mode and output display connection. Before connecting the evaluation board for the first time, make sure that all switches are correctly set. Possible settings and defaults are shown below.

Figure 3 Configuration DIP Switches

DIP switch Function Set Description ON Other oscillator settings SW100-1 CLKSEL0 OFF 14.32 MHz source (Default) ON 14.32 MHz source (Default) SW100-2 CLKSEL1 OFF Other oscillator settings ON SW100-3 CPU MODE 0 OFF ON SW100-4 CPU MODE 1 OFF ON SW100-5 CPU MODE 2 OFF

Host CPU mode select¹

ON SW100-6 MUX GMODE 0 OFF ON SW100-7 MUX GMODE 1 OFF ON SW100-8 MUX GMODE 2 OFF

General purpose mode pins²

ON Connects to CPU with BS signal SW100-9 BS Mode OFF Connects to CPU without BS signal ON Sets the XRDY signal to the ‘not ready’ level SW100-10 RDY Mode OFF Sets the XRDY signal to the ‘ready’ level ON Switch On SW101-1 Switching Regulator

shutdown OFF Switch Off ON SW101-2 FPGA configuration OFF

Reserved


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¹,² Check the CPU mode and the General Purpose Mode tables in the hardware manual (see also below). For Hardware Manual cross-reference purposes: (see following sections) ON = Low OFF = High 6.1 CLKSEL0/CLKSEL1 The following table (copied from the MB86276 ‘Lime’ Hardware Manual available at the time this document was written) lists the CLKSEL settings that can be selected.

CLKSEL1 CLKSEL0 Input frequency Assured operation range (*1) L L 13.5 MHz 13.365 to 13.5 MHz

L H 14.32 MHz 14.177 to 14.32 MHz

H L 17.73 Hz 17.553 to 17.73 MHz

H H 33.33 Hz 32.997 to 33.33 MHz

Table 2 Clock Select

*1 Assured operation input frequency range: Standard value –1% 6.2 CPU Mode The following table (copied from the MB86276 ‘Lime’ Hardware Manual available at the time this document was written) lists the CPU modes that can be selected.

CPU MODE 2 CPU MODE 1 CPU MODE 0 CPU L L L SH3 (Fujitsu FR series MCU’s)

L L H SH4

L H L V832

L H H SPARClite

H L L General purpose 16bit CPU with SRAM interface

H L H General purpose 16bit CPU with address and data multiplex interface

H H L General-purpose 32bit CPU with address and data multiplex interface

H H H I2C Slave

Table 3 CPU Modes


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6.3 General Purpose Mode Pins The following table (copied from the MB86276 ‘Lime’ Hardware Manual available at the time this document was written, talking the Errata Sheet nto consideration) lists the General Purpose modes that can be selected and the pin multiplex functionality that results (note also the dependency on the corresponding CPU mode listed in the previous section).

MUX GMODE

2

MUX GMODE

1

MUX GMODE

0 PIN Multiplex

Host Interface Primary RGB output

Secondary RGB output

Video Capture GPIO

L L L 32bit CPU I2C Slave RGB888 -- Native

RGB666 --

L L H 32bit CPU I2C Slave RGB888 -- RBT656/601 GPIO[4:0]

L H L 16bit CPU I2C Slave RGB666 RGB888 RBT656/601 GPIO[2:0]

L H H 16bit CPU

I2C Slave RGB666 RGB666

Native

RGB666 --

H L L Reserved Reserved Reserved Reserved Reserved

H L H Reserved Reserved Reserved Reserved Reserved

H H L Reserved Reserved Reserved Reserved Reserved

H H H Reserved Reserved Reserved Reserved Reserved

Table 4 Multiplex Modes


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7 Interfaces and connectors 7.1 Connectors between CPU board and graphic board This section describes the connector allocation between the CPU board and the graphic board. The connection of the two sub-boards is realized by two connectors: a 96-pole DIN plug and a 48-pole DIN plug.

Figure 3 Connection Block Diagram


Revision 1.03 of 18


Pin Name Pin Name Pin Name A1 n.c. B1 n.c. C1 n.c. A2 3.3V B2 3.3V C2 3.3V A3 5.0V B3 5.0V C3 5.0V A4 GND B4 GND C4 GND A5 D0 B5 D1 C5 D2 A6 D3 B6 D4 C6 D5 A7 D6 B7 D7 C7 D8 A8 D9 B8 D10 C8 D11 A9 D12 B9 D13 C9 D14 A10 D15 B10 D16 C10 D17 A11 D18 B11 D19 C11 D20 A12 D21 B12 D22 C12 D23 A13 D24 B13 D25 C13 D26 A14 D27 B14 D28 C14 D29 A15 D30 B15 D31 C15 GND A16 GND B16 GND C16 GND A17 A0 B17 A1 C17 A2 A18 A3 B18 A4 C18 A5 A19 A6 B19 A7 C19 A8 A20 A9 B20 A10 C20 A11 A21 A12 B21 A13 C21 A14 A22 A15 B22 A16 C22 A17 A23 A18 B23 A19 C23 A20 A24 A21 B24 A22 C24 A23 A25 A24 B25 A25 C25 n.c. A26 n.c. B26 n.c. C26 n.c. A27 n.c. B27 n.c. C27 GND A28 S0 B28 S1 C28 S2 A29 S3 B29 S4 C29 S5 A30 S6 B30 S7 C30 GND A31 n.c. B31 n.c. C31 n.c. A32 GND B32 GND C32 GND

Table 5 96-Pole Connector Pin*¹ Reference


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Pin Name Pin Name Pin Name A1 CS0 B1 GND C1 CS1 A2 CS2 B2 1.8V C2 CS3*2

A3 CS4 B3 GND C3 CS5 A4 CS6 B4 1.8V C4 RDY A5 BGRNT B5 GND C5 BRQ A6 RDX B6 n.c. C6 WR0 A7 WR1 B7 n.c. C7 WR2 A8 WR3 B8 n.c. C8 AS A9 ALE B9 n.c. C9 CLK A10 DREQ0 B10 n.c. C10 DACK0 A11 DEOP0 B11 n.c. C11 n.c. A12 IRQ_A B12 n.c. C12 SDA A13 IRQ_B B13 n.c. C13 SCL A14 SIN B14 n.c. C14 SOT A15 GND B15 n.c. C15 SLK A16 RESET B16 n.c. C16 GND

Table 6 48-Pole Connector Pin*¹ Reference *¹ Note: The pin number refers to the female connector of the CPU main board. *2 Note: CS3: This is currently used by the FR 467 and 369 CPU’s in connection with the Lime device.


Revision 1.03 of 18


7.2 Interface for the digital RGB output

Figure 6 Digital RGB out 7.3 Interface for LVDS out

Figure 7 LVDS out


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7.4 Interface for the digital RGB input

Figure 8 Digital RGB in 7.5 Interface for the digital YUV422 input

RG

B d

igita

l inp

ut

Figure 9 Digital YUV422 (ITU656) input


Revision 1.03 of 18


8 Schematic Lime Evaluation Board (PA7) Please refer to the pages following the Fujitsu Headquarters address information.

9 Important Notes for Proprietary Board Designs

Address line remapping via FPGA Customers who wish to use Lime in legacy 32-bit modes (SH3, SH4, V832, and FR) and may want to simplify the situation by directly mapping Lime's host interface to the host interface connector should be aware that the FPGA on the Starterkit maps the CPU’s address bus lines to those of the Lime device with an offset according to the CPU type. For 16 bit CPU’s the offset is 1 (i.e. line 1 of the address bus is mapped to line 0 of Lime). For 32 bit CPU’s the offset is 2 (i.e. line 2 of the address bus is mapped to line 0 of Lime).

Direct Access to Graphics Memory

If you are trying to access Lime on the Starterkit board from your own CPU board, direct access to graphics memory can be very critical in verifying CPU-Lime communication. Also, if you want to use Local Memory Transfer of display lists to store bitmaps in graphics memory etc. direct access to the Graphics Memory is necessary. This requires modified FPGA firmware which can be obtained by contacting the GCC Application Group ([email protected]).

Using a non-Fujitsu CPU board / Component Initialization via I2C

I2C master communication using the Lime device is not possible for the slave devices SAA7113 and DVI Panel Link Translator. These slave devices should therefore be initialized through I2C using the host interface (i.e. the MCU must control the peripheral directly).

10 Errata Incorrect silkscreen board markings/comments in schematics

The silkscreen description and schematic comments for the settings of SW100 are incorrect for the PA7 version of the board. The table lists the default settings as follows: CLKSEL0 Default ON CLKSEL1 Default OFF The correct settings are: (14.32 MHz) CLKSEL0 Default OFF CLKSEL1 Default ON

mailto:[email protected]


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11 Worldwide Headquarters and Disclaimer

Japan Tel: +81 3 5322 3353 Fax: +81 3 5322 3386

Fujitsu Limited Shinjuku Dai-Ichi Seimei Bldg. 2-7-1, Nishi-shinjuku Shinjuku-ku, Tokyo 163-0721 Japan

Asia Pacific Tel: +65 281 0770 Fax: +65 281 0220

Fujitsu Microelectronics Asia Ltd 151 Lorong Chauan New Tech Park #05-08 Singapore 556741

http://www.fujitsu.com http://www.fujitsu.com/sg/

USA Tel: +1 408 737-5600 Fax: +1 408 737-5999

Fujitsu Microelectronics America Inc. 1250 E. Arques Avenue, M/S 333, Sunnyvale, CA USA 94088-3470 Customer Response Center Mon-Fri 7am-5pm (PST)

Europe Tel: +49 6103 6900 Fax:+49 6103 690122

Fujitsu Microelectronics Europe GmbH Pittlerstrasse 47 D-63225 Langen Germany

http://www.fujitsu.com/us/services/edevices/microelectronics/

http://www.fujitsu.com/emea/services/microelectronics/

The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. No license is granted by implication or otherwise under any patent or patent rights of Fujitsu Microelectronics GmbH. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorisation by Japanese government should be required for export of those products from Japan.

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

RESET#1

I2C[1..0]RESET#1

CONFIG[9..0]

EXT_RESET#

VO0_CLK[3..0]

VO1_CLK[3..0]

RESET#1

VO0_RGB[23..0]

VO0_SYNC[4..0]

VI_656_CLK

I2C[1..0]

RESET#[1..0]

VO1_SYNC[4..0]

VO1_RGB[23..0]VI_656_D[7..0]

FPGA_CFG

Title

Size Document Number Rev

Date: Sheet o f

30200-001 PA8

Fujitsu Lime Evaluation Board

© mycable GmbHBoeker Stieg 43D-24613 AukrugGermanywww.mycable.de

A3

1 11Tuesday, December 12, 2006

Top

Revision: PA8

Top#3

Lime Evaluation Board#2Reference ID: 100

Hierarchy Part References

Lime Evaluation Board

+---#1 Lime Eval Top ¦ +---#2 Power 1xx +---#3 Video Input 2xx +---#4 Video Output +---#5 RGB Output 3xx +---#6 DVI Output 4xx +---#7 LVDS Output 5xx +---#8 Lime Subsystem +---#9 Lime 6xx +---#10 FPGA 7xx +---#11 DRAM 8xx

Power &Config

VideoInput Output

Video

Device Function

I2C Address Map

Ux00 SAA7113 composite video input 0x48 0x49Ux00 XC2S200E* video input selector 0x60 0x61 and host CPU bus muxUx00 SIL164 DVI transmitter #0 0x70 0x71Ux01 SIL164 DVI transmitter #1 0x72 0x73

* I2C address of video input selector depends on FPGA implementation

ReadWrite

Reference ID: 200 #4#8

VO0_RGB[23..0]

VO1_RGB[23..0]

VO1_SYNC[4..0]

VO0_SYNC[4..0]

RESET#1

VO0_CLK[3..0]

VO1_CLK[3..0]

I2C[1..0]

RESET#[1..0]

CONFIG[9..0]

EXT_RESET#

FPGA_CFG

VI_656_D[7..0]

VI_656_CLK

I2C[1..0]

RESET#1

Lime Subsystem

VI_656_D[7..0] VO1_RGB[23..0]

RESET#[1..0]

VO0_SYNC[4..0]

VO1_SYNC[4..0]

VO0_RGB[23..0]

CONFIG[9..0]

VI_656_CLK

I2C[1..0]

VO0_CLK[3..0]

VO1_CLK[3..0]

EXT_RESET#

FPGA_CFG

ATREUB

Note

R402, R412 are not mounted! This is necessary in order to permit the I2C addressing of the SIL164 DVI device.

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CO

NFI

G3

CO

NFI

G0

CO

NFI

G2

CO

NFI

G1

CO

NFI

G5

CO

NFI

G6

CO

NFI

G7

CONFIG[9..0]

CO

NFI

G4

SD33#

CO

NFI

G8

CO

NFI

G9

RESET#0

RESET#1

RESET#1

RESET#0

RESET#0

RESET#[1..0]

RESET#1

PG_VCC18

PG_VCC18

FPG

A_C

FGS

D33

#

FPGA_CFG

EXT_RESET#

CONFIG[9..0]

RESET#[1..0]

EXT_RESET#

FPGA_CFG

VCC50

VCC33

VCC50 VCC33VCC33VCC18 VCC33 VCC33VCC33

VCC_EXT

VCC50VCC33VCC33 VCC33VCC18

VCC50

VCC33

VCC33

VCC33

Title

Size Document Number R ev

Date: Sheet o f

30200-002 PA8

Fujitsu Lime Evaluation Board: Power


A2


Place Cs close topower input! PCB layout: refer to

application note!

Place C126 - C130 directly tothe corresponding U102 pins!

PCB label:3.3V

PCB label:5.0V

PCB label:RESET

PCB label:PG 1.8V

PCB layout: refer toapplication note!

PCB label:Config

PCB label:Supply

1 1940 shutdown off2 FPGA user config n/a

n/a: settings depend on the corresponding host CPU interface mode and display connection

Configswitch #no function default

Supplyswitch #no function default

DIP Switch Settings

If 3.3V and 5V is provided by the host CPU board, bothregulators must be shut down. No wall power supplyshall be connected to the Lime board in this case.

1 CLKSEL0 on2 CLKSEL1 off3 Host CPU MODE 0 n/a4 Host CPU MODE 1 n/a5 Host CPU MODE 2 n/a6 Pin mux GMODE0 n/a7 Pin mux GMODE1 n/a8 Pin mux GMODE2 n/a9 BS Mode n/a10 RDY Mode n/a

22uC120

C107 1n 0603

C11410u D104

MBRM120LT3

10nC128

232kR115

1n

C121

C103

100n 0603

R110390R

110kR116

100nC116

L101 744773047

R112470R

1n

C122

C106 330p

100nC119

LTC2900

U102

LTC2900-1IMS

V31

V12

CRT3

RST#4

VREF 8

VPG 7

GND 6PBR#5

V4 9

V2 10

SW102B3S1000

1 4

2 3

D102

CMDSH-3

D101

MBRM120LT3

C104100n

R106 16k5

22pC115

D100SMAJ18A

309kR109

100nC131

D108TLMC3100

4M7

R108

15kR114

D103

CMDSH-3

R102 0R

100nC126

R103 15k

D106TLMC3100

75k

R117

X100

KLD-SMT2-0202-A

123

SW101506-GDH02S

100nC129

100uC118

SW100506-GDH10S

C111 330p

4k7R118

C113100n

100nC125

4k7

R119

C10810u 1812

TLC7733

U103

TLC7733ID

CONTROL1

RESIN2

CT3

GND4

VDD 8

SENSE 7

RESET 6

RESET# 5

R127 470R

C109100n 0603

F100microSMD110

C1011n 0603

D107TLMC3100

LT1940

U100

LT1940EFE

BOOST11

SW12

VIN13

VIN24

VIN35

FB1 16

VC1 15

PG1 14

RUN/SS1 13

RUN/SS2 12

VIN46

SW27

BOOST28 FB2 9

VC2 10

PG2 11

GN

DU

M

R10510k

C110 1n 0603

NC7SZ125

U104

NC7SZ125

OE1

A2

GND3 Y 4

VCC 5

100nC130

R12510k

93k1

R122

T100MGSF1N02LT1

10kR107

R1204k7

+C100100u

4k7

R123

R111470R

L102 744773033

7447785002L103

R126 110k

R104 15kC112

100n 0603

R100 30k1C1021n 0603

U101

LTC3412EFE

PVIN216

SVIN1

SYNC/MODE6

RT5

ITH3SGND1 8

PGND1 12

PGOOD 2

SW1 10

VFB4

SG

ND

217

SW2 11SW3 14SW4 15

PGND2 13

PVIN19

RUN/SS7

D105TLMT3100

100uC117

4k7R124

L100744226

21

34

R113680R

100p

C123

9k53R121

100nC127

100nC124

C10510u

R10110k

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VI_AI12

VI_AI22

I2C[1..0]

I2C0 I2C_SCL

I2C1 I2C_SDA

VI_656_D0VI_656_D1VI_656_D2VI_656_D3

VI_656_D4VI_656_D5VI_656_D6VI_656_D7

RESET#1

SAA7113_CLK

VI_656_D[7..0]

VI_656_CLK

VI_AI12

VI_AI22

SAA7113_CLK

I2C[1..0]

VI_656_CLK

VI_656_D[7..0]

RESET#1

GND_CV

GND_CV

GND_CVGND_CV GND_CV

GND_CV

GND_CV

VCC33

VCC33

GND_CV

GND_CV

GND_CV

GND_CV

VCC33

GND_CV

Title


Date: Sheet o f

30200-003 PA8

Fujitsu lime Evaluation Board: Video Input


A3


Place RN300, RN301 andR304 directly to thecorresponding U300 pins!

PCB Layout: refer to layout guideand SAA7113 application note!

Place capacitors directlyto digital power pins!

Place filter networkdirectly to VDDAx andVSSAx power pins!

Place R205 directlyto Y200 pin 3!

Keep SAA7113 clock signalas short as possible!

I2C addresses of SAA7113read: 0x49, write: 0x48

New

56RR207

JEITA RC-5231

X2001

2

56RR201

RN200

33Rx4

1234 5

678

33RR202

10kR204

33RR205

47nC216

L303

BLM18PG600SN1

L201

BLM18PG600SN1

BLM18PG600SN1L200

C2121u

1nC208

47nC215

100nC204

47nC202

C214100n

47nC200

X201MDIN04SSV-BC

4

2 1

3

5 6 7

47nC203

RN201

33Rx4

1234 5

678

L202

BLM18PG600SN1

10uC207

OSC

Y200

SG8002 CA PC 24.576

OE 1

GND 2OUT3

VCC4

18RR208

100nC210

18RR206

18RR200

47nC201

10uC211

4k7R203

Video in 1

Video in 2

B oundary Scan

I 2C

Video out

Clo ck

I O

SAA7113H

U200

AI11 4AI1D 5AI12 7

AOUT 9

AI21 43AI2D 44AI22 1

AGND 6

VSSA1 2VSSA2 41

VDDA1 3VDDA2 42

TDI 38TCK 37TMS 39

TRST 8TDO 36

VD

DD

E1

18V

DD

DI

29V

DD

DA

33V

DD

DE

234

VS

SD

E1

16V

SS

DI

28V

SS

DA

30V

SS

DE

235

RTS

026

RTS

127

RTC

025

VD

DA

010

VS

SA

011

CE

40

VPO022VPO121VPO220VPO319VPO415VPO514VPO613VPO712

XTALI32

LLC17

SCL24

SDA23

XTAL31

C213100n

1nC205

100nC206

56RR209

100nC209

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VO0_RGB[23..0]

VO1_RGB[23..0]

VO1_RGBAN[2..0]

VO0_RGBAN[2..0]RESET#1

VO0_RGB[23..0]

VO1_RGB[23..0]

RESET#1

VO0_CLK2

VO1_CLK2

VO1_SYNC[4..0]

VO0_SYNC0VO0_SYNC1VO0_SYNC2

VO1_SYNC0VO1_SYNC1VO1_SYNC2

VO0_SYNC[4..0]

VO1_SYNC[2..0]

VO0_SYNC[2..0]

VO0_CLK[3..0] VO0_CLK[1..0]

VO1_CLK0

VO1_CLK2

VO0_CLK3

VO1_CLK[3..0]

VO0_CLK2

VO1_CLK1

VO0_CLK0VO0_CLK1

VO1_CLK[1..0]

VO1_CLK3

I2C[1..0]

VO0_SYNC0VO0_SYNC1VO0_SYNC2VO0_SYNC3

VO1_SYNC0VO1_SYNC1VO1_SYNC2VO1_SYNC3

VO1_SYNC[3..0]

VO0_SYNC[3..0]

VO0_CLK3

VO1_CLK3

RESET#1

VO0_RGB[23..0]

VO1_RGB[23..0]

I2C[1..0]

VO0_RGB[23..0]

VO1_RGB[23..0]

RESET#1

VO0_SYNC[4..0]

VO1_SYNC[4..0]

VO0_CLK[3..0]

VO1_CLK[3..0]

Title


Date: Sheet o f

30200-004 PA8

Fujitsu Lime Evaluation Board: Video Output


A3


LVDS Output

DVI Output

RGB Output

Reference ID: 500#7

#6 Reference ID: 400

#5 Reference ID: 300

VO0_RGBAN[2..0]

VO1_RGBAN[2..0]

RESET#1

VO1_RGB[23..0]

VO0_RGB[23..0]

VO0_SYNC[4..0]

VO1_SYNC[4..0]

VO0_CLK[1..0]

VO1_CLK[1..0]

I2C[1..0]

VO0_SYNC[3..0]

VO1_SYNC[3..0]

VO0_CLK3

VO1_CLK3

RESET#1

VO0_RGB[23..0]

VO1_RGB[23..0]

VO0_RGBAN[2..0]

VO1_RGBAN[2..0]

I2C[1..0]

VO0_RGB[23..0]

VO1_RGB[23..0]

RESET#1

VO0_SYNC[2..0]

VO1_SYNC[2..0]

VO1_CLK2

VO0_CLK2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VO0_RGBAN2

VO0_RGBAN1

VO0_RGBAN0

VO0_RGB[23..0]

VO0_RGB0 VO0_B0VO0_RGB1 VO0_B1VO0_RGB2 VO0_B2VO0_RGB3 VO0_B3VO0_RGB4 VO0_B4VO0_RGB5 VO0_B5VO0_RGB6 VO0_B6VO0_RGB7 VO0_B7

VO0_RGB8 VO0_G0VO0_RGB9 VO0_G1VO0_RGB10 VO0_G2VO0_RGB11 VO0_G3VO0_RGB12 VO0_G4VO0_RGB13 VO0_G5VO0_RGB14 VO0_G6VO0_RGB15 VO0_G7

VO0_RGB16 VO0_R0VO0_RGB17 VO0_R1VO0_RGB18 VO0_R2VO0_RGB19 VO0_R3VO0_RGB20 VO0_R4VO0_RGB21 VO0_R5VO0_RGB22 VO0_R6VO0_RGB23 VO0_R7

VO0_CSYNC

VO1_RGB0 VO1_B0VO1_RGB1 VO1_B1VO1_RGB2 VO1_B2VO1_RGB3 VO1_B3VO1_RGB4 VO1_B4VO1_RGB5 VO1_B5VO1_RGB6 VO1_B6VO1_RGB7 VO1_B7

VO1_RGB8 VO1_G0VO1_RGB9 VO1_G1VO1_RGB10 VO1_G2VO1_RGB11 VO1_G3VO1_RGB12 VO1_G4VO1_RGB13 VO1_G5VO1_RGB14 VO1_G6VO1_RGB15 VO1_G7

VO1_RGB16 VO1_R0VO1_RGB17 VO1_R1VO1_RGB18 VO1_R2VO1_RGB19 VO1_R3VO1_RGB20 VO1_R4VO1_RGB21 VO1_R5VO1_RGB22 VO1_R6VO1_RGB23 VO1_R7

VO1_RGBAN2

VO1_RGBAN1

VO1_RGBAN0

VO1_RGB[23..0]VO1_RGB[23..0]

VO1_CSYNC

VO1_RGBAN[2..0]

VO0_RGBAN[2..0]

VO0_RGBAN0VO0_BLUEVO0_RGBAN1VO0_GREENVO0_RGBAN2VO0_RED

VO1_RGBAN0VO1_BLUEVO1_RGBAN1VO1_GREEN

VO0_CLK[1..0]

VO0_CLK0VO0_CLK1

VO1_CLK[1..0]

VO1_CLK0VO1_CLK1

VO0_CLK0 VO1_CLK0

VO0_SYNC[4..0]

VO

0_SY

NC

0V

O0_H

SY

NC

VO

0_SY

NC

1V

O0_V

SY

NC

VO

0_SY

NC

2V

O0_D

EV

O0_S

YN

C3

VO

0_CS

YN

CV

O0_S

YN

C4

VO

0_GV

VO1_SYNC[4..0]

VO

1_SY

NC

0V

O1_H

SY

NC

VO

1_SY

NC

1V

O1_V

SY

NC

VO

1_SY

NC

2V

O1_D

EV

O1_S

YN

C3

VO

1_CS

YN

CV

O1_S

YN

C4

VO

1_GV

VO0_B1VO0_B3VO0_B5VO0_B7VO0_G1VO0_G3VO0_G5VO0_G7

VO0_R1VO0_R3VO0_R5VO0_R7VO0_VSYNCVO0_CSYNCVO0_CLK1I2C_SDA


VO0_R0VO0_R2VO0_R4VO0_R6VO0_HSYNCVO0_DEVO0_GVI2C_SCL


VO1_R1VO1_R3VO1_R5VO1_R7VO1_VSYNCVO1_CSYNCVO1_CLK1I2C_SDA


VO1_R0VO1_R2VO1_R4VO1_R6VO1_HSYNCVO1_DEVO1_GVI2C_SCL

I2C[1..0]

I2C0 I2C_SCLI2C1 I2C_SDA

RESET#1

RESET#1 RESET#1

VO1_RED VO1_RGBAN2

VO0_RGB[23..0]

VO0_CLK[1..0]

VO1_RGB[23..0]

VO0_RGBAN[2..0]

VO1_RGBAN[2..0]

VO1_CLK[1..0]

VO0_SYNC[4..0]

VO1_SYNC[4..0]

I2C[1..0]

RESET#1

GND_RGBO

GND_RGBO

GND_RGBO

GND_RGBO

VCC33GND_RGBO

GND_RGBO

GND_RGBO

VCC33

VCC33 VCC33

VCC33 VCC33

Title


Date: Sheet o f

30200-005 PA8

Fujitsu Lime Evaluation Board: Video Output: RGB Output


A2


Place filter network directlyto U500 power pins!

NP

NP


NP

NP

Consider ADV7125 layout rules!

RG

B d

igit

al o

utpu

t #0

RG

B d

igit

al o

utpu

t #1

10kR315

BLM18PG600SN1L301

68RR308

75RR300

100nC314

75RR302

0RR316

100nC310

10uC317

0RR317

X300

FTSH-120-01-L-DV-EJ-P

1 23 45 67 89 10

11 1213 1415 1617 1819 202123 24

22

2527 2829 3031 3233 3435 3637 3839 40

26

470RR309

BLM18PG600SN1L300

L302

BLM18PG600SN1

68RR306

100nC312

100nC306

X301


1 23 45 67 89 10

11 1213 1415 1617 1819 202123 24

22

2527 2829 3031 3233 3435 3637 3839 40

26

100nC302

100nC308

100nC313

100nC311

10kR311

100nC316

75RR304

10kR314

10uC304

470RR307

ADV7125Video DAC

U300

ADV7125JSTZ240

B016B117B218B319B420B521B622B723

G03G14G25G36G47G58G69G710

R041R142R243R344R445R546R647R748

SYNC#12BLANK11CLOCK24

PSAVE#38

IOR 34

IOG 32

IOB 28

IOR# 33

IOG# 31

IOB# 27

VC

C13

VC

C29

VC

C30

GN

D1

GN

D2

GN

D14

GN

D15

GN

D25

GN

D26

GN

D39

GN

D40

RSET 37

COMP 35

VREF 36

10kR310

100nC309

1nC307

10uC315

75RR305

1nC303

100nC305

0RR313

100nC301

75RR303

75RR301

0RR312

10uC300

ADV7125Video DAC

U301

ADV7125JSTZ240

B016B117B218B319B420B521B622B723

G03G14G25G36G47G58G69G710

R041R142R243R344R445R546R647R748

SYNC#12BLANK11CLOCK24

PSAVE#38

IOR 34

IOG 32

IOB 28

IOR# 33

IOG# 31

IOB# 27

VC

C13

VC

C29

VC

C30

GN

D1

GN

D2

GN

D14

GN

D15

GN

D25

GN

D26

GN

D39

GN

D40

RSET 37

COMP 35

VREF 36

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

I2C_SDAI2C_SCL

DVI0_PLLVCC

VO0_TX2MVO0_TX2P

VO0_VSYNCVO0_TX1MVO0_TX1P

VO0_TX0MVO0_TX0P

VO0_TXCPVO0_TXCM

VO0_HSYNC

DVI0_PLLVCC

VO0_

TX1M

VO0_

TX0P

VO0_

TXC

M

VO0_

TX0M

VO0_

TX2M

VO0_

TX2P

VO0_

TXC

P

VO0_

TX1P

DVI0_HTPLG

DVI0_DKEN

DVI0_CTL1

DVI0_ISEL

DVI0_CTL3

DVI0_HTPLGDVI0_PD

DVI1_PDDVI1_ISEL

DVI0_CTL2

RESET#1

DVI0_CTL1

DVI0_CTL2

DVI0_CTL3

VO0_CLK2

VO0_R7VO0_R6VO0_R5

VO0_R3VO0_R2VO0_R1VO0_R0VO0_G7VO0_G6VO0_G5VO0_G4

VO0_R4

VO

0_B

0V

O0_

B1

VO

0_B

2V

O0_

B3

VO

0_B

4V

O0_

B5

VO

0_B

7V

O0_

G0

VO

0_G

1V

O0_

G2

VO

0_G

3

VO

0_B

6

VO0_SYNC[2..0]

VO0_VSYNCVO0_HSYNC

VO0_DE

VO0_SYNC2 VO0_DEVO0_SYNC1 VO0_VSYNCVO0_SYNC0 VO0_HSYNC

VO0_RGB[23..0]

VO

0_C

LK2

VO

0_RG

B0

VO

0_B0

VO

0_RG

B1

VO

0_B1

VO

0_RG

B2

VO

0_B2

VO

0_RG

B3

VO

0_B3

VO

0_RG

B4

VO

0_B4

VO

0_RG

B5

VO

0_B5

VO

0_RG

B6

VO

0_B6

VO

0_RG

B7

VO

0_B7

VO

0_RG

B8

VO

0_G0

VO

0_RG

B9

VO

0_G1

VO

0_RG

B10

VO

0_G2

VO

0_RG

B11

VO

0_G3

VO

0_RG

B12

VO

0_G4

VO

0_RG

B13

VO

0_G5

VO

0_RG

B14

VO

0_G6

VO

0_RG

B15

VO

0_G7

VO

0_RG

B16

VO

0_R0

VO

0_RG

B17

VO

0_R1

VO

0_RG

B18

VO

0_R2

VO

0_RG

B19

VO

0_R3

VO

0_RG

B20

VO

0_R4

VO

0_RG

B21

VO

0_R5

VO

0_RG

B22

VO

0_R6

VO

0_RG

B23

VO

0_R7

DVI1_DKEN

DVI1_CTL3DVI1_CTL2DVI1_CTL1

DVI1_PD

DVI1_ISEL

VO1_REDVO1_GREENVO1_BLUE

VO1_CLK2

VO1_TX2MVO1_TX2P

VO1_VSYNCVO1_TX1MVO1_TX1P

VO1_TX0MVO1_TX0P

VO1_TXCPVO1_TXCM

VO1_HSYNC

RESET#1

VO1_G4

DVI1_PLLVCC

DVI1_CTL1

DVI1_CTL2

DVI1_CTL3

VO1_SYNC2 VO1_DEVO1_SYNC1 VO1_VSYNCVO1_SYNC0 VO1_HSYNC

I2C_SDAI2C_SCL

DVI1_HTPLG

VO

1_C

LK2

VO1_SYNC[2..0]

VO1_VSYNC

DVI1_PLLVCC

VO1_

TXC

M

VO1_

TX0P

VO1_

TX0M

VO1_

TXC

P

VO1_

TX1M

VO1_

TX2M

VO1_

TX1P

VO1_

TX2P

VO1_HSYNC

VO1_DE

DVI1_HTPLG

VO1_G5VO1_G6VO1_G7VO1_R0VO1_R1VO1_R2VO1_R3VO1_R4VO1_R5VO1_R6VO1_R7

VO

1_B

0V

O1_

B1

VO

1_B

2V

O1_

B3

VO

1_B

4V

O1_

B5

VO

1_B

6V

O1_

B7

VO

1_G

0V

O1_

G1

VO

1_G

2V

O1_

G3

VO

1_RG

B14

VO

1_G6

VO

1_RG

B15

VO

1_G7

VO

1_RG

B23

VO

1_R7

VO

1_RG

B19

VO

1_R3

VO

1_RG

B3

VO

1_B3

VO

1_RG

B20

VO

1_R4

VO

1_RG

B12

VO

1_G4

VO

1_RG

B9

VO

1_G1

VO1_RGB[23..0]

VO

1_RG

B17

VO

1_R1

VO

1_RG

B5

VO

1_B5

VO

1_RG

B16

VO

1_R0

VO

1_RG

B10

VO

1_G2

VO

1_RG

B1

VO

1_B1

VO

1_RG

B13

VO

1_G5

VO

1_RG

B21

VO

1_R5

VO

1_RG

B4

VO

1_B4

VO

1_RG

B11

VO

1_G3

VO

1_RG

B0

VO

1_B0

VO

1_RG

B7

VO

1_B7

VO

1_RG

B8

VO

1_G0

VO

1_RG

B2

VO

1_B2

VO

1_RG

B22

VO

1_R6

VO

1_RG

B6

VO

1_B6

VO

1_RG

B18

VO

1_R2

VO0_REDVO0_GREENVO0_BLUE

VO0_RGBAN1 VO0_GREENVO0_RGBAN0 VO0_BLUE

VO0_RGBAN[2..0]

VO0_RGBAN2 VO0_RED

VO1_RGBAN1 VO1_GREENVO1_RGBAN2 VO1_RED

VO1_RGBAN0 VO1_BLUE

VO1_RGBAN[2..0]

I2C[1..0]

I2C0 I2C_SCLI2C1 I2C_SDA

RESET#1

VO0_RGB[23..0]

VO0_CLK2

VO0_SYNC[2..0]

VO1_SYNC[2..0]

VO1_RGB[23..0]

VO1_CLK2

VO0_RGBAN[2..0]

VO1_RGBAN[2..0]

I2C[1..0]

VCC33

VCC33

VCC50

GND_DVI

VCC33

GND_DVI

GND_DVI

VCC33

GND_DVIVCC33

VCC33

VCC33

GND_DVI

VCC50

GND_DVI

VCC33

GND_DVI

VCC33

VCC33

Title


Date: Sheet o f

30200-006 PA8

Fujitsu Lime Evaluation Board: Video Output: DVI Output


A2


NP





Place capacitors directlyto U400 power pins!

Place capacitors directlyto U401 power pins!

Consider SIL164 PCBlayout application note!

Consider SIL164 PCBlayout application note!

I2C addresses of SIL164 #0read: 0x71, write: 0x70

I2C addresses of SIL164 #1read: 0x73, write: 0x72

BLM18PG600SN1L415

100nC426

0RR417

10uC432

BLM18PG600SN1L411

33pC429

BLM18PG600SN1L405

33pC413

100nC408

BLM18PG600SN1L413

10uC422

510RR408

33pC410

1nC407

0RR409

SIL 164 PanelLinkTransmitter

U401

SiI164CT64

VCC11DE2VREF3HSYNC4VSYNC5CTL3/A3/DK36CTL2/A2/DK27CTL1/A1/DK18EDGE/HTPLG9PD10MSEN11VCC212ISEL/RST13DESL/SDA14BSEL/SCL15GND116

PG

ND

17P

VC

C1

18E

XT_

SW

ING

19A

GN

D1

20TX

C-

21TX

C+

22A

VC

C1

23TX

0-24

TX0+

25A

GN

D2

26TX

1-27

TX1+

28A

VC

C2

29TX

2-30

TX2+

31A

GN

D3

32

VCC3 33RESEVED 34DKEN 35D23 36D22 37D21 38D20 39D19 40D18 41D17 42D16 43D15 44D14 45D13 46D12 47GND2 48P

VC

C2

49D

1150

D10

51D

952

D8

53D

754

D6

55ID

CK

-56

IDC

K+

57D

558

D4

59D

360

D2

61D

162

D0

63G

ND

364

0RR412

4k7x4RN400

12345

678

100nC415

100nC401

D400BZX84C3V32

2

11

33

100nC403

BLM18PG600SN1L408

SIL 164 PanelLinkTransmitter

U400

SiI164CT64

VCC11DE2VREF3HSYNC4VSYNC5CTL3/A3/DK36CTL2/A2/DK27CTL1/A1/DK18EDGE/HTPLG9PD10MSEN11VCC212ISEL/RST13DESL/SDA14BSEL/SCL15GND116

PG

ND

17P

VC

C1

18E

XT_

SW

ING

19A

GN

D1

20TX

C-

21TX

C+

22A

VC

C1

23TX

0-24

TX0+

25A

GN

D2

26TX

1-27

TX1+

28A

VC

C2

29TX

2-30

TX2+

31A

GN

D3

32

VCC3 33RESEVED 34DKEN 35D23 36D22 37D21 38D20 39D19 40D18 41D17 42D16 43D15 44D14 45D13 46D12 47GND2 48

PV

CC

249

D11

50D

1051

D9

52D

853

D7

54D

655

IDC

K-

56ID

CK

+57

D5

58D

459

D3

60D

261

D1

62D

063

GN

D3

64

0RR416

220RR411

0RR402

10uC427

33pC428

BLM18PG600SN1L406

BLM18PG600SN1L409

100nC434

0RR415

1nC

417

BLM18PG600SN1L402

390RR410

4k7x4RN401

12345

678 BLM18PG600SN1

L403

510RR418

BLM18PG600SN1L400

33pC405

390RR400

DVIS029T-002BSX401

123456789

1011121314151617181920212223

C1C2C3C4

C5A

24

C5B

4k7x4RN402

12345

678

0RR419

BLM18PG600SN1L414

10uC400

33pC431

10uC414

100nC419

100nC424

0RR407

1nC420

BLM18PG600SN1L407

33pC412

100nC433

0RR414

0RR405

10uC409

BLM18PG600SN1L401

1nC

435

10kR413 BLM18PG600SN1

L412

L416

BLM18PG600SN1

10uC418

0RR406

220RR401

10kR403

33pC423

DVIS029T-002BSX400

123456789

1011121314151617181920212223

C1C2C3C4

C5A

24

C5B

100nC421

33pC430

D401BZX84C3V32

2

11

33

10uC404

BLM18PG600SN1L404

1nC402

100nC406

33pC411

100nC416

BLM18PG600SN1L410

1nC425

0RR404

ATREUB

Note

R402 is not mounted!

ATREUB

Note

R412 is not mounted!

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LVDS_DIS#VO0_CLK3

VO

1_RG

B1

VO

1_B1

VO

1_RG

B2

VO

1_B2

VO

1_RG

B3

VO

1_B3

VO

1_RG

B5

VO

1_B5

VO

1_RG

B6

VO

1_B6

VO

1_RG

B4

VO

1_B4

VO

1_RG

B7

VO

1_B7

VO

1_RG

B9

VO

1_G1

VO

1_RG

B10

VO

1_G2

VO

1_RG

B11

VO

1_G3

VO

1_RG

B8

VO

1_G0

VO

1_RG

B14

VO

1_G6

VO

1_RG

B13

VO

1_G5

VO

1_RG

B15

VO

1_G7

VO

1_RG

B19

VO

1_R3

VO

1_RG

B17

VO

1_R1

VO

1_RG

B18

VO

1_R2

VO

1_RG

B23

VO

1_R7

VO

1_RG

B16

VO

1_R0

VO

1_RG

B21

VO

1_R5

VO

1_RG

B22

VO

1_R6

VO

1_RG

B20

VO

1_R4

VO

1_RG

B12

VO

1_G4

VO1_RGB[23..0]

VO

1_RG

B0

VO

1_B0

VO1_SYNC[3..0]

VO

1_SY

NC

0V

O1_H

SY

NC

VO

1_SY

NC

1V

O1_V

SY

NC

VO

1_SY

NC

2V

O1_D

EV

O1_S

YN

C3

VO

1_CS

YN

C

VO0_CLK3

VO1_CLK3

VO0_DE

VO0_LVDS_3PVO0_LVDS_3MVO0_LVDS_CPVO0_LVDS_CMVO0_LVDS_2PVO0_LVDS_2M

VO0_LVDS_1PVO0_LVDS_1MVO0_LVDS_0PVO0_LVDS_0M

VO0_R6VO0_R0VO0_R1

VO0_R2VO0_R3VO0_R4

VO0_R7VO0_R5VO0_G0

VO0_G1VO0_G2VO0_G6

VO0_G7VO0_G3VO0_G4

VO0_G5

VO0_B6

VO0_B7VO0_B1VO0_B2

VO0_B3VO0_B4VO0_B5

VO0_HSYNCVO0_VSYNC

LVDS_DIS#VO1_CLK3VO1_DE

VO1_LVDS_3PVO1_LVDS_3MVO1_LVDS_CPVO1_LVDS_CM

VO1_LVDS_2M

VO1_LVDS_1PVO1_LVDS_1MVO1_LVDS_0PVO1_LVDS_0M

VO1_R6VO1_R0VO1_R1

VO1_R2VO1_R3VO1_R4

VO1_R7VO1_R5VO1_G0

VO1_G1VO1_G2VO1_G6

VO1_G7VO1_G3VO1_G4

VO1_G5VO1_B0VO1_B6

VO1_B7VO1_B1VO1_B2

VO1_B3VO1_B4VO1_B5

VO1_HSYNCVO1_VSYNC

VO1_LVDS_2P

VO0_LVDS_0M VO0_LVDS_0PVO0_LVDS_1M VO0_LVDS_1PVO0_LVDS_2M VO0_LVDS_2P

VO0_LVDS_CPVO0_LVDS_3P

VO0_LVDS_CMVO0_LVDS_3M

VO1_LVDS_0M VO1_LVDS_0PVO1_LVDS_1M VO1_LVDS_1PVO1_LVDS_2M VO1_LVDS_2P

VO1_LVDS_CPVO1_LVDS_3P

VO1_LVDS_CMVO1_LVDS_3M

RESET#1 LVDS_DIS#

VO

0_RG

B16

VO

0_R0

VO

0_RG

B4

VO

0_B4

VO

0_SY

NC

0V

O0_H

SY

NC

VO

0_RG

B9

VO

0_G1

VO

0_RG

B2

VO

0_B2

VO

0_RG

B23

VO

0_R7

VO0_RGB[23..0]

VO

0_RG

B7

VO

0_B7

VO

0_RG

B13

VO

0_G5

VO

0_RG

B21

VO

0_R5

VO

0_SY

NC

2V

O0_D

E

VO

0_RG

B18

VO

0_R2

VO0_B0

VO

0_RG

B0

VO

0_B0

VO

0_RG

B19

VO

0_R3

VO

0_RG

B1

VO

0_B1

VO

0_SY

NC

3V

O0_C

SY

NC

VO

0_RG

B5

VO

0_B5

VO

0_RG

B14

VO

0_G6

VO

0_RG

B10

VO

0_G2

VO

0_SY

NC

1V

O0_V

SY

NC

VO

0_RG

B12

VO

0_G4

VO

0_RG

B8

VO

0_G0

VO

0_RG

B22

VO

0_R6

VO

0_RG

B20

VO

0_R4

VO0_SYNC[3..0]

VO

0_RG

B3

VO

0_B3

VO

0_RG

B6

VO

0_B6

VO

0_RG

B15

VO

0_G7

VO

0_RG

B17

VO

0_R1

VO

0_RG

B11

VO

0_G3

VO0_CSYNC

VO1_CSYNC

VO0_RGB[23..0]

VO1_RGB[23..0]

VO0_SYNC[3..0]

VO1_SYNC[3..0]

VO0_CLK3

VO1_CLK3

RESET#1

VCC33

VCC33

VCC33

GND_LVDS

GND_LVDS

VCC33

VCC33

GND_LVDS

VCC33

GND_LVDS

VCC33

GND_LVDS

VCC33

VCC33

Title


Date: Sheet o f

30200-007 PA8

Fujitsu Lime Evaluation Board: Video Output: LVDS Output


A2


Place filter directlyto PLL power pins!


Place capacitors directlyto LVDS power pins!

Place capacitors directlyto LVDS power pins!

Place filter directlyto PLL power pins!


NP

NP

BLM18PG600SN1L502

100nC503

100nC521

1nC500

R502 0R

100nC510

100nC512

10uC519

R501

0R

BLM18PG600SN1L500

10uC508

10uC515

100nC520

R504 0R

10uC513

R50010k

1nC516

R5030R

100nC509

1nC505

R5050R

100nC514

DS90CR285

TransmitterChannel Link

U500

DS90CR285MTD

TXIN52 VCC11

TXIN63TXIN74GND15TXIN86TXIN97TXIN108VCC29TXIN1110TXIN1211TXIN1312GND213TXIN1414TXIN1515TXIN1616VCC317TXIN1718TXIN1819TXIN1920GND321TXIN2022TXIN2123TXIN2224TXIN2325VCC426TXIN2427TXIN2528 GND4 29TXIN26 30TXCLKIN 31PWRDWN 32PLLGND1 33PLLVCC 34PLLGND2 35LVDSGND1 36TXOUT3_P 37TXOUT3_M 38TXCLKOUT_P 39TXCLKOUT_M 40TXOUT2_P 41TXOUT2_M 42LVDSGND2 43

TXOUT0_P 47TXOUT1_M 46TXOUT1_P 45LVDSVCC 44

TXOUT0_M 48LVDSGND3 49TXIN27 50TXIN0 51TXIN1 52GND5 53TXIN2 54TXIN3 55TXIN4 56

100nC518

100nC501

10uC504

DS90CR285

TransmitterChannel Link

U501

DS90CR285MTD

TXIN52 VCC11

TXIN63TXIN74GND15TXIN86TXIN97TXIN108VCC29TXIN1110TXIN1211TXIN1312GND213TXIN1414TXIN1515TXIN1616VCC317TXIN1718TXIN1819TXIN1920GND321TXIN2022TXIN2123TXIN2224TXIN2325VCC426TXIN2427TXIN2528 GND4 29TXIN26 30TXCLKIN 31PWRDWN 32PLLGND1 33PLLVCC 34PLLGND2 35LVDSGND1 36TXOUT3_P 37TXOUT3_M 38TXCLKOUT_P 39TXCLKOUT_M 40TXOUT2_P 41TXOUT2_M 42LVDSGND2 43

TXOUT0_P 47TXOUT1_M 46TXOUT1_P 45LVDSVCC 44

TXOUT0_M 48LVDSGND3 49TXIN27 50TXIN0 51TXIN1 52GND5 53TXIN2 54TXIN3 55TXIN4 56

X500

FTSH-108-01-L-DV-P

1 23 45 67 89 10

11 1213 1415 16

100nC507

100nC517

L501

BLM18PG600SN1

1nC511

X501

FTSH-108-01-L-DV-P

1 23 45 67 89 10

11 1213 1415 16

10uC502

100nC506

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SDD[31..0]

SDCAS#

SDWE#

SDQM#[3..0]

SDA[14..0]

SDRAS#

SDCLK[1..0]

I2C[1..0]

RESET#1

CONFIG[9..0]

RESET#[1..0]

RESET#0

VO_D[23..0]

VO_DCLKO

VO0_SYNC[4..0]

VO0_CLK[3..0]

VO_DCLKI

VO1_CLK[3..0] LIME_D[31..0]

LIME_A[23..0]

VI_656_D[7..0]

VO1_SYNC[4..0]

VI_656_CLK

I2C[1..0]

VI_SYNC[3..0]

VO0_RGB[23..0]

FPGA_CLK

VO_SYNC[4..0]

VI_D[17..0]

CPU_CLK

RESET#0VO1_RGB[23..0]

LIME_CTRL[11..0]

EXT_RESET#

FPGA_CFG

RESET#[1..0]

CONFIG[9..0]

I2C[1..0]

VI_656_D[7..0]

VI_656_CLK

VO0_CLK[3..0]

VO1_CLK[3..0]

VO0_SYNC[4..0]

VO1_SYNC[4..0]

VO0_RGB[23..0]

VO1_RGB[23..0]

EXT_RESET#

FPGA_CFG

Title


Date: Sheet o f

30200-008 PA8

Fujitsu Lime Evaluation Board: Lime Subsystem


A3


Reference ID: 8xxReference ID: 6xx #9#10Reference ID: 7xx

I2C

, con

fig,

rese

tVi

deo

inpu

tVi

deo

outp

utH

ost C

PUin

terf

ace

#11

SDRAM

SDR

AM

Bus Multiplexer &Video I/O Switch

SDQM#[3..0]

SDD[31..0]

SDA[14..0]

SDCLK[1..0]

SDCAS#

SDRAS#

SDWE#

Lime

SDA[14..0]

SDD[31..0]

SDQM#[3..0]LIME_A[23..0]

LIME_CTRL[11..0]

RESET#[1..0]

I2C[1..0]

LIME_D[31..0]

VI_D[17..0]

SDCLK[1..0]

SDCAS#

SDRAS#

SDWE#CPU_CLK

CONFIG[9..0]

VO_DCLKI

VO_DCLKO

VO_D[23..0]

VO_SYNC[4..0]

VI_SYNC[3..0]

FPGA_CLK

FPGA

LIME_A[23..0]

LIME_CTRL[11..0]

LIME_D[31..0]

RESET#0

I2C[1..0]

VI_656_D[7..0]

VI_656_CLK

CPU_CLK

VO_DCLKI

VO_DCLKO

VO_D[23..0]

VO_SYNC[4..0]

VI_D[17..0]

VI_SYNC[3..0]

FPGA_CLK

VO0_CLK[3..0]

VO1_CLK[3..0]

VO0_SYNC[4..0]

VO1_SYNC[4..0]

VO0_RGB[23..0]

VO1_RGB[23..0]

EXT_RESET#

CONFIG[9..0]

FPGA_CFG

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SDD[31..0]

SDA[14..0]

SDQM#[3..0]

I2C[1..0]

CONFIG[9..0]

RESET#[1..0]

RESET#0RESET#1

SDQM#3SDQM#2SDQM#1SDQM#0

SDWE#

SDRAS#

SDCAS#

SDCLK[1..0]

SDCLK0

SDCLK1

SDA14

SDA0

SDA13

SDA1

SDA4SDA3

SDA6SDA5

SDA8SDA7

SDA10SDA9

SDA12SDA11

SDA2

SDD14

SDD0

SDD13

SDD1

SDD4SDD3

SDD6SDD5

SDD8SDD7

SDD10SDD9

SDD12SDD11

SDD2

SDD29

SDD15

SDD28

SDD16

SDD19SDD18

SDD21SDD20

SDD23SDD22

SDD25SDD24

SDD27SDD26

SDD17

SDD31SDD30

VI_SYNC[3..0]

LIME_CLK_EN

LIME_CLK

LIME_DREQ

LIME_GMODE0LIME_GMODE1LIME_GMODE2

RESET#1CONFIG3 LIME_MODE1

CONFIG0 LIME_CLKSEL0

CONFIG6 LIME_GMODE1

CONFIG8 LIME_BS_MODECONFIG9 LIME_RDY_MODE

CONFIG1 LIME_CLKSEL1CONFIG2 LIME_MODE0

CONFIG4 LIME_MODE2CONFIG5 LIME_GMODE0

CONFIG7 LIME_GMODE2

I2C1 I2C_SDAI2C0 I2C_SCL

LIM

E_X

RD

YLI

ME

_XIN

T

CPU_CLK

LIME_A[23..0]

LIME_D[31..0]

LIME_CTRL5 LIME_XWE3

LIME_CTRL1 LIME_RDLIME_CTRL0 LIME_XCS

LIME_CTRL6 LIME_XRDY

LIME_CTRL11 LIME_XINT


LIME_CTRL7 LIME_XBSLIME_CTRL8 LIME_DREQ


LIME_CTRL[11..0]

LIME_CTRL9 LIME_DTACK


LIME_CTRL10 LIME_RACK

LIM

E_X

CS

LIM

E_R

DLI

ME

_XBS

LIM

E_D

TAC

K

LIM

E_R

AC

KLI

ME

_CLK

_EN

I2C

_SC

LI2

C_S

DA

LIM

E_X

WE

0LI

ME

_XW

E1

LIM

E_X

WE

2LI

ME

_XW

E3

FPGA_CLK

LIME_A5

LIME_A23

LIME_A12

LIME_A9

LIME_A19

LIME_A3

LIME_A15

LIME_A10

LIME_A4

LIME_A22

LIME_A6

LIME_A0

LIME_A14

LIME_A7

LIME_A20

LIME_A17

LIME_A1

LIME_A21

LIME_A2

LIME_A13

LIME_A16

LIME_A18

LIME_A11

LIME_A8

LIME_D9

LIME_D4

LIME_D13LIME_D14

LIME_D29

LIME_D15

LIME_D25

LIME_D1

LIME_D6

LIME_D8

LIME_D21

LIME_D26

LIME_D7

LIME_D12

LIME_D24

LIME_D22

LIME_D11

LIME_D27

LIME_D18LIME_D19

LIME_D2

LIME_D17

LIME_D20

LIME_D3

LIME_D28

LIME_D30

LIME_D23

LIME_D10

LIME_D31

LIME_D5

LIME_D0

LIME_D16

CPU_CLKLIME_D31LIME_D30LIME_D29LIME_D28LIME_D27LIME_D26LIME_D25LIME_D24LIME_D23LIME_D22LIME_D21LIME_D20LIME_D19LIME_D18LIME_D17LIME_D16

LIME_D6LIME_D5LIME_D4LIME_D3LIME_D2LIME_D1LIME_D0

LIME_D15LIME_D14LIME_D13LIME_D12LIME_D11LIME_D10LIME_D9LIME_D8LIME_D7

LIME_CLK LIME_CLKCPU_CLKLIME_XBSLIME_XRDYLIME_XWE3LIME_XWE2

LIME_XWE0LIME_RD

LIME_XWE1

LIME_XCS

LIME_A22LIME_A21

LIME_A23

LIME_A20

LIME_A18LIME_A17

LIME_A19

LIME_A16

LIME_A10LIME_A9

LIME_A11

LIME_A8

LIME_A6LIME_A5

LIME_A7

LIME_A4

LIME_A2LIME_A1

LIME_A3

LIME_A0

LIME_A15LIME_A14LIME_A13LIME_A12

L_VO_DLCKOVI_R3VI_R2VI_R1VI_R0VI_G5VI_G4VI_G3VI_G2VI_G1VI_G0VI_B5VI_B4VI_B3VI_B2VI_B1VI_B0

L_VO_DISPEL_VO_VSYNCL_VO_HSYNCVIN_FIDVIN_VSYNCVIN_ HSYNCRESET#1RESET#0I2C_SDAI2C_SCLLIME_XINTLIME_RACKLIME_DTACKLIME_DREQ

VIN_RGBCKL_VO_GVL_VO_CSYNC

LIME_D16LIME_D17LIME_D18LIME_D19




LIME_D0

LIME_D2LIME_D1

LIME_D3LIME_D4LIME_D5LIME_D6LIME_D7LIME_D8LIME_D9LIME_D10LIME_D11LIME_D12LIME_D13LIME_D14LIME_D15

LIME_A0LIME_A1LIME_A2LIME_A3LIME_A4LIME_A5LIME_A6LIME_A7LIME_A8LIME_A9LIME_A10LIME_A11LIME_A12LIME_A13LIME_A14LIME_A15LIME_A16LIME_A17LIME_A18LIME_A19LIME_A20LIME_A21LIME_A22LIME_A23

LIME_XWE0

LIME_XWE2LIME_XWE1

LIME_XWE3

LIME_XBS

LIME_RDLIME_XCS

LIME_XINTLIME_XRDYCPU_CLKLIME_DTACK

LIME_RACK

LIME_MODE0LIME_MODE1LIME_MODE2

LIME_BS_MODELIME_RDY_MODE

LIME_CLK

LIME_CLKSEL1LIME_CLKSEL0RESET#0

I2C_SCLI2C_SDA

VIN_FID V I_SYNC3VIN_RGBCK V I_SYNC0VIN_ HSYNC V I_SYNC1VIN_VSYNC V I_SYNC2

VO_D2VO_B2

L_VO_R3

VO_SYNC4VO_GV

VO_D5VO_B5

VO_D17VO_R1

VO_D[23..0]

L_VO_R6

L_VO_R1

L_VO_CSYNC

VO_D8VO_G0

L_VO_B2

L_VO_B7

VO_D21VO_R5

L_VO_GV

VO_SYNC2VO_DE

L_VO_G5L_VO_G4

L_VO_B3

VO_D23VO_R7

L_VO_G3

L_VO_G6

VO_D20VO_R4

L_VO_R0

VO_D10VO_G2L_VO_G2

L_VO_B6

VO_D16VO_R0

VO_SYNC[4..0]

L_VO_B5

L_VO_R5

VO_D0VO_B0

L_VO_R2

L_VO_B4

VO_D6VO_B6

VO_D18VO_R2

L_VO_G0

L_VO_G7

VO_D13VO_G5

VO_D22VO_R6L_VO_R7

VO_D1VO_B1

L_VO_HSYNCL_VO_VSYNC

VO_D9VO_G1L_VO_G1

L_VO_B1L_VO_B0

VO_D4VO_B4

VO_SYNC1VO_VSYNC

L_VO_DLCKO

L_VO_R4

VO_D7VO_B7

VO_SYNC3VO_CSYNCL_VO_DISPE

VO_D11VO_G3

VO_D14VO_G6

VO_D12VO_G4

VO_D15VO_G7

VO_D3VO_B3

VO_D19VO_R3

VO_SYNC0VO_HSYNC

L_V

O_B

7

L_V

O_R

0L_

VO

_R1

L_V

O_R

2L_

VO

_R3

L_V

O_R

4L_

VO

_R5

L_V

O_R

6L_

VO

_R7

L_V

O_G

0L_

VO

_G1

L_V

O_G

2L_

VO

_G3

L_V

O_G

4L_

VO

_G5

L_V

O_G

6L_

VO

_G7

L_V

O_B

0L_

VO

_B1

L_V

O_B

2L_

VO

_B3

L_V

O_B

4L_

VO

_B5

L_V

O_B

6

L_V

O_V

SY

NC

L_V

O_H

SY

NC

VO

_DC

LKI

L_V

O_D

LCK

OL_

VO

_CS

YN

C

V I_D16VI_R4VI_D15VI_R3

L_V

I_R

4

V I_D14VI_R2

L_V

I_R

5

V I_D13VI_R1VI_D12VI_R0

VI_D5VI_B5VI_D4VI_B4VI_D3VI_B3VI_D2VI_B2VI_D1VI_B1

VI_D10VI_G4VI_D9VI_G3VI_D8VI_G2VI_D7VI_G1VI_D6VI_G0

VI_D0VI_B0VI_D11VI_G5

L_VI_R5

L_VI_R4

VI_D17VI_R5

VI_D[17..0]

VO_DCLKI

VO_DCLKO

L_V

O_G

VL_

VO

_DIS

PE

SDD[31..0]

SDA[14..0]

SDQM#[3..0]

LIME_CTRL[11..0]

I2C[1..0]

CONFIG[9..0]

RESET#[1..0]

SDWE#

SDRAS#

SDCAS#

SDCLK[1..0]

VI_SYNC[3..0]

CPU_CLK

LIME_A[23..0]

LIME_D[31..0]

FPGA_CLK

VO_D[23..0]

VO_SYNC[4..0]

VI_D[17..0]

VO_DCLKO

VO_DCLKI

VCC18VCC18VCC33

VCC33

VCC33

VCC33

VCC33

VCC18

Title


Date: Sheet o f

30200-009 PA8

Fujitsu Lime Evaluation Board: Lime Subsystem: Lime


A1


Place filter networkdirectly to Lime PLLpower pins!

PCB layout tobe clarified!

Place R820 and R8yydirectly to Y800 pin 3!

NP

PCB Label:Lime Data

PCB Label:Lime Addr/Ctrl

PCB Label:Lime Ctrl/Sync/Vin

R601 33RRN

603

10kx

4

1 2 3 45678

100nC605

RN614

10kx4

1234 5

678

1nC601

C620100n

R6024k7

L601

BLM18PG600SN1

RN612

33Rx4

1234 5

678

RN

604

10kx

4

1 2 3 45678

1nC615

100nC611

R605 33R

10uC607

10uC613

RN617 33Rx41234 5

678

RN

602

10kx

4

1 2 3 45678

R6060R

RN615 33Rx41234 5

678

10uC608

OSC

Y600

SG8002 CA PC 14.320

OE 1

GND 2OUT3

VCC4

1nC600

R608 33R

10uC617

RN613

33Rx4

1234 5

678

MSB

LSB

AMPMICTOR 38

X602

39 4340 41 42

1 23 45 67 89 10

11 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 38

BLM18PG600SN1L600

100nC604

R610 33R

10uC614

R611 33R

RN607

33Rx4

1234 5

678

100nC612

RN609

33Rx4

1234 5

678

R603 33R

RN

600

10kx

4

1 2 3 45678

10uC609

R613 0R

RN

601

10kx

4

1 2 3 45678

R607 33R

RN610

33Rx4

1234 5

678

RN611

33Rx4

1234 5

678

100nC603

100nC602

R612 33R

RN618 33Rx41234 5

678

R609 33R

RN

605

10kx

4

1 2 3 45678

100nC606

C618100n

RN616 33Rx41234 5

678

MB86276LIME

SyncVideo Out Video In

Test

Frame Buffer Interface

Host Interface

Power

I2C

U600AMB86276

VD

DE

_0E

4V

DD

E_1

F4V

DD

E_2

H4

VD

DE

_3J4

VD

DE

_4L4

VD

DE

_5M

4V

DD

E_6

N4

VD

DE

_7R

4V

DD

E_8

T4V

DD

E_9

U5

VD

DE

_10

U6

VD

DE

_11

U12

VD

DE

_12

U13

VD

DE

_13

U15

VD

DE

_14

U16

VD

DE

_15

T17

VD

DE

_16

R17

VD

DE

_17

N17

VD

DE

_18

M17

VD

DE

_19

K17

VD

DE

_20

J17

VD

DE

_21

H17

VD

DE

_22

F17

VD

DE

_23

E17

VD

DE

_24

D16

VD

DE

_25

D15

VD

DE

_26

D9

VD

DE

_27

D8

VD

DE

_28

D6

VD

DE

_29

D5

PLL

VS

SU

8P

LLV

DD

U9

RI1

B8

RI2

C8

RI3

A9

RI4

B9

RI5

C9

MCLKO V1MCLKI T1

VIN

FID

A2

VIN

VS

YN

CA

3V

INH

SY

NC

B3

RG

BC

KB

1

XPLLTEST C1XTST C2XSM D1

GMODE0 B20GMODE1 C19GMODE2 C20

BO

1B

11B

O2

C11

BO

3D

11B

O4

A10

BO

5B

10B

O6

C10

BO

7D

10

RI0

A8

MD1 E2MD2 E3MD3 F1MD4 F2MD5 F3MD6 G1MD7 G2MD8 G3MD9 H1

MD10 H2MD11 H3MD12 J1MD13 J2MD14 J3MD15 K1MD16 K2MD17 K3MD18 K4MD19 L1MD20 L2MD21 L3MD22 M1MD23 M2MD24 M3MD25 N1MD26 N2MD27 N3MD28 P1MD29 P2MD30 P3MD31 R1

MCAS Y7MRAS V6MWE W7

MDQM0 R2MDQM1 R3MDQM2 T2MDQM3 T3

MD0 E1

MA0 U2MA1 U3MA2 V2MA3 W1MA4 Y2MA5 Y3MA6 W3MA7 Y4MA8 W4MA9 V4

MA10 Y5MA11 W5MA12 V5MA13 Y6MA14 W6

D0P19D1P18D2N20D3N19D4N18D5M20D6M19D7M18D8L20D9L19D10L18D11L17D12K20D13K19D14K18D15J20D16J19D17J18D18H20D19H19D20H18D21G20D22G19D23G18D24F20D25F19D26F18D27E20D28E19D29E18D30D20D31D19

A0W13A1V13A2Y14A3W14A4V14A5Y15A6W15A7V15A8Y16A9W16A10V16A11Y17A12W17A13V17A14Y18A15W18A16Y19A17W20A18V20A19V19A20U20A21U19A22U18A23T20

CLKSEL0V7CLKSEL1V9CKMW8CLKY8

SW9

RDY_MODEW10BS_MODEV10MODE0U10MODE1Y11MODE2W11

XRDYV11XINTU11

DREQY12

BCLKIY10

XCSW12XRDV12

XBSY13

XWE0T19XWE1T18XWE2R20XWE3R19

DTACKR18

DRACKP20

XRSTV8

BI0

A4

BI1

B4

BI2

C4

BI3

A5

BI4

B5

BI5

C5

GI0

A6

GI1

B6

GI2

C6

GI3

A7

GI4

B7

GI5

C7

RO

0B

16R

O1

C16

RO

2A

15R

O3

B15

RO

4C

15R

O5

A14

RO

6B

14R

O7

C14

GO

0A

13G

O1

B13

GO

2C

13G

O3

D13

GO

4A

12G

O5

B12

GO

6C

12G

O7

D12

BO

0A

11

CS

YN

CB

18G

VD

18D

ISP

EC

17

VS

YN

CA

19H

SY

NC

B17

DC

LKI

A18

DC

LKO

A16

SCL D2SDA D3

VS

S_0

A1

VS

S_1

U1

VS

S_2

Y1

VS

S_3

Y9

VS

S_4

A20

VS

S_5

A17

VS

S_6

B2

VS

S_7

W2

VS

S_8

W19

VS

S_9

B19

VS

S_1

0C

3V

SS

_11

V3

VS

S_1

2V

18V

SS

_13

C18

VS

S_1

4D

4V

SS

_15

U4

VS

S_1

6U

17V

SS

_17

D17

VD

DI_

0G

4V

DD

I_1

P4

VD

DI_

2U

7V

DD

I_3

U14

VD

DI_

4P

17V

DD

I_5

G17

VD

DI_

6D

14V

DD

I_7

D7

VS

S_1

8Y

20

MSB

LSB

AMPMICTOR 38

X600

39 4340 41 42

1 23 45 67 89 10

11 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 38

100nC616

MSB

LSB

AMPMICTOR 38

X601

39 4340 41 42

1 23 45 67 89 10

11 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 38

RN606 33Rx41234 5

678

1nC610

C6191u

RN608

33Rx4

1234 5

678

Thermal pins of LIME

U600BMB86276

VD

DI_

8G

7

VS

S_1

9G

8V

SS

_20

G9

VS

S_2

1G

10V

SS

_22

G11

VS

S_2

3G

12V

SS

_24

G13

VS

S_2

5G

14

VD

DI_

9H

7

VS

S_2

6H

8V

SS

_27

H9

VS

S_2

8H

10V

SS

_29

H11

VS

S_3

0H

12V

SS

_31

H13

VS

S_3

2H

14

VD

DI_

10J7

VS

S_3

3J8

VS

S_3

4J9

VS

S_3

5J1

0V

SS

_36

J11

VS

S_3

7J1

2V

SS

_38

J13

VS

S_3

9J1

4

VD

DI_

11K

7

VS

S_4

0K

8V

SS

_41

K9

VS

S_4

2K

10V

SS

_43

K11

VS

S_4

4K

12V

SS

_45

K13

VS

S_4

6K

14

VD

DI_

12L7

VS

S_4

7L8

VS

S_4

8L9

VS

S_4

9L1

0V

SS

_50

L11

VS

S_5

1L1

2V

SS

_52

L13

VS

S_5

3L1

4

VD

DI_

13M

7

VS

S_5

4M

8V

SS

_55

M9

VS

S_5

6M

10V

SS

_57

M11

VS

S_5

8M

12V

SS

_59

M13

VS

S_6

0M

14

VD

DI_

14N

7

VS

S_6

1N

8V

SS

_62

N9

VS

S_6

3N

10V

SS

_64

N11

VS

S_6

5N

12V

SS

_66

N13

VS

S_6

7N

14

VD

DI_

15P

7V

DD

I_16

P8

VD

DI_

17P

9V

DD

I_18

P10

VD

DI_

19P

11

VS

S_6

8P

12V

SS

_69

P13

VS

S_7

0P

14

R600 33R

R604 33R

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

EXT_VI_RGB_HSYNC

VI_RGB_D0VI_RGB_D2VI_RGB_D4

VI_RGB_D1VI_RGB_D3VI_RGB_D5VI_RGB_D7

EXT_VI_RGB_VSYNC

EXT_VI_RGB_CLK

VO0_CLK

VO0_CLK[3..0]

VO0_CLK0

VO0_CLK1

VO0_CLK2

VO0_CLK3

VO1_CLK

VO1_CLK[3..0]

VO1_CLK0

VO1_CLK1

VO1_CLK2

VO1_CLK3

TDO_FPGA2

TDO

_FP

GA

1

FP

GA

_CC

LK

JTAG_TCKJTAG_TMS

RESET#0

VI2_656_D0VI2_656_D1VI2_656_D2VI2_656_D3VI2_656_D4VI2_656_D5VI2_656_D6VI2_656_D7VI2_656_CLKVI2_656_HSYNC

VI2_656_VSYNC

VI2_656_CLK

VI_656_CLK

EXT_VI_RGB_VSYNC

EXT_VI_RGB_HSYNC

VI2_656_D7

VO0_B4VO0_B5VO0_B6VO0_B7


VO0_G4VO0_G5VO0_G6VO0_G7


VO0_R4VO0_R5VO0_R6VO0_R7


EXT_VI_RGB_CLK

VI_RGB_D0 EXT_VI_B0VI_RGB_D1 EXT_VI_B1VI_RGB_D2 EXT_VI_B2VI_RGB_D3 EXT_VI_B3VI_RGB_D4 EXT_VI_B4VI_RGB_D5 EXT_VI_B5VI_RGB_D6 EXT_VI_G0VI_RGB_D7 EXT_VI_G1VI_RGB_D8 EXT_VI_G2VI_RGB_D9 EXT_VI_G3VI_RGB_D10 EXT_VI_G4VI_RGB_D11 EXT_VI_G5VI_RGB_D12 EXT_VI_R0VI_RGB_D13 EXT_VI_R1VI_RGB_D14 EXT_VI_R2VI_RGB_D15 EXT_VI_R3VI_RGB_D16 EXT_VI_R4VI_RGB_D17 EXT_VI_R5

VI_RGB_D9VI_RGB_D11VI_RGB_D13VI_RGB_D15VI_RGB_D17

VI_RGB_D6VI_RGB_D8VI_RGB_D10VI_RGB_D12VI_RGB_D14VI_RGB_D16

VO_DCLKO

VO_D6

VO_D4

VO_D3VO_D2

VI2_656_D6VI2_656_D5VI2_656_D4

VI2_656_D3VI2_656_D2VI2_656_D1VI2_656_D0

VI_656_D7

VI_656_D5

VI_656_D3

VI_656_D0

VO_D22VO_D21

VO_D19

VO_D17VO_D16

VO_D14

VO_D12

VO_D7

VO1_CLK

VO1_HSYNC

VO1_VSYNCVO1_DEVO1_CSYNCVO1_GV


VO0_CLK

VO0_HSYNC

VO0_VSYNCVO0_DEVO0_CSYNCVO0_GV


VO1_B4

VO1_B7



VO1_B6VO1_B5


VO_DCLKI

LIME_CLKSEL0

LIME_CLKSEL1

LIME_GMODE0

LIME_GMODE1

LIME_GMODE2

RESET#0

RESET#0

VO_DCLKO

VI_656_CLK

I2C[1..0]

VO_D[23..0]

VO_D1VO_D0

VO_D5

VO_D9VO_D10VO_D11

VO_D8

VO_D13

VO_D15

VO_D18

VO_D23

VO_D20

VI_656_D1VI_656_D2

VI_656_D4

VI_656_D6

VI_656_D[7..0]

VO_SYNC0 VO_HSYNC

VO_SYNC2 VO_DEVO_SYNC1 VO_VSYNC

VO_SYNC3 VO_CSYNC

VO_SYNC[4..0]

VO_SYNC4 VO_GV

VO0_RGB[23..0]

VO

0_R

GB

0V

O0_

B0

VO

0_R

GB

1V

O0_

B1

VO

0_R

GB

2V

O0_

B2

VO

0_R

GB

3V

O0_

B3

VO

0_R

GB

4V

O0_

B4

VO

0_R

GB

5V

O0_

B5

VO

0_R

GB

6V

O0_

B6

VO

0_R

GB

7V

O0_

B7

VO

0_R

GB

8V

O0_

G0

VO

0_R

GB

9V

O0_

G1

VO

0_R

GB

10V

O0_

G2

VO

0_R

GB

11V

O0_

G3

VO

0_R

GB

12V

O0_

G4

VO

0_R

GB

13V

O0_

G5

VO

0_R

GB

14V

O0_

G6

VO

0_R

GB

15V

O0_

G7

VO

0_R

GB

16V

O0_

R0

VO

0_R

GB

17V

O0_

R1

VO

0_R

GB

18V

O0_

R2

VO

0_R

GB

19V

O0_

R3

VO

0_R

GB

20V

O0_

R4

VO

0_R

GB

21V

O0_

R5

VO

0_R

GB

22V

O0_

R6

VO

0_R

GB

23V

O0_

R7

VO

1_R

GB

23V

O1_

R7

VO1_RGB[23..0]

VO1_RGB[23..0]

VO

1_R

GB

22V

O1_

R6

VO

1_R

GB

21V

O1_

R5

VO

1_R

GB

20V

O1_

R4

VO

1_R

GB

19V

O1_

R3

VO

1_R

GB

18V

O1_

R2

VO

1_R

GB

17V

O1_

R1

VO

1_R

GB

16V

O1_

R0

VO

1_R

GB

15V

O1_

G7

VO

1_R

GB

14V

O1_

G6

VO

1_R

GB

13V

O1_

G5

VO

1_R

GB

12V

O1_

G4

VO

1_R

GB

11V

O1_

G3

VO

1_R

GB

10V

O1_

G2

VO

1_R

GB

9V

O1_

G1

VO

1_R

GB

8V

O1_

G0

VO

1_R

GB

7V

O1_

B7

VO

1_R

GB

6V

O1_

B6

VO

1_R

GB

5V

O1_

B5

VO

1_R

GB

4V

O1_

B4

VO

1_R

GB

3V

O1_

B3

VO

1_R

GB

2V

O1_

B2

VO

1_R

GB

1V

O1_

B1

VO

1_R

GB

0V

O1_

B0

VO0_SYNC[4..0]

VO0_SYNC0 VO0_HSYNCVO0_SYNC1 VO0_VSYNCVO0_SYNC2 VO0_DEVO0_SYNC3 VO0_CSYNCVO0_SYNC4 VO0_GV

VO1_SYNC[4..0]

VO1_SYNC0 VO1_HSYNCVO1_SYNC1 VO1_VSYNCVO1_SYNC2 VO1_DEVO1_SYNC3 VO1_CSYNCVO1_SYNC4 VO1_GV

FVIS0

FP

GA

_DO

NE

JTAG_TCK

FPGA_DONE

LIME_D[31..0]

CPU_D30CPU_D27CPU_D24CPU_D21CPU_D18CPU_D15CPU_D12CPU_D9CPU_D6CPU_D3CPU_D0

CPU_A0CPU_A3CPU_A6CPU_A9CPU_A12CPU_A15CPU_A18CPU_A21CPU_A24

CPU_S0CPU_S3CPU_S6

CPU_D1CPU_D4CPU_D7CPU_D10CPU_D13CPU_D16CPU_D19CPU_D22CPU_D25CPU_D28CPU_D31

CPU_A1CPU_A4CPU_A7CPU_A10CPU_A13CPU_A16CPU_A19CPU_A22CPU_A25

CPU_S1CPU_S4CPU_S7

CPU_D2CPU_D5CPU_D8CPU_D11CPU_D14CPU_D17CPU_D20CPU_D23CPU_D26CPU_D29

CPU_A2CPU_A5CPU_A8CPU_A11CPU_A14CPU_A17CPU_A20CPU_A23

EXT_RESET#

CPU_SINCPU_IRQ_BCPU_IRQ_ACPU_DEOP0CPU_DREQ0CPU_ALECPU_WR3CPU_WR1CPU_RDXCPU_BGRNTCPU_CS6CPU_CS4CPU_CS2CPU_CS0

CPU_SLKCPU_SOTI2C_SCLI2C_SDA

CPU_DACK0CPU_CLKCPU_ASCPU_WR2CPU_WR0CPU_BRQCPU_ RDYCPU_CS5CPU_CS3CPU_CS1

EXT_RESET#

LIME_CTRL1 LIME_RD

LIME_CTRL6 LIME_XRDYLIME_CTRL7 LIME_XBS

LIME_D16

LIME_D31

CPU_A15

CPU_D14

LIME_A9


LIME_D11

LIME_D0

CPU_ALE

CPU_CS6

CPU_D22

LIME_A19

FPG

A_I

NIT

#

CPU_AS

CPU_A10

CPU_A3CPU_A2

CPU_D1

CPU_IRQ_B

LIME_A3

LIME_CTRL0 LIME_XCS


LIME_D17

FPG

A1_

DO

UT

CPU_S2CPU_S1

CPU_D28CPU_CS1

CPU_D25

CPU_D0

LIME_D23

LIME_D20LIME_BS_MODE

LIME_D18

LIME_DTACK

I2C_SDA

LIME_D3

LIME_D14

LIME_D10

CPU_D20CPU_A19

FP

GA

_DO

NE

FPG

A_P

RO

G#

CPU_D24

CPU_A22

CPU_A5

LIME_RD

LIME_A10

LIME_A1

CONFIG2 LIME_MODE0

CONFIG6 LIME_GMODE1

LIME_D2

CPU_A8

CPU_D10

CPU_A23

CPU_D4

CPU_A1

LIME_DREQ

LIME_A23

LIME_D5

CPU_CS3CPU_CS2

CPU_D30

CPU_A25

CPU_D13

CPU_A6

LIME_D24

LIME_D14

LIME_XCS

LIME_A16

LIME_A11

LIME_D25LIME_D24


CONFIG3 LIME_MODE1


FPG

A_P

RO

G#

CPU_D31

CPU_A17

CPU_D19

CPU_A12

CPU_D2

LIME_D27

LIME_RDY_MODE

LIME_D22

LIME_D17

CPU_SIN

LIME_XRDYLIME_XWE3

LIME_CTRL8 LIME_DREQ

CPU_S0

LIME_D30

CPU_S6CPU_S5

CPU_A24

CPU_D15

RESET#0

LIME_A8

LIME_A0

LIME_CTRL10 LIME_RACK

LIME_D19

I2C_SCLI2C0

LIME_D20LIME_D21

LIME_D12

LIME_D15


CPU_DREQ0

CPU_CS5

LIME_A18

TDO

_FP

GA

2

CPU_D29

CPU_D27

LIME_MODE1

I2C_SCL

LIME_D8LIME_D7

CPU_D23

CPU_BRQCPU_BGRNT

CPU_A18

CPU_D17

CPU_A7

CPU_A4LIME_A13

LIME_D30

LIME_D23

CONFIG9 LIME_RDY_MODE

LIME_D26

LIME_CTRL11 LIME_XINT

FPG

A_I

NIT

#

CPU_DEOP0

JTA

G_T

CK

TDO

_FP

GA

1

CPU_WR2

CPU_S3

CPU_D5

CPU_A0

LIME_D21

FPGA_CLK

LIME_XBS

CPU_IRQ_A

LIME_A6


LIME_D18

LIME_D1

CPU_D9

LIME_D28

CPU_WR1CPU_WR0

CPU_D18

LIME_D26

LIME_XWE2

LIME_XWE1

LIME_A7

LIME_A5

CONFIG[9..0]

LIME_CTRL[11..0]

LIME_D31

CONFIG4 LIME_MODE2

CPU_A9

CPU_D11

LIME_XINT

LIME_A22

FP

GA

_CC

LK

CPU_CLK

CPU_S4

CPU_ RDY

CPU_D26

CPU_A21

CPU_D7

LIME_MODE0

LIME_A15LIME_A14

CONFIG7 LIME_GMODE2

LIME_D9

CONFIG8 LIME_BS_MODE

CONFIG5 LIME_GMODE0

CPU_A16

CPU_D16

CPU_D8

CPU_D3

LIME_D15

LIME_A12

LIME_D29

FPGA1_DOUT

CPU_RDX

CPU_D12

LIME_A17

LIME_D6

LIME_D4

LIME_D27

LIME_D13

CPU_DACK0

CPU_CS4

CPU_D21

CPU_S7

CPU_CS0

CPU_A14

LIME_D25

LIME_D16

LIME_RACK

LIME_XWE0

LIME_A4

LIME_D28

I2C_SDAI2C1

LIME_CTRL9 LIME_DTACK

LIME_D22

JTAG_TMS

LIME_A21LIME_A20

JTA

G_T

MS

CPU_WR3

CPU_A20

CPU_A13

CPU_A11

CPU_D6

LIME_D19

LIME_A2

LIME_A[23..0]

LIME_A0LIME_A1LIME_A2LIME_A3LIME_A4LIME_A5LIME_A6LIME_A7LIME_A8LIME_A9LIME_A10LIME_A11LIME_A12LIME_A13LIME_A14LIME_A15LIME_A16LIME_A17LIME_A18LIME_A19LIME_A20LIME_A21LIME_A22LIME_A23

LIME_D29

FVID0

FVID1

FVID2

FVID3

FVID4

FVID5

FVID6

FVID7

FVID8

FVID9

FVID10

FVID11

FVID12

FVID13

FVID14FVID15

FVID16FVID17

FVIS3FVIS2

FVIS1

VIN_RGBCK

VIN_ HSYNC

FVID0FVID1FVID2FVID3

VI_D0VI_D1VI_D2VI_D3







FVID16FVID17FVIS2FVIS3

VI_D16VI_D17VIN_VSYNCVIN_FID

VI_D[17..0]

VI_D0VI_D1VI_D2VI_D3VI_D4VI_D5VI_D6VI_D7VI_D8VI_D9VI_D10VI_D11VI_D12VI_D13VI_D14VI_D15VI_D16VI_D17

VI_SYNC[3..0]

V I_SYNC0VIN_RGBCKV I_SYNC1VIN_ HSYNCV I_SYNC2VIN_VSYNCV I_SYNC3VIN_FID

VO_DCLKI

FPGA_CLK

CPU_CLK

LIME_D4

LIME_D7

LIME_D5LIME_D6

LIME_D0

LIME_D3

LIME_D1LIME_D2

LIME_MODE2

LIME_D12LIME_D13

LIME_D8

LIME_D11LIME_D10LIME_D9

CPU_SOT

VI2_656_HSYNCVI2_656_VSYNC

CPU_S5CPU_S2

FPGA_COMM

FPGA_COMM

CPU_SLK

I2C_SDAI2C_SCL

I2C_SDAI2C_SCL

SMPG_INT

SMPG_INT

RESET#0

LIME_GMODE0

LIME_GMODE1LIME_GMODE2

FPGA_CFG

FPGA_CFG

VO1_CLK[3..0]

VO0_CLK[3..0]

LIME_D[31..0]

RESET#0

VO_DCLKO

VI_656_CLK

I2C[1..0]

VO_D[23..0]

VO_SYNC[4..0]

VI_656_D[7..0]

CONFIG[9..0]

LIME_CTRL[11..0]

VO0_RGB[23..0]

VO1_RGB[23..0]

VO1_SYNC[4..0]

VO0_SYNC[4..0]

EXT_RESET#

LIME_A[23..0]

VI_D[17..0]

VI_SYNC[3..0]

FPGA_CLK

VO_DCLKI

CPU_CLK

FPGA_CFG

VCC33

VCC33

VCC33

VCC33

VCC18 VCC33 VCC33

VCC33

VCC33

VCC33

VCC33

VCC18

VCC33 VCC50 VCC33 VCC50 VCC33 VCC50

VCC33

VCC33

VCC50

Title


Date: Sheet o f

30100-010 PA8

Fujitsu Lime Evaluation Board: Lime Subsystem: FPGA


A1


RG

B d

igit

al in

put

Place R829 - R833 close to thecorresponding U801 pins!

Place R834 - R837 close to thecorresponding U802 pins!

PCB label:FPGA fill

Video I/O Switch Host CPU Mux

NP

NP

NP

Place all damping resistors andresistor networks directky tothe corresponding FPGA pins!

C71410u

R719 1k

C712100n

C75110u

C725100n

TP700

C739100n

C710100n

X700A

DIN 96_ABC-S

A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17A18A19A20A21A22A23A24A25A26A27A28A29A30A31A32

RN707 33Rx41234 5

678

C708100n

R711 33R

RN715

33Rx4

1234 5

678

C719100n

X705

TSM-105-01-L-DV-A-P

1 23 45 67 89 10

R716 33R

C74610u

RN706 33Rx41234 5

678

C706100n

D700TLMT3100 red

X701A

DIN 48_ABC-S

A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16

R700 33R

C737100n

X702


1 23 45 67 89 10

11 1213 1415 1617 1819 202123 24

22

R701 33R

R704 33R

C73310u

C75347p

RN718

33Rx4

1234 5

678

XilinxSpartan-IIE -FT256

Configuration

Power

7

6

5

4

3

2

1

0

IO3_0: INIT#

IO2_22: DINIO2_23: DOUT

U700

XC2S50E-6FT256IG

ND

1T1

6G

ND

2T1

GN

D4

R2

GN

D5

L11

GN

D6

L6

GN

D10

K7

GN

D9

K8

GN

D8

K9

GN

D7

K10

GN

D15

H10

GN

D14

J7G

ND

13J8

GN

D12

J9G

ND

11J1

0

GN

D20

G9

GN

D19

G10

GN

D18

H7

GN

D17

H8

GN

D16

H9

GN

D24

F6G

ND

23F1

1G

ND

22G

7

GN

D3

R15

GN

D21

G8

VC

CO

_B5_

3M

8

VC

CO

_B4_

3M

9V

CC

O_B

4_2

L10

VC

CO

_B4_

1L9

VC

CO

_B3_

3K

11V

CC

O_B

3_2

J12

VC

CO

_B3_

1J1

1V

CC

O_B

2_3

H12

VC

CO

_B2_

2H

11V

CC

O_B

2_1

G11

VC

CO

_B1_

3F1

0V

CC

O_B

1_2

F9V

CC

O_B

1_1

E9

VC

CO

_B0_

3F8

VC

CO

_B0_

2F7

VC

CO

_B0_

1E

8

VC

CIN

T4N

4V

CC

INT5

M12

VC

CIN

T6M

5V

CC

INT7

E12

VC

CIN

T8E

5V

CC

INT9

D13

VC

CIN

T10

D4

VC

CIN

T11

C14

VC

CIN

T12

C3

IO7_0D3IO7_1C2IO7_2C1IO7_3D2IO7_4D1IO7_5 / VREFE3IO7_6E4IO7_7E2IO7_8E1IO7_9 / VREFF4IO7_10F3IO7_11F2IO7_12F1IO7_13F5IO7_14G5IO7_15G3IO7_16G4IO7_17 / VREFG2

IO6_0 (TRDY)J4IO6_1J2IO6_2J3IO6_3J1IO6_4 / VREFK1IO6_5K2IO6_6K3IO6_7L1IO6_8L2IO6_9K4IO6_10K5IO6_11L3IO6_12 / VREFM2IO6_13M1IO6_14N1IO6_15L4IO6_16 / VREFL5IO6_17M3

IO5_0P4IO5_1R4IO5_2T3IO5_3T4IO5_4N5IO5_5P5IO5_6 / VREFR5IO5_7T5IO5_8N6IO5_9P6IO5_10 / VREFR6IO5_11T6IO5_12M6IO5_13N7IO5_14P7IO5_15R7IO5_16T7

GCK1T8

IO4_0 (DLL)R9IO4_1P9IO4_2N9IO4_3T10IO4_4 / VREFR10IO4_5P10IO4_6R11IO4_7T11IO4_8N10IO4_9M10IO4_10P11IO4_11 / VREFR12IO4_12T12IO4_13T13IO4_14N11IO4_15 / VREFM11IO4_16P12IO4_17N12

GCK0T9

IO3_1 (D7) P16IO3_2 N15IO3_3 N16IO3_4 N14IO3_5 M14

IO3_6 / VREF M15IO3_7 M16IO3_8 M13IO3_9 L14

IO3_10 / VREF L15IO3_11 (D6) L16IO3_12 (D5) L13

IO3_13 K14IO3_14 K15IO3_15 K16IO3_16 L12IO3_17 K12

IO2_0 (IRDY) H16IO2_1 G16IO2_2 H14IO2_3 H15

IO2_4 (D3) G15IO2_5 / VREF F16

IO2_6 H13IO2_7 G14IO2_8 F15IO2_9 E16

IO2_10 G13IO2_11 (D2) F14IO2_12 (D1) E15

IO2_13 / VREF D16IO2_14 F13IO2_15 E14IO2_16 D15

IO1_0 (CS#) A14IO1_1 (WRITE#) A13

IO1_2 B13IO1_3 C12IO1_4 B12IO1_5 A12

IO1_6 / VREF D12IO1_7 E11IO1_8 D11IO1_9 C11

IO1_10 / VREF B11IO1_11 A11IO1_12 E10IO1_13 D10IO1_14 C10IO1_15 B10IO1_16 A10

IO1_17 / VREF D9

GCK2 B8

IO0_0 (DLL) D8IO0_1 A7IO0_2 E7

IO0_3 / VREF D7IO0_4 C7IO0_5 B7IO0_6 A6IO0_7 B6IO0_8 C6IO0_9 A5

IO0_10 / VREF B5IO0_11 D6IO0_12 E6IO0_13 D5

IO0_14 / VREF C5IO0_15 B4

GCK3 C8

M0

T2M

1R

1M

2R

3

TDI

C13

TMS

B1

TCK

A2

TDO

B14

PR

OG

RA

M#

R16

DO

NE

T15

CC

LKA

15IN

IT#

P15

DIN

(D0)

B16

DO

UT

/ BU

SY

C15

IO7_18G1IO7_19H4IO7_20H3IO7_21H2IO7_22 (IRDY)H1

IO6_18M4IO6_19N2IO6_20N3IO6_21P1IO6_22P2

IO5_17 / VREFM7IO5_18N8IO5_19P8IO5_20 (DLL)R8

IO4_18R13IO4_19P13IO4_20T14IO4_21R14

IO3_18 / VREF K13IO3_19 (D4) J14

IO3_20 J15IO3_21 J16

IO3_22 (TRDY) J13

IO2_17 / VREF C16IO2_18 G12IO2_19 F12IO2_20 E13IO2_21 D14

IO1_18 C9IO1_19 B9IO1_20 A9

IO1_21 (DLL) A8

IO0_16 C4IO0_17 A4IO0_18 A3IO0_19 B3

VC

CIN

T3N

13V

CC

INT2

P3

VC

CIN

T1P

14

VC

CO

_B5_

2L8

VC

CO

_B5_

1L7

VC

CO

_B6_

1J5

VC

CO

_B6_

2J6

VC

CO

_B6_

3K

6V

CC

O_B

7_1

G6

VC

CO

_B7_

2H

5V

CC

O_B

7_3

H6

GN

D25

B15

GN

D26

B2

GN

D27

A16

GN

D28

A1

RN716

33Rx4

1234 5

678

C713100n

C702100n

C711100n

C72210u

C755100n

C709100n

R712 33R

RN708 33Rx41234 5

678

R706 33R

C730100n

R714 1k

C721100n

RN711 33Rx41234 5

678

C74010u

IDT2305

Zero DelayClock Buffer

U703

IDT2305-1DCGI

REF1

CLK22

CLK13

GND4 CLK3 5

VDD 6

CLK4 7

CLKOUT 8

C718100n

R717 33R

C7381u

RN704 33Rx41234 5

678

C71510u

R703 33R

XilinxSpartan-IIE -FT256

Configuration

Power

7

6

5

4

3

2

1

0

IO3_0: INIT#

IO2_22: DINIO2_23: DOUT

U701

XC2S50E-6FT256I

GN

D1

T16

GN

D2

T1

GN

D4

R2

GN

D5

L11

GN

D6

L6

GN

D10

K7

GN

D9

K8

GN

D8

K9

GN

D7

K10

GN

D15

H10

GN

D14

J7G

ND

13J8

GN

D12

J9G

ND

11J1

0

GN

D20

G9

GN

D19

G10

GN

D18

H7

GN

D17

H8

GN

D16

H9

GN

D24

F6G

ND

23F1

1G

ND

22G

7

GN

D3

R15

GN

D21

G8

VC

CO

_B5_

3M

8

VC

CO

_B4_

3M

9V

CC

O_B

4_2

L10

VC

CO

_B4_

1L9

VC

CO

_B3_

3K

11V

CC

O_B

3_2

J12

VC

CO

_B3_

1J1

1V

CC

O_B

2_3

H12

VC

CO

_B2_

2H

11V

CC

O_B

2_1

G11

VC

CO

_B1_

3F1

0V

CC

O_B

1_2

F9V

CC

O_B

1_1

E9

VC

CO

_B0_

3F8

VC

CO

_B0_

2F7

VC

CO

_B0_

1E

8

VC

CIN

T4N

4V

CC

INT5

M12

VC

CIN

T6M

5V

CC

INT7

E12

VC

CIN

T8E

5V

CC

INT9

D13

VC

CIN

T10

D4

VC

CIN

T11

C14

VC

CIN

T12

C3

IO7_0D3IO7_1C2IO7_2C1IO7_3D2IO7_4D1IO7_5 / VREFE3IO7_6E4IO7_7E2IO7_8E1IO7_9 / VREFF4IO7_10F3IO7_11F2IO7_12F1IO7_13F5IO7_14G5IO7_15G3IO7_16G4IO7_17 / VREFG2

IO6_0 (TRDY)J4IO6_1J2IO6_2J3IO6_3J1IO6_4 / VREFK1IO6_5K2IO6_6K3IO6_7L1IO6_8L2IO6_9K4IO6_10K5IO6_11L3IO6_12 / VREFM2IO6_13M1IO6_14N1IO6_15L4IO6_16 / VREFL5IO6_17M3

IO5_0P4IO5_1R4IO5_2T3IO5_3T4IO5_4N5IO5_5P5IO5_6 / VREFR5IO5_7T5IO5_8N6IO5_9P6IO5_10 / VREFR6IO5_11T6IO5_12M6IO5_13N7IO5_14P7IO5_15R7IO5_16T7

GCK1T8

IO4_0 (DLL)R9IO4_1P9IO4_2N9IO4_3T10IO4_4 / VREFR10IO4_5P10IO4_6R11IO4_7T11IO4_8N10IO4_9M10IO4_10P11IO4_11 / VREFR12IO4_12T12IO4_13T13IO4_14N11IO4_15 / VREFM11IO4_16P12IO4_17N12

GCK0T9

IO3_1 (D7) P16IO3_2 N15IO3_3 N16IO3_4 N14IO3_5 M14

IO3_6 / VREF M15IO3_7 M16IO3_8 M13IO3_9 L14

IO3_10 / VREF L15IO3_11 (D6) L16IO3_12 (D5) L13

IO3_13 K14IO3_14 K15IO3_15 K16IO3_16 L12IO3_17 K12

IO2_0 (IRDY) H16IO2_1 G16IO2_2 H14IO2_3 H15

IO2_4 (D3) G15IO2_5 / VREF F16

IO2_6 H13IO2_7 G14IO2_8 F15IO2_9 E16

IO2_10 G13IO2_11 (D2) F14IO2_12 (D1) E15

IO2_13 / VREF D16IO2_14 F13IO2_15 E14IO2_16 D15

IO1_0 (CS#) A14IO1_1 (WRITE#) A13

IO1_2 B13IO1_3 C12IO1_4 B12IO1_5 A12

IO1_6 / VREF D12IO1_7 E11IO1_8 D11IO1_9 C11

IO1_10 / VREF B11IO1_11 A11IO1_12 E10IO1_13 D10IO1_14 C10IO1_15 B10IO1_16 A10

IO1_17 / VREF D9

GCK2 B8

IO0_0 (DLL) D8IO0_1 A7IO0_2 E7

IO0_3 / VREF D7IO0_4 C7IO0_5 B7IO0_6 A6IO0_7 B6IO0_8 C6IO0_9 A5

IO0_10 / VREF B5IO0_11 D6IO0_12 E6IO0_13 D5

IO0_14 / VREF C5IO0_15 B4

GCK3 C8

M0

T2M

1R

1M

2R

3

TDI

C13

TMS

B1

TCK

A2

TDO

B14

PR

OG

RA

M#

R16

DO

NE

T15

CC

LKA

15IN

IT#

P15

DIN

(D0)

B16

DO

UT

/ BU

SY

C15

IO7_18G1IO7_19H4IO7_20H3IO7_21H2IO7_22 (IRDY)H1

IO6_18M4IO6_19N2IO6_20N3IO6_21P1IO6_22P2

IO5_17 / VREFM7IO5_18N8IO5_19P8IO5_20 (DLL)R8

IO4_18R13IO4_19P13IO4_20T14IO4_21R14

IO3_18 / VREF K13IO3_19 (D4) J14

IO3_20 J15IO3_21 J16

IO3_22 (TRDY) J13

IO2_17 / VREF C16IO2_18 G12IO2_19 F12IO2_20 E13IO2_21 D14

IO1_18 C9IO1_19 B9IO1_20 A9

IO1_21 (DLL) A8

IO0_16 C4IO0_17 A4IO0_18 A3IO0_19 B3

VC

CIN

T3N

13V

CC

INT2

P3

VC

CIN

T1P

14

VC

CO

_B5_

2L8

VC

CO

_B5_

1L7

VC

CO

_B6_

1J5

VC

CO

_B6_

2J6

VC

CO

_B6_

3K

6V

CC

O_B

7_1

G6

VC

CO

_B7_

2H

5V

CC

O_B

7_3

H6

GN

D25

B15

GN

D26

B2

GN

D27

A16

GN

D28

A1

RN709 33Rx41234 5

678

C73410u

C700100n

X700C

DIN 96_ABC-S

C1C2C3C4C5C6C7C8C9C10C11C12C13C14C15C16C17C18C19C20C21C22C23C24C25C26C27C28C29C30C31C32

RN703 33Rx41234 5

678

R707390

C742100n

C74710p

C701100n

C75610u

C707100n

C731100n

R705 33R

C726100n

C72310u

R713 33R

C724100n

R722 0R

C728100n

R709 1k

RN700 33Rx41234 5

678

C757100n

C71710u

C70410u

RN705 33Rx41234 5

678

C71610u

R720 1k

U702

XCF02S

D01DNC12CLK3TDI4TMS5TCK6CF7OE/RESET8DNC29CE10 GND 11DNC3 12

VCCO 19VCCINT 18

TDO 17DNC6 16DNC5 15DNC4 14CEO 13

VCCJ 20

C74110u

X704

TSM-106-01-L-SH-A

123456

R718 33R

RN719

33Rx4

1234 5

678

X701C

DIN 48_ABC-S

C1C2C3C4C5C6C7C8C9C10C11C12C13C14C15C16

R708 0R

RN717

33Rx4

1234 5

678

C74310u

C703100n

C73510u

C750100n

RN713 33Rx41234 5

678

C727100n

R710 33R

RN712 33Rx41234 5

678

C729100n

C720100n

IDT2305

Zero DelayClock Buffer

U704

IDT2305-1DCGI

REF1

CLK22

CLK13

GND4 CLK3 5

VDD 6

CLK4 7

CLKOUT 8

C75810u

R715 33R

RN710 33Rx41234 5

678

R2730R 1206

C745100n

C75447p

X700B

DIN 96_ABC-S

B1B2B3B4B5B6B7B8B9B10B11B12B13B14B15B16B17B18B19B20B21B22B23B24B25B26B27B28B29B30B31B32

X703

TMM-110-01-L-D-SM-A-P

123456

121314151617181920

7891011

RN702 33Rx41234 5

678

RN701 33Rx41234 5

678

R702 33R

C70510u

X701B

DIN 48_ABC-S

B1B2B3B4B5B6B7B8B9B10B11B12B13B14B15B16

C75210p

RN714

4k7x4

1234 5

678

100nC736

C74410u

C73210u

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SDQM#2

SDQM#3

SDCLK0

SDA[14..0]

SDA14 SDBA1

SDA13 SDBA0

SDA0

SDA1

SDA2

SDA3

SDA10

SDRAS#

SDCAS#

SDD16

SDD17

SDWE#

SDD18

SDD19

SDD20

SDQM#[3..0]

SDD21

SDA12

SDD22

SDCLK[1..0]

SDCLK1SDCLK0

SDD23

SDA4

SDD31

SDD30

SDD29

SDA5

SDA6

SDD28

SDA7

SDD26

SDA8

SDA9

SDD25

SDA11

SDD24

SDD27

SDQM#1

SDQM#0

SDQM#1

SDQM#2

SDCLK1

SDA14 SDBA1

SDA13 SDBA0

SDQM#3

SDA0

SDA1

SDA2

SDA3

SDA10

SDRAS#

SDD0

SDCAS#

SDD1

SDWE#

SDD2

SDD3

SDD4

SDQM#0

SDD5

SDA12

SDD6

SDD7

SDA4

SDD15

SDD14

SDD13

SDA6

SDA5

SDD12

SDD10

SDA7

SDA8

SDA9

SDD9

SDD8

SDA11

SDD11

SDD[31..0]

SDWE#

SDCAS#

SDRAS#

SDA[14..0]

SDD[31..0]

SDCLK[1..0]

SDQM#[3..0]

SDRAS#

SDCAS#

SDWE#

VCC33

VCC33

Title


Date: Sheet o f

30200-011 PA8

Fujitsu Lime Evaluation Board: Lime Subsystem: SDRAM


A2

11 11Tuesday, March 13, 2007

Place C's close to SDRAM power pins,one of each value to each SDRAM!

C8021u

C80110u

C8071n

C804100n

SDRAM 256Mbit

TSOP 1 (54)4M x 16bit x 4 Banks

U800

K4S561632x-xCxx

VDD01

DQ02

VDDQ03

DQ14

DQ25

VSSQ06

DQ37

DQ48

VDDQ19

DQ510

DQ611

VSS012

DQ713

VDD114

LDQM15

WE16

CAS17

RAS18

CS19

BA020

BA121

A10/AP22

A023

A124

A225

A326

VDD227 VSS1 28

VSS2 54

DQ15 53

DQ14 51

VSSQ1 52

DQ13 50

A4 29

A5 30

A6 31

A7 32

A8 33

A9 34

A11 35

A12 36

CKE 37

CLK 38

UDQM 39

NC/RFU 40

VSS3 41

DQ8 42

DQ9 44

DQ10 45

DQ11 47

DQ12 48

VDDQ2 43

VSSQ2 46

VDDQ3 49

C805100n

C8061n

C8031u

SDRAM 256M*16

TSOP 1 (54)4M x 16bit x 4 Banks

U801

K4S561632x-xCxx

VDD01

DQ02

VDDQ03

DQ14

DQ25

VSSQ06

DQ37

DQ48

VDDQ19

DQ510

DQ611

VSS012

DQ713

VDD114

LDQM15

WE16

CAS17

RAS18

CS19

BA020

BA121

A10/AP22

A023

A124

A225

A326

VDD227 VSS1 28

VSS2 54

DQ15 53

DQ14 51

VSSQ1 52

DQ13 50

A4 29

A5 30

A6 31

A7 32

A8 33

A9 34

A11 35

A12 36

CKE 37

CLK 38

UDQM 39

NC/RFU 40

VSS3 41

DQ8 42

DQ9 44

DQ10 45

DQ11 47

DQ12 48

VDDQ2 43

VSSQ2 46

VDDQ3 49

C80010u

bm-cremson starterkit lime-v1 03 - farnell element14 · 2010-04-30 · h l 17.73 hz 17.553 to 17.73...

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