bologna – 14 october , 2009 fine...bologna – 14 october , 2009 video over wireless: fpga design...

Bologna – 14 October , 2009

Video over wireless:FPGA design and implementation of a pulse-FPGA design and implementation of a pulsebased echo canceler for DVB-T/H

Ph.D Student: G.ChiurcoTutor: Prof. O.Andrisano

Alma Mater University of Bologna, Italy

Scenario description: Problems and goals

Single Frequency Network (SFN) constituted by:a. a DVB-T/H broadcasting station/ gb. an on-channel relay station or repeater (OCR)c. many stationary and mobile users

Main goal: covering with the DVB-T signal an area notreachable by the DVB-T broadcast station

Giovanni Chiurco

Alma Mater University of Bologna - WiLab

reachable by the DVB-T broadcast station.

Targetg

Repeater based on DVB-T pilots Repeater “general-purpose”: The Pulse-based Echo Canceler

Giovanni Chiurco


Outline

Project Flow; FPGA d l t kit FPGA development kit;

Scenario description: Problems and Goals; The BB-OCR solution for DVB-T signal;

Echo canceller: Basic Scheme and Operations; FPGA Design and Implementation; FPGA Design and Implementation; Workbench Test-Bed; Measurements and Results.

Giovanni Chiurco


Project FlowjProject & Analysis

Simulation Implementation &Measurements

Giovanni Chiurco


FPGA development kit featuresp

FPGA Stratix II Altera d Kit EP2S180F1020C3dev. Kit EP2S180F1020C3

Analog I/O:•Two-channel, 12-bit, 125-million samples per second (MSPS) analog-to digital (A/D);•Two-channel, 14-bit, 165-MSPS digital-to-analog (D/A).

Digital I/O • Connector for the Texas Instruments (TI) Evaluation Module (TI-EVM);

Two 40 pin connectors for Analog Devices' A/D converter evaluation boards;• Two 40-pin connectors for Analog Devices' A/D converter evaluation boards; • Mictor connector for Agilent and Tektronix logic analyzers; • RS-232 serial port; • 10/100 Ethernet physical layer/media access control;

(PHY/MAC) and RJ-45 jack.

Memory • 32-Mbyte SDR SDRAM • 16-Mbyte flash • 1-Mbyte SRAM

16 Mb t t fl h• 16-Mbyte compact flash

Giovanni Chiurco


Scenario description: Problems and goals (3)

Adopted strategy: DVB-T repeater.

(d)(c) x (e)

(c)

( )( ) x(c)

(d)(b)( ) (e)(d)(b)(a)

Consequence: the amplifier power must be limited Reduced service area!

The echo canceller permits to increase the coverage area

Giovanni Chiurco


Repeaters: classical solutionsp

Antenna Isolation

TimeDelay

Quality ofTx signal

Selectivityof Rx signal

MantainSync.

RF OCR

IF OCR IF OCR

BB OCR

Dec. OCR

BB-OCR Direct relay scheme: Low delay techniques, based basically on:

ESTIMATION of the loop-back channel; (ADAPTIVE) FILTERING to cancel the echoes;

Giovanni Chiurco


Baseband OCR

Filter

HPAFilterand LNA

HPA

RF

Upconverter

IF

Down converter

L.O.

IF

D/A – Up conversion

IF

A/D - BBDown conv.

IF

Data Process.

Giovanni Chiurco


Baseband OCR (2)( ) OCR architecture implemented on the FPGA board:

Giovanni Chiurco


Echo canceller basic scheme

Delay+

M lti indo cancelle

Ch l

-

Estimator

Multi-window canceller

Possibility to cancel Channel

estimationunit

Controller

Dynamic tap

update

Estimator & Pulse

Generatorsingle and multiple echoes;

up to Nw different echo

FIR1

clusters can be cancelled;

the position of the lli i d i

FIRi

Del

ay li

ne

Echo

……

cancelling windows isautomatically determined.

FIRNw

Echo Canceller Multi-window

canceller

Giovanni Chiurco


Echo canceller basic operationsp

Two operative phases:

Start-Up (open-loop) determination of the number and position of the determination of the number and position of the

cancelling windows (pulse-based) initial coupling channel (pulse) estimation FIR’s set-up FIR s set up

Steady-State (closed-loop) effective DVB T signal repetition effective DVB-T signal repetition (fast) echo tracking (LMS-algorithm) stability and coupling channel monitoring (periodical

check of new echoes with the pulse technique)check of new echoes with the pulse technique)

Giovanni Chiurco


Search and cancelling windowsg Search window: from 3-6ms to about 60ms (nearly

correspondent to reflections from obstacles at 8Km); Cancelling window: about 5ms (for 8MHz BW);

Target: suppressing a single echo with power 15dBover the useful DVB-T signal powerover the useful DVB-T signal power

echo suppression > 40 dB

Giovanni Chiurco


FPGA design and implementation The ECHO_CANCELLER entity:

ESTIMATOR_iq:implementing the channel pulse estimator, the pulse generator and an additional Least Mean Squarean additional Least Mean Square (LMS) algorithm working in the steady-state mode;

SHREG&MUX:SHREG&MUX: implementing the delay which allows to position the cancelling window inside the overall search window;

( 1)( ) [ ( ) ( )]

Ph mh m y n y n

DYN_FIR_MCV:implementing the cancelling FIR filters with dynamically variable coefficients based on the Multi

( ) [ ( ) ( )]n nP P P Q Qh m y n y n

( 1)Qh m coefficients, based on the Multi Cycle Variable (MCV) technology.( ) [ ( ) ( )]

n nQ P Q Q Ph m y n y n

Giovanni Chiurco


FPGA design and implementation The ECHO_CANCELLER entity:

ESTIMATOR_iq:implementing the channel pulse estimator, the pulse generator and an additional Least Mean Squarean additional Least Mean Square (LMS) algorithm working in the steady-state mode;

SHREG&MUX:SHREG&MUX: implementing the delay which allows to position the cancelling window inside the overall search window;

DYN_FIR_MCV:implementing the cancelling FIR filters with dynamically variable coefficients based on the Multicoefficients, based on the Multi Cycle Variable (MCV) technology.

Giovanni Chiurco


Workbench Test-bed

Giovanni Chiurco


MER: Modulation Error Ratio The modulation error ratio or MER is a measure used to quantify the

performance of a digital radio transmitter or receiver in a communicationst i di it l d l ti ( h QAM) A i l t b id lsystem using digital modulation (such as QAM). A signal sent by an ideal

transmitter or received by a receiver would have all constellation pointsprecisely at the ideal locations, however various imperfections in theimplementation (such as noise, low image rejection ratio, phase noise,implementation (such as noise, low image rejection ratio, phase noise,carrier suppression, distortion, etc.) or signal path cause the actualconstellation points to deviate from the ideal locations.

The modulation error ratio is equal to theratio of the root mean square (RMS) powerof the error vector to the power of thereference. It is defined in dB as:

where Perror is the RMS power of the error vector, and Psignal is the RMS power of ideal transmitted signal.

Giovanni Chiurco


MER gain with Echo Canceller ONg

MER vs Eco

45,0

50,0

30,0

35,0

40,0

R [d

B]

15,0

20,0

25,0ME

10,0-10 -5 0 5 10 15 20 25

Eco [dB]

MER con cancellatore MER no-canc

Giovanni Chiurco


Different MER measurements:

MER filtering

MER modulator

Giovanni Chiurco


MER vs. Power DVB-T signalg

Signal Level to the ADC: 10dBmMER vs P_mod[dBm]

60 0

Eco = -10dB40 0

50,0

60,0

]

Eco = +20dBEco = +15dB

Eco = +10dBEco = +5dB Eco = 0dB

Eco = -5dB

30,0

40,0

MER

[dB

]

Eco = +25dB

Eco = +20dB

10,0

20,0

-30,0 -25,0 -20,0 -15,0 -10,0 -5,0 0,0

P_mod [dBm]

MER con cancellatore MER modulatore MER filtraggio

Giovanni Chiurco


Echo Suppression intra-windowpp

Attenuations vs. Echo Level

70

75

60

65

70

on [d

B]

45

50

55

Atte

nuat

io

35

40

-10 -5 0 5 10 15 20 25 30

Echo Level [dB]

A.P. A.min A.P.2 A.min 2

Giovanni Chiurco


Locking timeg

Locking Time for echoes [-10 +25] dB

2,499

2,500

Locking Time for echoes [ 10, +25] dB

1,3521,516

1,844

1 500

2,000

1,000

1,500

t [s]

0,000

0,500

2048 4096 8192 163842048 4096 8192 16384

Number of Pulse Accumulation

Giovanni Chiurco


Measurements:

Echo level = -5dB

Giovanni Chiurco


Measurements:

Echo level = +10dB

Giovanni Chiurco


Measurements:

Echo level = +20dB

Giovanni Chiurco


Publications

Giovanni Chiurco


Crediti acquisiti nel II anno

Scuola di Dottorato – Napoli: 40

Scuola di Dottorato Bressanone: 21Scuola di Dottorato – Bressanone: 21

Mini corso Heterogeneous Network: 12

TOTALE II ANNO: 73

TOT. I + II ANNO: 113

Giovanni Chiurco


Th k f Thank you for your attention!attention!

[email protected]

Giovanni Chiurco


bologna – 14 october , 2009 fine...bologna – 14 october , 2009 video over wireless: fpga design...

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