boolean algebra saras m. srivastava pgt (computer science) kendriya vidyalaya, iisc bangalore –...
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BOOLEAN
ALGEBRA
Saras M. SrivastavaPGT (Computer Science)Kendriya Vidyalaya, IISc
Bangalore – 560 012
What is logic ?
Any logical things have only two state either
true or false.
Example :
Is 12 – 10 = 2 Yes
Is India post populated country in the world?
No
Saras M. Srivastava PGT CS, KV IISc, Bangalore 12
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BINARY VALUED QUANTITIES
Binary Decision : THE DECISION which results into either YES
/TRUE OR NO/FALSE
Tautology : If the result of any logical statement or
expression is always TRUE or 1
Fallacy : If the result is always FALSE or 0
Saras M. Srivastava PGT CS, KV IISc, Bangalore 12
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BINARY VALUED QUANTITIES
Binary Decision : THE DECISION which results into either YES
/TRUE OR NO/FALSE
Tautology : If the result of any logical statement or
expression is always TRUE or 1
Fallacy : If the result is always FALSE or 0
Saras M. Srivastava PGT CS, KV IISc, Bangalore 12
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LOGICAL OPERATIONS
Logic operations
NOT (Complement)- Changes TRUE to FALSE, 1 to 0, high to low.
AND — “A AND B” is true if A and B are individually true (A•B, AB, A.B)
OR — “A OR B” is true if either A or B is true (or both are true) (A+B, A.B).
Saras M. Srivastava PGT CS, KV IISc, Bangalore 12
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Evaluation of Boolean Expression using truth table
Prepare truth table X’Y’ + X’Y XY’(Z+YZ’) + Z’ Prove using truth table (X + Y)’ = X’Y’ X + XY = X
Saras M. Srivastava PGT CS, KV IISc, Bangalore 12
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LOGIC GATES
What is logic Gate ?Gate is an electronic circuit which operates on
one or more signals to produce an output
signal. Basically there are three type of Logic
Gate.
Saras M. Srivastava PGT CS, KV IISc, Bangalore 12
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TRUTH TABLES Truth table Represents all the possible
values of logical variables / statements along with all the possible results of the given combination of values.
Saras M. Srivastava PGT CS, KV IISc, Bangalore 12
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Inverter (NOT Gate)
This Gate operates on single variable and operation performed by NOT operator called complementation. Thus A means complement of A’.
A A’
0 1
1 0
Input Output
A A’
Symbol
Truth Table
Saras M. Srivastava PGT CS, KV IISc, Bangalore 12
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AND GATE:
If both inputs signals are 1 (i.e. high) then the output will also be 1 (i.e. high).
Otherwise, the output willbe 0 (i.e. low).
A B A.B
0 0 0
0 1 0
1 0 0
1 1 1
A
BA.B
Truth Table
Two input AND Gate
The AND Gate have two or more than two input signals and produce an out put signal.
Saras M. Srivastava PGT CS, KV IISc, Bangalore 12
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OR Gate:
If either of the two input signals are 1 (high), or both of them are 1 (high), the output will be 1 (high).
A B A+B
0 0 0
0 1 1
1 0 1
1 1 1
AB
A+B
The OR Gate have two or more than two input signals and produce an out put signal.
Saras M. Srivastava PGT CS, KV IISc, Bangalore 12
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Universal Gates
NAND and NOR Gate are known as Universal Gate
because any Boolean function can be constructed
using only NAND or only NOR gates.
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The NAND Gate:
The NAND gate is a combination of an AND gate followed by an inverter (not Gate). It is compliment of AND Gate.
A B Y
0 0 1
0 1 1
1 0 1
1 1 0A
B Y
The NAND (Not AND) Gate has two or more input signal but only one output signal. If All the inputs are 1 (i.e. high), then the output l is 0 (i.e. low)
Saras M. Srivastava PGT CS, KV IISc, Bangalore 12
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15NAND Gates into Other Gates:-
AY
A
B
Y
YAB
NOT Gate
AND Gate
OR Gate
We can create other gates with the help of NAND Gate.
Saras M. Srivastava PGT CS, KV IISc, Bangalore 12
NOR Gate :The NOR (Not OR) Gate has two or more input signal but only one output signal. If All the inputs are 0 (i.e. low), then the output signal is 1 (i.e. high)
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
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AB
Y
The NOR gate is a combination of an OR gate followed by an inverter (not Gate). It is compliment of OR Gate.
Truth Table for NOR Gate
XOR Gate (Exclusive OR Gate):- We use XOR Gate for parity check. XOR Gate produces output 1 for only those inputs combinations that have odd number of 1’s.
# Odd number of 1’s produce output 1. Two input XOR Gate
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
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AB
Y=AB’+A’B
# A B= AB’+A’B
Truth Table for XOR Gate :
+
XNOR Gate (Exclusive NOR Gate):- We use XNOR Gate for parity check. XNOR Gate produces output 1 for only those inputs combinations that have even number of 1’s.
# Even number of 1’s and 0’s produce output 1.
Truth Table for Two Input XNOR Gate
A B Y
0 0 1
0 1 0
1 0 0
1 1 1
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A B=AB+A’B’
Laws &
Theorems of
Boolean
Algebra
Boolean Algebra A Boolean algebra is defined as a closed
algebraic system containing a set K (two or more) elements and two operators, and +.
Operators + and are similar to + and x. Useful for identifying and minimizing circuit
functionality Identity elements
a + 0 = a a 1 = a
0 is the identity element for the + operation.
1 is the identity element for the operation.
Saras M. Srivastava PGT CS, KV IISc, Bangalore 12
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Duality
The principle of duality says that if an expression is valid in Boolean algebra, the dual of that expression is also valid.
To form the dual of an expression, replace all + operators with operators, all operators with + operators, all ones with zeros, and all zeros with ones.
Form the dual of the expressiona + (b c) = (a + b) (a + c)
Following the replacement rules…a (b + c) = a b + a c
Saras M. Srivastava PGT CS, KV IISc, Bangalore 12
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Commutativity and Associativity
The Commutative Property:For every a and b in K, a + b = b + a a b = b a
The Associative Property:For every a, b, and c in K, a + (b + c) = (a + b) + c a (b c) = (a b) c
Saras M. Srivastava PGT CS, KV IISc, Bangalore 12
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Distributivity and Complements
The Distributive Property:For every a, b, and c in K, a ( b + c ) = ( a b ) + ( a c ) a + ( b c ) = ( a + b ) ( a + c )
The Existence of the Complement:For every a in K there exists a unique element called a’ (complement of a) such that, a + a’ = 1 a a’ = 0
Saras M. Srivastava PGT CS, KV IISc, Bangalore 12
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Involution
This theorem states:a’’ = a
Taking the double inverse of a value will give the initial value.
Saras M. Srivastava PGT CS, KV IISc, Bangalore 12
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Absorption
This theorem states:a + ab = a a(a+b) = a
To prove the first half of this theorem:a + ab = a . 1 + ab
= a (1 + b)= a (b + 1)= a (1)
a + ab = a
Saras M. Srivastava PGT CS, KV IISc, Bangalore 12
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DeMorgan’s Theorem
A key theorem in simplifying Boolean algebra expression is DeMorgan’s Theorem. It states: (a + b)’ = a’b’and (ab)’ = a’ + b’
Saras M. Srivastava PGT CS, KV IISc, Bangalore 12
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Truth Table to Boolean Expression
Converting a truth table to an expression Each row with output of 1 becomes a product term Sum product terms (SOP) together.
x00001111
y00110011
z01010101
G00010011
xyz + xyz’ + x’yz
Any Boolean Expression can be represented in sum of products form!
Saras M. Srivastava PGT CS, KV IISc, Bangalore 12
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Equivalent Circuit Representations Number of 1’s in truth table output column equals AND terms for Sum-of-Products (SOP)
x y z
x00001111
y00110011
z01010101
G00010011
G = xyz + xyz’ + x’yz
G
x xx
xx
x
xx
x
Saras M. Srivastava PGT CS, KV IISc, Bangalore 12
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Minterms and Maxterms
Each variable in a Boolean expression is a literal
Boolean variables can appear in normal (x) or complement form (x’)
Each AND combination of terms is a minterm Each OR combination of terms is a maxterm
Saras M. Srivastava PGT CS, KV IISc, Bangalore 12
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Minterms and Maxterms: Example
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Minterms
x y z Minterm0 0 0 x’y’z’ m0
0 0 1 x’y’z m1
…1 0 0 xy’z’ m4
…1 1 1 xyz m7
: Maxterms
x y z Maxterm0 0 0 x+y+z M0
0 0 1 x+y+z’ M1
…1 0 0 x’+y+z M4
…1 1 1 x’+y’+z’ M7
Saras M. Srivastava PGT CS, KV IISc, Bangalore 12
Functions with Minterms Minterm number same as row position
in truth table (starting from top from 0) Shorthand way to represent functions
x00001111
y00110011
z01010101
G00010011
G = xyz + xyz’ + x’yz
G = m7 + m6 + m3 = Σ(3, 6, 7)
Saras M. Srivastava PGT CS, KV IISc, Bangalore 12
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Complementing Functions
x00001111
y00110011
z01010101
G00010011
G = xyz + xyz’ + x’yz
G’ = (xyz + xyz’ + x’yz)’
G’11101100
Can we find a simpler representation?
Saras M. Srivastava PGT CS, KV IISc, Bangalore 12
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Conversion Between Canonical Forms
Easy to convert between minterm and maxterm representations
For maxterm representation, select rows with 0’s
x00001111
y00110011
z01010101
G00010011
G = xyz + xyz’ + x’yz
G = m7 + m6 + m3 = Σ(3, 6, 7)
G = M0M1M2M4M5 = Π(0,1,2,4,5)
G = (x+y+z)(x+y+z’)(x+y’+z)(x’+y+z)(x’+y+z’)
Saras M. Srivastava PGT CS, KV IISc, Bangalore 12
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Karnaugh Maps
A Karnaugh map is a graphical tool for assisting in the general simplification procedure.
Two variable maps.
Three variable maps.
0A
1 11
00 01
0
1
BC
01 1
111 10
F=AB’C’ +AB C +ABC +ABC + A’B’C + A’BC’
0A
1 11
B0 1
0
1
F=AB +AB +AB
A B C F0 0 0 00 0 1 10 1 0 10 1 1 01 0 0 11 0 1 11 1 0 11 1 1 1
+
Saras M. Srivastava PGT CS, KV IISc, Bangalore 12
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Rules for K-MapsWe can reduce functions by circling 1’s in the
K-mapEach circle represents minterm reductionFollowing circling, we get minimized and-or
form.Rules to considerEvery cell containing a 1 must be included at
least once.The largest possible “power of 2 rectangle”
must be enclosed.The 1’s must be enclosed in the smallest
possible number of rectangles.Saras M. Srivastava PGT CS, KV IISc,
Bangalore 12
35
Karnaugh Maps Two variable maps.
0A
1 11
B0 1
0
1 F=A+B
Three variable maps.
F=A+B C +BC 0
A
1 11
00 01
0
1
BC
01 1
111 10
F=AB +AB +AB
F=AB’C’ +AB C +ABC +ABC + A’B’C + A’BC’
Saras M. Srivastava PGT CS, KV IISc, Bangalore 12
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Karnaugh MapsNumbering scheme based on Gray–code
e.g., 00, 01, 11, 10 Only a single bit changes in code for
adjacent map cells00 01
ABC
0
1
11 10
C
B
A
F(A,B,C) = m(0,4,5,7)
G(A,B,C) = 0 0
0 0
1 1
1 1C
B
A
1 0
0 0
0 1
1 1C
B
A
A
= AC + B’C’
Saras M. Srivastava PGT CS, KV IISc, Bangalore 12
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Karnaugh Maps for Four Inputs
Represent functions of 4 inputs with 16 minterms
Use same rules developed for 3-input functions
Saras M. Srivastava PGT CS, KV IISc, Bangalore 12
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Karnaugh map: 4-variable example
F(A,B,C,D) =
m(0,2,5,8,9,10,11,12,13,14,15)F = C + B’D’+ A’BD
D
A
B
1 0
0 1
0 1
0 0
1 1
1 1
1 1
1 1C
AB
CD
Saras M. Srivastava PGT CS, KV IISc, Bangalore 12
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Karnaugh maps: Don’t cares
f(A,B,C,D) = m(1,3,5,7,9) + d(6,12,13) without don't cares
f = + C’D
0 0
1 1
X 0
X 1D
A
1 1
0 X
0 0
0 0
B
C
A’D
CDAB
00
01
11
10
00 01 11 10
C f0 00 11 01 10 00 11 X100110011
D0101010101010101
10100XX00
A0000000011111111
+
B0000111100001111
+
Saras M. Srivastava PGT CS, KV IISc, Bangalore 12
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Saras M. Srivastava PGT CS, KV IISc, Bangalore 12
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Thank
YouSaras M. Srivastava PGT CS, KV IISc,
Bangalore 12
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