VLSI B.TECH LIST

BVM01. VLSI implementation of Fast Addition using Quaternary Signed Digit Number System 2013BVM02. Dramatically Low-Transistor-Count High-Speed Ternary Adders 2013BVM03. High Performance and Power Efficient 32-bit Carry Select Adder using Hybrid PTL/CMOS Logic Style 2013BVM04. A Parallel Multiplier - Accumulator Based On Radix – 4 Modified Booth Algorithms by Using Spurious Power

Suppression Technique2013BVM05. Transistor Level Design And Analysis Of Vedic Algorithm Based Low Power MAC-2013BVM06. High speed Modified Booth Encoder multiplier for signed and unsigned numbers. . 2013BVM07. Design and Implementation of UART Design with BIST Capability. 2013BVM08. Design and Implementation of PS2 Controller 2013BVM09. Design and implementation of two variable multiplier using KCM and Vedic mathematics 2013BVM010. A new Approach to implement Parallel Prefix adder in FPGA

BVM011. An efficient implementation of floating point multiplier 2013 BVM012. Design & Implementation Of 32-Bit Risc (MIPS) Processor 2013 BVM013. A Pico Blaze-Based Embedded System for Monitoring Applications2013BVM014. Design and Implementation of BPSK Communication Modulation2013BVM015. Content-Addressable Memory (CAM) Circuits and Architectures2013BVM016. Design and Implementation of Vedic Multipliers 2013BVM017. Design of FIR Filter on FPGAs using IP cores2013BVM018. High Speed ASIC Design of Complex Multiplier Using Vedic Mathematics- 2013BVM019. Design of low power TPG using LP-LFSR 2012BVM020. Design of low power high speed vlsi adder sub system2012BVM021. A hybrid low power adder for high-performance processor 2012BVM022. A very fast and low power carry select adder circuit2012BVM023. Nonlinear Multi-Error Correction Codes for Reliable MLC NAND Flash Memories 2012BVM024. Soft-Error-Resilient FPGAs Using Built-In 2-D Hamming Product Code2012BVM025. Efficient Majority Logic Fault Detection With Difference-Set Codes for Memory Applications 2012BVM026. FPGA implementation of binary coded Decimal digit adders and multipliers2012BVM027. On Modulo 2n þ + 1 Adder Design- 2012BVM028. Efficient Implementation Of 16-Bit Multiplier-Accumulator Using Radix Modified Booth Algorithm And Spst Adder

Using Verilog 2012BVM029. Accumulator Based 3-Weight Pattern Generation.2012BVM030. An efficient FPGA implementation of the Advanced Encryption Standard algorithm.2012BVM031. Design and Implementation of Hamming code algorithm for SOC bus CommunicationBVM032. Platform-Independent Customizable UART Soft-Core2012BVM033. A High Speed Wallace Tree Multiplier Using Modified Booth Algorithm for Fast Arithmetic Circuits 2012BVM034. A Fast Hybrid Carry-Look-ahead/Carry-Select Adder Design2012BVM035. Design and Implementation of an Eight Bit Multiplier Using Twin Precision Technique and Baugh-Woolley

Algorithm- 2012BVM036. A New Architecture for Signed Radix-2N Pure Array Multipliers2012BVM037. High Speed Truncation- Error -Tolerant Adder 2012BVM038. Implementation of ATE for digital integrated circuits2012BVM039. Design and Implementation of INIUART Controller. 2012BVM040. Design and Implementation of UART Controller2012BVM041. Design and Implementation of I2C Controller2012

BVM042. Design and Implementation of Reed Solomon Encoder 2012BVM043. FPGA Implementation of CRC with Error Correction 2012BVM044. Design and Implementation of Double Precision FPU Processor 2012BVM045. Design and Implementation of FMA 64 bit for SIMD processors2012BVM046. Design and Implementation of Huffman encoder for JPEG Compression2012BVM047. VLSI Implementation of Data Encryption Standard Algorithm2012BVM048. Design and Implementation of SPI Controller 2012BVM049. A Harmonic Signal Generator Based on DDS and SOPC 2012BVM050. An Adaptive Implementation of a Dynamically Reconfigurable K-Nearest Neighbour

Classifier On FPGA 2012BVM051. Implementation of Pipelined 2D-DCT and Quantization Architecture for JPEG Image Compression2012BVM052. FPGA Prototyping of Hardware Implementation of CORDIC Algorithm 2012BVM053. Improvement of the Orthogonal Code Convolution Capabilities Using FPGA Implementation 2012BVM054. AHB Interface With SPI Master By Using Verilog2012BVM055. Design of low power column bypass multiplier using FPGA- 2011BVM056. Low Power MAC Unit for DSP Processor 2011BVM057. Single Cycle Access Structure for Logic Test2011BVM058. A New Reversible Design of BCD Adder- 2011BVM059. Low Power Design Techniques Applied to Pipelined Parallel and Iterative CORDIC Design-2011BVM060. Design and Implementation of AES Algorithm2011BVM061. Design and Implementation of SD RAM2011BVM062. Design of Discrete Cosine Transform (DCT) processor on FPGA for Video Compression application2011BVM063. Fast Division Algorithm with a small Look Up table2011BVM064. Design and VLSI Implementation of DDR SDRAM Controller for High Speed Applications2011BVM065. VHDL Design and FPGA Implementation of Weighted Majority Logic Decoders2010BVM066. Design and Implementation of multi serial SOC for Aero space communication

2010BVM067. FPGA-based for Implementation of Multi-Serials to Ethernet Gateway2010BVM068. Design and Implementation of Beger's Encoder and Decoder2010BVM069. Implementation Of Chaotic Cellular Automaton with Binary Synchronization Property 2010BVM070. Fpga-Based Smart Sensor Implementation With Precise Frequency to Digital Converter For Flow Measurement2010BVM071. A High Throughput AMBA AHB Protocol 2010BVM072. Low Complexity digit Serial Montgomery Multipliers for special class of GF(n) 2010BVM073. Implementation of a Self-Motivated Arbitration Scheme for the Multilaye AHB Bus matrix2010BVM074. Controllable Arbitrary Integer Frequency Divider Based on VHDL2009BVM075. Power Efficient Pipelined Reconfigurable Fixed-Width Baugh-wooley Multipliers 2009BVM076. Implementation Modular Exponentiation Using Sliding Window Method2007BVM077. Design and Implementation of single precision FPU Processor2006BVM078. Design and Implementation of FMA 32 bit for SIMD processors2006BVM079. Efficient Iterative Techniques for Soft Decision Decoding of Reed-Solomon Codes 2005 BVM080. Design and Implementation of CAN Controller 2005BVM081. The CSI Multimedia Architecture 2005BVM082. Measurement and Evaluation of Power Analysis Attacks on Asynchronous S-BoxBVM083. Technique of LFSR Based Test Generator Synthesis for Deterministic and Pseudorandom Testing.BVM084. Efficient Built-in Self-Repair Strategy for Embedded SRAM with Selectable RedundancyBVM085. Design and Implementation of Hamming code algorithm for SOC bus CommunicationBVM086. Development of PCI bus arbiter multi processor environmentBVM087. Design and Implement of FFT Processor for OFDMA System Using FPGABVM088. Real Time Simulation of a FPGA Based Space Vector PWM Controller

BVM089. Vhdl Simulation of Peak Detector, 64-Bit BCD Counter and Reset Automatic Block for PD Detection System Using FPGA

BVM090. Design and Implementation of Viterbi AlgorithmBVM091. Common Architecture for LDPC CodesBVM092. FPGA Based Implementation of Communication ModulationBVM093. A Lossless Data Compression and Decompression Algorithm and Its Hardware ArchitectureBVM094. 8051 Micro controller Synthesizable model and implementation on FPGABVM095. Development of intellectual property for local interconnect network for automobile sensor interface applicationBVM096. Design and implementation of Finite impulse response filtersBVM097. Development of Huffman encoder for MPEG-2video encoding applicationsBVM098. Development of Video display processor on FPGABVM099. Design and analysis of low density parity check encoder for fixed mobile communication systemsBVM0100. Design analysis of 1-GIGABIT Ethernet Media acess controller(GEMAC) Core for Full-duplex operations BVM0101. Design of turbo convolutional Code decoder for 3GPP Wireless mobile communication systemsBVM0102. Design and implementation of orthogonal frequency division multiple access modem on FPGABVM0103. Development of Keyboard controller for single board computer based on FPGABVM0104. FPGA Implementation of an Advanced Traffic Light Controller using Verilog HDLBVM0105. AMBA BUS BASED APB –I2C Protocol

BVM0106. AHB – Master to Slave Configuration

BVM0107. VLSI architecture of elimination undesirable cross talk

BVM0108. Dual Methodology high performance Multiplier

BVM0109. High Throughput DCT Using Parallel processing and pipelining

BVM0110. Design of 16- Bit RISC processor

BVM0111. A Robust and Efficient method for Error Detection and Correction in Memories

BVM0112. Bus Encoder For Crosstalk Avoidance In RLC Modeled Interconnects

BVM0113. Design and Implementation of MAC unit

BVM0114. Efficient Iterative Techniques for Soft Decision Decoding