by kevin banovic´ · and amer samarah for their advice on circuit design and practical information...

MIXED-SIGNAL ARCHITECTURES FOR SPECTRUM SENSING

by

Kevin Banovic

A thesis submitted in conformity with the requirementsfor the degree of Doctor of Philosophy

Graduate Department of Electrical and Computer EngineeringUniversity of Toronto

c© Copyright 2016 by Kevin Banovic

AbstractMixed-Signal Architectures for Spectrum Sensing

Kevin BanovicDoctor of Philosophy

Graduate Department of Electrical and Computer EngineeringUniversity of Toronto

2016

The radio spectrum is subject to temporal and geographic variations and measurements in-

dicate low utilization below 6GHz. In response, the Federal Communications Commission sent

a notice of proposed rulemaking to facilitate cognitive radio use in the licensed digital televi-

sion bands. Cognitive radios identify unused spectrum segments for data transmission while

minimizing interference with licensed radios. Spectrum sensing is the enabling technology

and detects the presence of a signal within a frequency band. Mixed-signal architectures of-

fer potential power savings by performing signal detection in the analog domain, significantly

reducing the analog-to-digital converter (ADC) sampling rate.

The integrating mixer is a novel mixed-signal architecture for spectrum sensing that is based

on the short-time Fourier transform (STFT). The architecture consists of a folded double bal-

anced mixer with capacitive loads that implements current-domain windowing in the first stage

while downconversion mixing and integration is implemented in the second stage. A load ca-

pacitor array enables integration with programmable time constant. A prototype was designed

and fabricated in IBM’s 0.13µm CMOS process. The measured results indicate an average

dynamic range (DR) of 24.2dB over a 2.2GHz bandwidth (BW) with a power dissipation of

1.55mW.

The integrating mixer architecture is extended by utilizing binary-weighted load capaci-

tors, which integrates the STFT signal and acts as the sampling capacitors for a successive

approximation register (SAR) ADC. An array of folded mixers are utilized to remove current

restrictions on the selection of the window function, which improves side-lobe reduction and

fall off in the frequency domain. A prototype was designed and fabricated in IBM’s 0.13µm

ii

CMOS process. The measured results indicate an average DR of 26.8dB over a 1.25GHz BW.

The integrated SAR ADC achieves a peak signal-to-noise-and-distortion ratio of 45.4dB at a

sampling frequency of 200kHz for an effective number of bits of 7.25. The power dissipation

is 0.88mW for a full quadrature implementation.

In comparison to recent spectrum sensing implementations, the integrating mixer proto-

types achieve the lowest power dissipation while obtaining a DR that falls within the re-

ported range. The prototypes are well suited for integration within low power cognitive radio

transceivers that target portable IEEE 802.22 applications.

iii

AcknowledgementsFirst and foremost, I would like to express my sincere gratitude and appreciation to my su-pervisor Professor Tony Chan Carusone for all his guidance and support over the years. Hisinitiative led me to an internship with Synopsys through the Mitacs Accelerate program and asa finalist at the Broadcom Foundation University Research Competition. I would like to thankProfessor Sebastian Magierowski from the Lassonde School of Engineering and Computer Sci-ence at York University for agreeing to be the external examiner for my final Ph.D. defense.I would like to thank Professor Glenn Gulak and Professor Antonio Liscidini for their partic-ipation in my Ph.D. exam committee and Professor Elvino Sousa for serving as the chair formy internal Ph.D. defense and as an examiner for my final Ph.D. defense. I much appreciatedtheir professionalism and feedback throughout the process. I would also like to thank ProfessorAli Sheikholeslami for being on the committee for my proposal and subsequent reviews. Atthis time I would also like to thank Professor Gulak once again for introducing me to the fieldof cognitive radio and for giving me an opportunity to pursue my degree at the University ofToronto.

I’ve been fortunate enough to meet many future colleagues and make some life-long friendsduring the course of my graduate studies. Kentaro Yamamoto and Pradip Thachile stood upfor me at my wedding. I went skydiving with Oleksiy Tyshchenko following one of six tripsto the San Francisco Bay Area for ISSCC. Pradip introduced me to SLR photography andover the years we’ve dabbled in a number of different areas of photography from darkroomphoto processing to large format digital printing to studio photoshoots. A group of us fromElectronics, including Ahmed Gharbiya, even went on a three day canoe trip to AlgonquinPark. More on the academic side, I would like to thank Masum Hossain, Meysam Zargham,and Amer Samarah for their advice on circuit design and practical information on layout in theCMRF8SF design kit. I would like to thank my fellow students in BA5000 and BA5158 whohave all had a positive impact on me in one way or another.

I would like to thank my family for all their love, support, encouragement and patienceover the years. My parents Monika and Josip Banovic were instrumental in getting me settledin a new city and environment, always there to support me along the way. My brother ChrisBanovic was always willing to lend a hand in support, even if it was a bit reluctant at times! Iwould like to thank my wife, Jelkica Banovic, for all the patience and sacrifices she has made,working from home to watch our son and always providing encouragement. I would also liketo thank our son Luka Banovic for all the joy he adds to our lives.

Lastly, I would like to thank the National Sciences and Engineering Research Council ofCanada, Ontario Graduate Scholarship, Mitacs and the Canadian Microelectronics Corporationfor their financial and technical support during the course of my graduate studies.

iv

Contents

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ivList of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viList of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ixList of Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi

1 Introduction 11.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Spectrum Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.3 Challenges and Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . 71.4 Receiver Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91.5 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111.6 Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2 Spectrum Sensing Architectures 132.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.2 FFT-based Energy Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.3 Cyclostationary Feature Detector . . . . . . . . . . . . . . . . . . . . . . . . . 152.4 STFT-based Energy Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . 172.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3 Integrating Mixer Architecture 203.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203.2 Integrating Mixer Design and Analysis . . . . . . . . . . . . . . . . . . . . . . 20

3.2.1 Window Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.2.2 Digital Window Generation and Synchronization . . . . . . . . . . . . 253.2.3 Current-Steering Digital-to-Analog Converter . . . . . . . . . . . . . . 263.2.4 Integrating Mixer Circuit Design . . . . . . . . . . . . . . . . . . . . . 283.2.5 Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323.2.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

v

3.3 Integrating Mixer Implementation . . . . . . . . . . . . . . . . . . . . . . . . 363.3.1 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373.3.2 Integrator Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 393.3.3 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 393.3.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.4 Comparisons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4 Integrating Mixer SAR Architecture 494.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494.2 Integrating Mixer SAR Design and Analysis . . . . . . . . . . . . . . . . . . . 49

4.2.1 Binary-Weighted SAR ADC . . . . . . . . . . . . . . . . . . . . . . . 514.2.2 Window Function and Digital Generation . . . . . . . . . . . . . . . . 544.2.3 Integrating Mixer SAR Circuit Design . . . . . . . . . . . . . . . . . . 584.2.4 Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644.2.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

4.3 Integrating Mixer SAR Implementation . . . . . . . . . . . . . . . . . . . . . 674.3.1 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694.3.2 SAR ADC Measurement Results . . . . . . . . . . . . . . . . . . . . . 714.3.3 Analog Measurement Results . . . . . . . . . . . . . . . . . . . . . . 764.3.4 Digital Measurement Results . . . . . . . . . . . . . . . . . . . . . . . 804.3.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

4.4 Comparisons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

5 Conclusion 895.1 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

A Spectrum Amplitude Estimation 92

B Additional Implementation Results 94

vi

List of Figures

1.1 Measurement of spectrum utilization in downtown Berkeley. . . . . . . . . . . 21.2 Cognitive radio concept to increase spectrum utilization. . . . . . . . . . . . . 31.3 Classification of spectrum sensing techniques. . . . . . . . . . . . . . . . . . . 41.4 MRSS receiver and energy detector. . . . . . . . . . . . . . . . . . . . . . . . 51.5 RRSI energy detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.6 Nonlinear distortion present for two tones in a low-IF receiver. . . . . . . . . . 71.7 Feedforward architecture for time domain interference cancellation. . . . . . . 81.8 Receiver architectures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101.9 Simplified Weaver image-reject architecture. . . . . . . . . . . . . . . . . . . . 10

2.1 Digital realization of FFT-based energy detector. . . . . . . . . . . . . . . . . . 142.2 Digital realization of cyclic periodogram based feature detector. . . . . . . . . 162.3 Mixed-signal realization of STFT-based energy detector. . . . . . . . . . . . . 18

3.1 Integrating mixer block diagram implementing the STFT in the analog domain. 213.2 Conceptual integration of windowing in a double balanced mixer. . . . . . . . . 223.3 Normalized current and transconductance window functions simulated with

Spectre and the corresponding α-value. . . . . . . . . . . . . . . . . . . . . . 233.4 Frequency domain response of the window function for α = 0.75 and α = 0.85. 243.5 Digital window generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253.6 Digital control signal waveforms and external ADC timing. . . . . . . . . . . . 263.7 5-bit thermometer coded CS-DAC and filtering current mirror schematic. . . . 273.8 Integrating mixer schematic with optional bleeding current sources. . . . . . . 293.9 Integrating mixer equivalent circuit for discharging capacitive loads during the

reset mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313.10 Integrating mixer integrator waveform simulation for fw = 1MHz and window-

ing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333.11 Integrating mixer integration power over process corners . . . . . . . . . . . . 343.12 Integrating mixer integration linearity over process corners. . . . . . . . . . . . 34

vii

3.13 Die microphotograph of integrating mixer prototype . . . . . . . . . . . . . . . 363.14 Integrating mixer PCB block diagram. . . . . . . . . . . . . . . . . . . . . . . 373.15 Populated integrating mixer PCB photograpgh. . . . . . . . . . . . . . . . . . 383.16 Test setup for integrating mixer. . . . . . . . . . . . . . . . . . . . . . . . . . 393.17 Integrating mixer integrator waveforms. . . . . . . . . . . . . . . . . . . . . . 403.18 Integrating mixer: spectrum estimate for a tone at 500MHz. . . . . . . . . . . . 413.19 Integrating mixer: spectrum estimates for a tone at 2.99GHz. . . . . . . . . . . 423.20 Integrating mixer: dynamic range over 0.5GHz to 3GHz for fw = 1MHz and

fw = 2MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433.21 Integrating mixer: 1dB compression for fw = 1MHz and fw = 2MHz. . . . . . 44

4.1 Block diagram of the integrating mixer SAR illustrated for a single path of anSTFT-based spectral estimate. . . . . . . . . . . . . . . . . . . . . . . . . . . 50

4.2 N-bit differential SAR architecture with bit cycling for bit bN−1. . . . . . . . . 514.3 Equivalent circuits for binary-weighted SAR operating modes including capac-

itor discharging for application in the integrating mixer architecture. . . . . . . 534.4 SAR control logic: differential sequencer and code register. . . . . . . . . . . . 554.5 Integrating mixer SAR control and output waveforms. . . . . . . . . . . . . . . 564.6 Frequency domain response of the window function for α = 0.5 and α = 0.85. 574.7 Integrating mixer SAR schematic. . . . . . . . . . . . . . . . . . . . . . . . . 594.8 Comparator input voltage versus SAR iteration. . . . . . . . . . . . . . . . . . 624.9 Double-tail voltage sense amplifier with SR latch, used as the SAR ADC com-

parator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634.10 Normalized total transconductance window function and corresponding α-value. 644.11 Integrating mixer SAR integration power over process corners . . . . . . . . . 654.12 Integrating mixer SAR integration linearity over process corners. . . . . . . . . 664.13 Die microphotograph of integrating mixer SAR prototype . . . . . . . . . . . . 684.14 Integrating mixer SAR PCB block diagram. . . . . . . . . . . . . . . . . . . . 694.15 Populated integrating mixer SAR PCB photograpgh. . . . . . . . . . . . . . . 704.16 Test setup for integrating mixer SAR. . . . . . . . . . . . . . . . . . . . . . . 704.17 SAR ADC: measured output power spectrum for fs = 200kHz. . . . . . . . . . 724.18 SAR ADC: measured SFDR, SNR, and SNDR for single-tone input versus (a)

input amplitude, (b) sampling frequency, and (c) input frequency. . . . . . . . . 734.19 SAR ADC: measured power versus sampling frequency. . . . . . . . . . . . . 754.20 SAR ADC: measured DNL and INL. . . . . . . . . . . . . . . . . . . . . . . . 754.21 SAR ADC: measured two-tone power spectrum for fs = 250kHz. . . . . . . . . 76

viii

4.22 Integrating mixer SAR analog testing: spectrum estimates for a tone at 0.5GHzfor all window frequencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

4.23 Integrating mixer SAR analog testing: dynamic range from 0.5Ghz to 1.4GHzfor fw = 250kHz and fw = 500kHz. . . . . . . . . . . . . . . . . . . . . . . . 78

4.24 Integrating mixer SAR analog testing: 1dB Compression for fw = 250kHz andfw = 500kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

4.25 Integrating mixer SAR digital testing: spectrum estimates for a tone at 0.5GHz. 814.26 Integrating mixer SAR digital testing: dynamic range over 0.5GHz to 1.3GHz. . 824.27 Integrating mixer SAR digital testing: 1dB compression. . . . . . . . . . . . . 83

B.1 Integrating mixer: dynamic range from 0.5Ghz to 3GHz for fw = 1.33MHzand fw = 4MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

B.2 Integrating mixer: 1dB compression for fw = 1.33MHz and fw =4MHz. . . . . 96B.3 Integrating mixer SAR analog testing: dynamic range from 0.5Ghz to 1.4GHz

for fw = 333kHz and fw = 1MHz. . . . . . . . . . . . . . . . . . . . . . . . . 97B.4 Integrating mixer SAR analog testing: 1dB compression for fw = 333kHz and

fw =1MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

ix

List of Tables

1.1 IEEE 802.22 DTV band operating restrictions for portable devices. . . . . . . . 31.2 Power dissipation of receiver implementations incorporating spectrum sensing. 5

2.1 Window function properties. . . . . . . . . . . . . . . . . . . . . . . . . . . . 172.2 Comparison between STFT and FFT-based energy detectors. . . . . . . . . . . 19

3.1 Hann-Hamming window function properties for α = 0.75 and α = 0.85. . . . . 243.2 5-bit binary to thermometer encoder logic . . . . . . . . . . . . . . . . . . . . 263.3 Cutoff frequencies of current mirror filter . . . . . . . . . . . . . . . . . . . . 283.4 Integrating mixer design parameters. . . . . . . . . . . . . . . . . . . . . . . . 303.5 Integrating mixer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313.6 Integrating mixer corner simulation result summary. . . . . . . . . . . . . . . . 333.7 Integrating mixer power summary. . . . . . . . . . . . . . . . . . . . . . . . . 353.8 List of key components on the integrating mixer PCB. . . . . . . . . . . . . . . 373.9 Integrating mixer: measurement result summary. . . . . . . . . . . . . . . . . 423.10 Integrating mixer: power summary. . . . . . . . . . . . . . . . . . . . . . . . . 453.11 Comparison of mixed-signal spectrum sensing implementations based on en-

ergy detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.1 Integrating mixer SAR design parameters. . . . . . . . . . . . . . . . . . . . . 604.2 Integrating mixer SAR modes . . . . . . . . . . . . . . . . . . . . . . . . . . 604.3 Integrating mixer SAR corner simulation summary. . . . . . . . . . . . . . . . 664.4 Integrating mixer SAR power simulation summary. . . . . . . . . . . . . . . . 674.5 List of key components on the integrating mixer SAR PCB. . . . . . . . . . . . 694.6 SAR ADC: measurement result summary. . . . . . . . . . . . . . . . . . . . . 744.7 Integrating mixer SAR analog testing: measurement result summary. . . . . . . 774.8 Integrating mixer SAR analog testing: third-order intercepts. . . . . . . . . . . 804.9 Integrating mixer SAR analog testing: power summary. . . . . . . . . . . . . . 804.10 Integrating mixer SAR digital testing: measurement result summary. . . . . . . 81

x

4.11 Integrating mixer SAR digital testing: third-order intercepts. . . . . . . . . . . 844.12 Integrating mixer SAR digital testing: power summary. . . . . . . . . . . . . . 844.13 Comparison of mixed-signal spectrum sensing implementations based on en-

ergy detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

xi

List of Acronyms

ADC Analog-to-digital converter

AGC Automatic gain control

AWGN Additive white Gaussian noise

BW Bandwidth

BPF Bandpass filter

CORDIC Coordinate rotation digital computer

CS-DAC Current switching digital-to-analog converter

DAC Digital-to-analog converter

DBW Detection bandwidth

DFF D flip-flop

DNL Differential non-linearity

DR Dynamic range

DSP Digital signal processing

DTV Digital television

DWG Digital window generator

DUT Design under test

ECMA European Computer Manufacturers Association

ESR Equivalent series resistance

xii

ENBW Equivalent noise bandwidth

ENOB Effective number of bits

ETSI European Telecommunications Standards Institute

FAM FFT accumulation method

FCC Federal Communications Commission

FFT Fast Fourier transform

FPGA Field-programmable gate array

IEEE Institute of Electrical and Electronics Engineers

IF Intermediate frequency

IMD Inter-modulation distortion

INL Integer non-linearity

LDO Low drop out

LNA Low-noise amplifier

LO Local oscillator

LPF Lowpass filter

LSB Least significant bit

LUT Lookup table

MBAN Medical body area network

MBMS Multimedia broadcast muticast service

MIMCAP Metal-insulator-metal capacitor

MOSFET Metal-oxide-semiconductor field-effect transistor

MSB Most significant bit

MUX Multiplexer

NBW Noise bandwidth

xiii

NMOS N-channel MOSFET

OFDM Orthogonal frequency division multiplex

OIP3 Output third-order intercept point

PLL Phase-locked loop

PCB Printed circuit board

PMOS P-channel MOSFET

QFN Quad-flat no-leads

RF Radio frequency

RMS Root mean square

SAR Successive approximation register

SDR Software-defined radio

SFDR Spurious-free dynamic range

SIR Signal-to-interference ratio

SNDR Signal-to-noise-and-distortion ratio

SNR Signal-to-noise ratio

SSCA Strip spectral correlation algorithm

STFT Short-time Fourier transform

THD Total harmonic distortion

UWB Ultra-wideband

VCO Voltage controlled oscillator

VGA Variable gain amplifier

WRAN Wireless regional area network

xiv

Chapter 1

Introduction

1.1 Motivation

There is a widespread belief that there is a lack of spectrum available for economical wirelesscommunication, which can be observed by the overlapping allocations from 9kHz to 300GHzin the National Telecommunications and Information Administration’s US frequency alloca-tion chart [1]. This belief is reinforced by the Federal Communications Commission’s (FCC)decision to allow ultra-wideband (UWB) communication underlay networks in the 3-10GHzband [2] and the allocation of 7GHz of unlicensed spectrum in the 57-64GHz band [3] for mm-wave communications. However, in order to sustain the growth of wireless communicationsystems, an order of magnitude increase in system capacity is required to support increasednumbers of users and higher data rates. This is not possible with the current method of allocat-ing fixed spectrum for licensed or unlicensed operation.

The actual utilization of the radio spectrum is subject to temporal and geographic varia-tions. Measurement of the radio spectrum taken in downtown Berkeley is illustrated in Figure1.1 [4], which indicates a maximum utilization of only 54.4% in the spectrum below 1GHzwhile only 17% utilization in the spectrum below 6GHz. A report by the FCC Spectrum Pol-icy Task Force confirms significant underutilized average capacity in spectrum resources under1GHz [5]. This trend occurs even in major US metropolitan areas when comparing the spec-trum utilization in the digital television (DTV) frequency bands. Measurements taken by theShared Spectrum Company in November 2005 in New York City and Chicago indicate 40.4%utilization and 52.2% utilization, respectively, in the DTV frequency bands [6]. In responseto the low utilization, the FCC sent a notice of proposed rule making (NPRM) to facilitateunlicensed negotiated or cognitive radio use in the licensed DTV bands.

Cognitive radios are reactive devices that identify unused spectrum segments known asspectral holes and dynamically adjust their transmission characteristics into these holes while

1

CHAPTER 1. INTRODUCTION 2

-100

-110

-120

-130

-140

-1500 1 2 3 4 5 6

PS

D (

dB

m/H

z)

Frequency (GHz)

Frequency (GHz)

Utilization (%)

0-1

54.4

1-2

35.1

2-3

7.6

3-4

0.25

4-5

0.13

5-6

4.6

Figure 1.1: Measurement of spectrum utilization in downtown Berkeley [4].

avoiding interference with licensed/primary users. As illustrated in Figure 1.2, cognitive radiotransmissions can be overlaid in spectral holes to increase spectrum utilization under the con-dition that the secondary users mitigate interference with the primary users. Cognitive radiois an extension of software-defined radios (SDR) envisioned by Joseph Mitola [7] and mustbe cognizant of spectral, temporal and spatial components of the environment in which theyare operating. Spectrum sharing is essential for efficient spectrum utilization and a number ofstandards are either complete or in development to facilitate dynamic spectrum access, includ-ing IEEE 802.22 Wireless Regional Area Networks (WRAN) [8], IEEE 802.11af (White-Fi),ECMA-392 [9], and ETSI Reconfigurable Radio Systems [10]. These standards deal with dy-namic spectrum allocation by license-exempt devices on a non-interfering basis in the spectrumallocated to the DTV broadcast service and fall within 47-910MHz1. In addition, the spectrumbetween 2360-2400MHz has been identified by the FCC as a candidate for medical body areanetworks on a secondary basis [11], while the spectrum between 3-10GHz remains a likelycandidate for cognitive radio networks in the near future.

The IEEE 802.22 WRAN standard [8] specifies the air interface and cognitive mediumaccess control of point-to-multipoint wireless regional area networks for fixed and portable de-vices operating in the DTV bands (54-862MHz). Fixed devices can operate in any non-adjacentchannel (except 3, 4 and 37) and transmit up to 4W power while they require geolocation to ac-cess available channels for broadcasting. Portable devices can operate with or without spectrumsensing. As per Table 1.1, in a non-spectrum sensing configuration, primary user avoidance isachieved with contact verification (mode-I) or geolocation (mode-II). Contact verification en-ables a mode-I portable device to stay within range of a fixed or mode-II portable device from

1IEEE 802.22: 54-862MHz, IEEE 802.11af: 54-790MHz, ECMA-392: 47-910MHz


(a) Radio spectrum with spectral holes. (b) Overlaid cognitive radio transmissions.

Figure 1.2: Cognitive radio concept to increase spectrum utilization.

Table 1.1: IEEE 802.22 DTV band operating restrictions for portable devices.

Mode I/II (Non-sensing) Mode I/II (Sensing)Channels 21-36, 38-51 21-36, 38-51Power Limit 40-100mW 40-50mWPrimary User Protection Contact verification/geolocation SensingTime Constraints Location checking every 60s detection in ≤ 2sAccuracy ±50m −114dBmPotential Applications Public safety, femtocell, MBMS Public safety, femtocell

which it obtained a list of broadcast channels [12]. Portable devices can transmit 100mW onnon-adjacent channels (40mW on adjacent channels) from 21-51 (except 37), and require ge-olocation every 60s. In a spectrum sensing configuration, a primary user must be detectedwithin 2s with a sensitivity of −114dBm and the transmit power is limited to 50mW on non-adjacent channels and 40mW on adjacent channels. Some of the potential applications includepublic safety networks, femtocells and multimedia broadcast multicast service (MBMS) [12].

Public safety networks are used by emergency personnel to respond to incidents and bycitizens to access emergency services. The current spectrum allocated to public safety is in-sufficient in many metropolitan areas while a lack of standardization across jurisdictions canprevent communication [12]. Cognitive radio technology can accommodate large data through-put and a large number of wireless users for short time periods but with low latency and highpriority [13]. A femtocell is a short range low-power cellular network that coexists alongsidemacrocells in a traditional cellular network. Femotocells are positioned to improve the indoorcoverage within a macrocell. Cognitive radio is ideal for resource allocation in order to maxi-mize the throughput using both licensed and unlicensed frequency bands while minimizing theinterference with nearby macrocells [14].

1.2 Spectrum Sensing

Spectrum sensing is the enabling technology behind cognitive radio, which detects the presenceof a primary user signal within frequency bands that may be composed of multiple signal


Figure 1.3: Classification of spectrum sensing techniques.

formats and channel bandwidths. In cognitive radio networks, spectrum sensing must be fastand accurate for effective spectrum utilization and minimal interference with primary usersignals. The sensitivity of the cognitive radio, known as the secondary user, must outperformthat of the primary user by a wide margin to prevent the hidden terminal effect, whereby thesecondary user suffers a large path loss to the primary user but the reverse is not true. Spectrumsensing deals with signal detection and seeks to distinguish between a band containing a signal,s(t), or Additive White Gaussian Noise (AWGN), n(t), and is given by the hypotheses:

H0 : x(t) = n(t)

H1 : x(t) = s(t)+n(t)

where H0 is the hypothesis the band is a spectral hole and H1 is the hypothesis the bandcontains a signal. Hypothesis H1 can be further expanded to determine whether s(t) is aprimary user or secondary user signal.

As illustrated in Figure 1.3, signal detection can be categorized into coherent and non-coherent detection, where coherent detectors typically require complete knowledge of the pri-mary user signal and full demodulation while non-coherent detectors require little to no priorknowledge of the primary user signal and do not require synchronization. Consequently, signaldetectors that employ non-coherent detection methods, such as energy detectors [15] [16] [17]and cyclostationary feature detectors [18] [19], are the main detectors employed in cognitiveradio transceivers due to complexity and time constraints. Matched filter detectors maximizethe signal-to-noise ratio (SNR) in an AWGN channel. The impulse response of the filter, h(t),is matched to the transmitted signal such that h(t) = s(T − t) [20], where s(t) is assumed to beconfined to 0≤ t ≤ T . Waveform detectors can be applied to primary user signals with knownsignal patters, such as embedded pilots in OFDM signals, and correlates the input signal withthe known pattern. Eigenvalue detectors compute the sample covariance matrix to obtain themaximum and minimum eigenvalues and compare the eigenvalue ratio to a threshold to de-termine if a signal is present [21]. Cyclostationary feature detectors compute the magnitudeof the cyclic spectrum, whose output peaks when the cycle frequency is equal to fundamental


Figure 1.4: MRSS receiver and energy detector [15].

Table 1.2: Power dissipation of receiver implementations incorporating spectrum sensing.

Component [15] [16] [17]RF filter + LNA + mixer 30.6mW 23mWa 32.4mW

VCO + PLL 61.2mW 34mW n/aLPF + VGA n/a n/a 3.8mW

Energy detector 43.2mW 23.8mW 7.7mWADC n/a 7.9mW n/aEtc. 45mW 33.9mWa n/a

180mW 122.6mW 43.9mWa Estimated from 56.9mW total for LNA + mixer + etc.

frequencies of the transmitted signal, such as the carrier frequency or cyclic prefix. These de-tectors are robust to noise uncertainty but sensitive to sampling offsets and are computationallyintensive. Energy detectors compute the energy contained in a frequency band (or estimate thefrequency spectrum) and compare the magnitude to the estimated noise power, which can be alimiting factor if reliable noise estimates cannot be obtained.

A number of mixed-signal spectrum sensing implementations based on energy detectionhave been proposed for cognitive radio [15] [16] [17]. The first implementation to target cog-nitive radio was for IEEE 802.22 WRAN applications and incorporated multi-resolution spec-trum sensing (MRSS)2 in a dual-mode direct-conversion receiver [15]. The MRSS receiver isillustrated in Figure 1.4, where the receive mode path is indicated with dashed lines. In thereceive mode, the MRSS prototype is a direct-conversion receiver with DC offset cancellation.In the spectrum sensing mode, the downconverted radio frequency (RF) input signal is corre-lated with a window function that has a lowpass filter (LPF) characteristic, which eliminatesthe need for a tunable LPF. The analog correlator consists of a multiplier and an integrator.A cos4(x) window is implemented with a digital window generator (DWG) that consists of a

2Equivalent to the short-time Fourier transform discussed in Section 2.4.


ADC

II0 II1 II2 II(N-1) IIN

IQ0 IQ1 IQ2 IQ(N-1) IQN

VBIAS

Digital Code

INI

INQ

N-stage Limiting Amplifiers

VRSSI

Rectifier

Figure 1.5: RRSI energy detector [17].

lookup table (LUT), 11-bit digital-to-analog converter (DAC), and a LPF. The minimum de-tectable sensitivity is −74dBm with a 32dB dynamic range and 35dB of interference rejection.A breakdown of the power dissipation is listed in Table 1.2. The energy detection componentconsists of the analog correlator with the DWG and consumes 43.2mW, which represents 24%of the total power dissipation. A second MRSS receiver implementation focused on power op-timization [16]. The minimum detectable sensitivity is −72.5dBm with a power consumptionof 23.8mW for 19.4% of the total power dissipation. However, the dynamic range was reducedto 24dB.

In [17], a harmonic rejection mixer was implemented that incorporates a received signalstrength indicator (RSSI) circuit for energy detection. The design targets cognitive radio up to2.4GHz, including IEEE 802.22 WRAN applications. As illustrated in Figure 1.5, the RSSIbased energy detector is comprised of limiting amplifiers, rectifiers and a passive RC filter.The sensitivity and dynamic range can be adjusted by turning on/off rectifier stages and chang-ing the current mirror ratios. In the high sensitivity mode, only the last few rectifier stagesare activated with large current. In the wide dynamic range mode, all the rectifier stages areactivated with low current. The minimum detectable sensitivity is −83dBm with 29− 48dBdynamic range. The high dynamic range is achieved for input powers between −30dBm to+18dBm and the overall gain is dependent on the mode of the RSSI detector. The energydetection component consists of the limiting amplifiers and rectifiers and consumes 7.7mW,which represents 17.5% of the total power dissipation. If the baseband LPF is added3, the de-sign consumes 11.5mW, which is still a substantial reduction from the MRSS implementations.

3The MRSS implementations do not require baseband filtering while it is required for the RSSI implementa-tion.


TIMAGE,1 TLO T1 T22 -T T1 2 2 -T T2 1 T T1 2+2T1 2T2

T

TIMAGE,2

F( )T

Figure 1.6: Nonlinear distortion present for two tones in a low-IF receiver.

1.3 Challenges and Considerations

A standard receiver downconverts one channel at a time and utilizes fixed image-reject filtersto eliminate channel images and/or LPF to eliminate harmonic images. Inter-modulation dis-tortion (IMD) effects can be mitigated with sufficient RF filtering since only a single channelis downconverted to baseband. In cognitive radio receivers, the desired bandwidth can rangefrom narrowband to wideband, requiring filters with a wide tuning range. If a large bandwidthconsisting of multiple channels is processed at once, image-reject filtering is required sincethere will be channels at non-zero intermediate frequencies (IF) after downconversion. In Fig-ure 1.6, distortion terms are illustrated for a bandwidth consisting of two tones. Clearly, if morethan two adjacent channels are processed simultaneously, distortion will be introduced sinceIMD products will fall within the desired bandwidth; this stresses the importance of linearity inthe front end for cognitive radio. The dynamic range of the analog-to-digital converter (ADC)can be a limiting factor if converting a wide bandwidth with a high signal-to-interference ra-tio (SIR). Time-domain samples that are clipped generate spurious components that degradethe spectral estimate, which can potentially bury primary user signals. Harmonic downmixingis another consideration for cognitive radio. If the local oscillator (LO) contains significantharmonic energy, such as the case for a square-wave LO, a harmonic image signal can be mis-taken as a signal within the band of interest if there is insufficient filtering. This is especiallyproblematic for wideband low-noise amplifiers (LNA) [22].

The design of high resolution wideband multi-mode ADCs for SDR and cognitive radiois an active area of research. A multi-mode discrete-time ∆Σ ADC with 100kHz-10MHz pro-grammable bandwidth that achieved a dynamic range of 88−67dB was presented in [23] whiletime-interleaved ADCs with ≥ 12-bit resolution and speeds up to 600MS/s have been reportedwith digital calibration techniques [24] [25] [26]. Alternatively, architectures that take advan-tage of spectrum estimation for cognitive radio to reduce the dynamic range requirements havebeen proposed [4] [27]. Interference estimation is proposed in [4] to estimate and attenuatethe interfering signal within the band of interest, reducing the dynamic range requirements.


Figure 1.7: Feedforward architecture for time domain interference cancellation [4].

This two stage process is illustrated in Figure 1.7, where estimation and attenuation are ac-complished in the first stage followed by automatic gain control (AGC) and quantization in thesecond stage. Interference estimation is achieved using a normalized least-mean-squares basedadaptive filter on the oversampled input signal. Simulations indicated up to a 35dB reductionin dynamic range. A complementary architecture is proposed in [27], where a compensatoris used to estimate the actual sample value when clipping is detected, thereby increasing thedynamic range. The input signal is oversampled (2−4×) and goes through a two stage inter-polation process. The first stage is polynomial spline interpolation, which uses a cluster of 4unclipped samples to estimate tangents and ultimately the value of clipped samples. Sinc filter-ing is then applied to the compensated clipped samples. Simulation results indicate 13−27dBof spurious noise suppression when 4× oversampling is applied [27]. This architecture avoidsadditional hardware by utilizing digital signal processing (DSP) with an increased ADC sam-pling rate.

Portable devices employing dynamic spectrum access is one of the main areas of researchfor cognitive radio. One of the potential applications is public safety networks, which requirepower efficient operation for mobile devices in order for emergency personnel to broadcastvoice, data and location based services. As listed in Table 1.1, the operating specifications forportable devices in IEEE 802.22 WRAN require spectrum sensing every 2s with a minimumdetectable power of −114dBm for license-exempt transmission in the 54-862MHz DTV band.Power efficient implementation of portable cognitive radio transceivers is crucial to extendtheir operation time between charging periods. As listed in Table 1.2, the spectrum sensingcomponent of recent mixed-signal implementations that target IEEE 802.22 WRAN consume17.5% to 24% of the total receiver power dissipation. Low power implementation of spec-trum sensing can result in a substantial overall power savings for a cognitive radio transceiver.Another potential application for low power spectrum sensing is medical body area networks(MBAN) in 2360-2400MHz band [12], which consist of sensors that monitor body functionsand transmit data wirelessly to a gateway or central control point. MBANs can be wearable orimplanted and operated inside the human body. Low power operation is crucial to extend the


life of battery powered MBANs.

1.4 Receiver Architectures

The traditional receiver is the superheterodyne architecture, which downconverts the RF inputsignal to one or more IF signals prior to baseband. A high-Q IF bandpass filter (BPF) with fixedbandwidth is utilized for image-rejection and implemented off-chip with a SAW or ceramicfilter. The absence of a single chip implementation and its fixed bandwidth disqualifies thisarchitecture for multi-standard SDR and cognitive radio, which leaves the direct-conversion,low-IF, and Weaver receiver architectures as potential candidates.

The most common receiver architecture is the direct-conversion receiver, which is illus-trated in Figure 1.8a. The RF input signal is downconverted to baseband in a single down-conversion stage. This eliminates channel images4 and allows the use of a LPF implementedon chip. DC offset is the main disadvantage which is enhanced by self-modulation of the LO.In addition, flicker noise around DC can reduce the achievable dynamic range. However, DCoffset and flicker noise are less of a concern for wideband signals where the direct-conversionarchitecture is the preferred single chip architecture. The low-IF architecture, illustrated inFigure 1.8b, eliminates DC offset by downconverting the RF input signal to low-IF and finaldownconversion is completed in the digital baseband. High-Q image-reject filtering is neededsince images are very close to desired channel. This requires double digital quadrature down-conversion or polyphase filtering with conventional downconversion [28]. Flicker noise is lessof an issue in this architecture. For narrow bandwidth applications, the low-IF architecture isthe preferred single chip architecture.

The Weaver receiver architecture, whose simplified version without quadrature outputs isillustrated in Figure 1.9, is an image-reject receiver architecture. Two consecutive quadraturedownconversions are performed on the input signal such that if the outputs are subtracted thechannel is passed while if the outputs are added the image is passed. This results in flexibleimage-rejection without a BPF, which can be applied to receivers with tunable bandwidths.Static and dynamic mismatch limits the typical image-rejection between 25dB to 40dB [29].However, modified Weaver architectures have been reported that are robust to gain and phasemismatches [30] while Weaver architectures that achieve 57dB image-rejection have been re-ported with calibration [29].

In wideband spectrum sensing applications, an image-reject receiver such as the Weaverreceiver is ideal since it can cancel the images caused by multiple channels at non-zero IF. In

4Only when the bandwidth consists of a single channel


(a) Direct-conversion receiver.

(b) Low IF receiver.

Figure 1.8: Receiver architectures.

Figure 1.9: Simplified Weaver image-reject architecture.


general, direct-conversion and Weaver receivers offer the most flexibility for spectrum sensingapplications.

1.5 Contributions

The focus of this dissertation is mixed-signal architectures for spectrum sensing with an em-phasis on non-coherent signal detection for implementation in cognitive radio networks. Theobjective is to develop power efficient spectrum sensing architectures that can be implementedin portable cognitive radio transceivers for operation in the 54-862MHz DTV band and targetsIEEE 802.22 WRAN applications including public safety networks. This dissertation describesthe operation, analysis, design, and implementation of a new spectrum sensing architecturebased on the short-time Fourier transform (STFT) for energy detection. The architecture con-sists of folded double balanced mixer with capacitive loads that implements current-domainwindowing in the first stage while downconversion mixing and integration are implemented inthe second stage. A two stage implementation enables the tail current of the input differentialpair to be maximized, thereby maximizing the transconductance for the windowing operation,while the bias current provided by the capacitive loads is minimized, thereby maximizing theintegration time. The detection bandwidth is set by the window function and the correspondingintegration period, which can be programmed with an array of load capacitors. Measurementresults for the prototype chip demonstrate an order-of-magnitude reduction in power dissipa-tion compared to recent spectrum sensing implementations. This contribution has been pub-lished in [31] and was presented at [32]. A second spectrum sensing architecture is developedfrom the first STFT based architecture. The design consists of a folded double balanced mixerarray that is connected to binary-weighted load capacitors that form the sampling capacitorsof a successive approximation register (SAR) ADC. The first stage of the mixer stage imple-ments current-domain windowing while the second stage implements downconversion mixing,integration and charge redistribution. Measurement results for the prototype chip demonstrateimproved side-lobe suppression, increased dynamic range, and a further decrease in powerdissipation. This contribution has been submitted for publication [33].

1.6 Outline

This dissertation is organized as follows:

Chapter 2. Spectrum Sensing Architectures A review of non-coherent detection methodsfor spectrum sensing including energy detection and cyclostationary feature detection.


Chapter 3. Integrating Mixer Architecture Design, analysis and experimental results of theintegrating mixer architecture that implements the STFT-based energy detector for spec-trum sensing. The design consists of a folded mixer with capacitive loads that imple-ments current domain windowing in the first stage and downconversion mixing and inte-gration in the second stage. The Hann-Hamming family of window functions is analyzedfor different values of the α-parameter while analytic expressions for the current andtransconductance window functions are compared to simulated waveforms. A prototypeof the integrating mixer is implemented in IBM’s CMRF8SF 0.13µm CMOS process,fabricated, packaged, and mounted on a custom printed circuit board (PCB) for labora-tory testing. Single-tone and two-tone tests over window frequencies are conducted tocharacterize the prototype and examine its performance. The prototype is compared torecent spectrum sensing implementations.

Chapter 4. Integrating Mixer SAR Architecture Design, analysis and experimental resultsof the integrating mixer SAR architecture that implements the STFT-based energy detec-tor and provides a digital estimate of the power spectrum. The design consists of a foldedmixer array that is connected to binary-weighted load capacitors that form the samplingcapacitors of a SAR ADC. The first stage of the mixer stage implements current-domainwindowing while the second stage implements downconversion mixing, integration andcharge redistribution. A prototype of the integrating mixer SAR is implemented in IBM’sCMRF8SF 0.13µm CMOS process, fabricated, packaged, and mounted on a customPCB for laboratory testing. Single-tone and two-tone tests over window and/or samplingfrequency are conducted to characterize the prototype and examine its performance. Theprototype is compared to the integrating mixer prototype and recent spectrum sensingimplementations.

Chapter 5. Conclusion A summary of the dissertation contributions is presented. Futurework including the implementation of the STFT-based integrating mixer in a Weaverreceiver architecture is suggested.

Chapter 2

Spectrum Sensing Architectures

2.1 Introduction

This chapter reviews non-coherent spectrum sensing architectures for energy detection andcyclostationary feature detection. The fast Fourier transform (FFT) based energy detector andcyclostationary feature detector are based on the FFT, which provides an efficient method to an-alyze the frequency spectrum and is a common component in the digital baseband of receivers.The STFT-based energy detector implements the windowed Fourier transform. Mixing andwindowing occurs in the analog domain while the window is generated in the digital domainusing a LUT or the CORDIC algorithm [34].

2.2 FFT-based Energy Detector

A time domain input signal x(t) is sampled with a frequency Fs to obtain N samples over aperiod of N · Ts, where N is an integer power-of-two and Ts = 1/Fs. The magnitude of thepower spectrum computed from a N-FFT is given by

|Sxx ( fk)|2 =1N

X(k)X∗(k) (2.1)

where fk = k ·Fs/N. The frequency resolution is given by ∆ f = Fs/N.An implementation of the FFT-based energy detector following direct downconversion is

illustrated in Figure 2.1, which consists of a N-FFT block whose output is correlated with itscomplex conjugate to obtain the magnitude of the power spectrum. This process is repeatedto obtain an average over L iterations. The 1/N term normalizes the FFT gain and is lumpedtogether with the averaging operation. The magnitude of the power spectrum is compared to athreshold, γ2

ED, which is selected based on the estimated noise power σ2n so as to meet a speci-

13

CHAPTER 2. SPECTRUM SENSING ARCHITECTURES 14

ΣL

NL1

2γED

ADC

LO

N-FFTSignalDetect

LNARF

f =F /2C S

*

2S (f ) xx kx(n)

TS

Figure 2.1: Digital realization of FFT-based energy detector.

fied probability of detection (PD) and probability of false alarm (PFA) pair. The computationalcomplexity for the energy detector scales with the FFT and is O (N +(N/2) log2 N).

The energy detector is limited by noise uncertainty such that there exists a SNR beyondwhich signal detection is not possible. This is referred to as the SNR wall. If the estimatednoise power is modeled as σ2

n ∈ [(1/ρ)σ2n ,ρσ2

n ], where σ2n is the nominal noise power and

ρ > 1 is a parameter that quantifies the size of the uncertainty, the SNR wall is given bySNRwall = (ρ2−1)/ρ [35]. In addition, a low pass filter with a cutoff frequency fc = Fs/2 isrequired prior to a high speed ADC to prevent aliasing.

One technique to overcome the SNR wall is cooperative energy detection, which utilizes themeasurements of several cognitive radios for signal detection [36] [37]. Consider a networkof M cooperative users which transmit their sensing data periodically to a base station via acommon control channel while the base station combines the sensing data to decide whetherthe frequency band contains a signal or is a spectral hole [37]. Suppose each user computes anN-FFT and L iterations are used for energy detection. The observed energy at the j-th user forthe k-th FFT bin is defined as

Yj(k) =1N

L

∑i=1

X j(k)X∗j (k) (2.2)

where the power is summed over L iterations. In the case of a soft combination scheme with M

weights,

w j

for 1≤ j ≤M, the weighted summation of the observed energies for k-th bin isdefined as [37]

Y (k) =M

∑j=1

w jYj(k). (2.3)

As the number of users approaches infinity, M→ ∞, it is shown in [38] that given a target PD,the PFA approaches zero irrespective of the SNR.

In summary, the FFT-based energy detector is a low complexity architecture that, whilelimited by noise uncertainty, can be successfully utilized in cooperative cognitive networks tomeet detection requirements in low SNR environments. Alternatively, energy detection can beutilized to quickly identify potential vacant portions of spectrum to perform detailed sensing


with a method such as cyclostationary feature detection, which is discussed in Section 2.3.

2.3 Cyclostationary Feature Detector

Modulated signals inherently contain cyclostationary features that arise from the inclusion ofone or more underlying periodicities such as sine-wave carriers, pulse trains, coding, hopingsequences, and cyclic prefixes. A signal x(t) can be modeled as second order cyclostationary ifits autocorrelation function, Rx(t,τ) = Ex(t + τ/2)x∗(t− τ/2), is periodic in time t for eachtime lag τ . The cyclic autocorrelation function for cycle frequency β is defined as [39] [40]

Rβx (τ) = lim

T→∞

1T

∫ T/2

−T/2x(t + τ/2)x∗(t− τ/2)e− j2πβ tdt (2.4)

which reduces to the standard autocorrelation function when β = 0. R0x(τ) can be considered

the DC component of the lag-product waveform in equation (2.4) while Rβx (τ) can be con-

sidered the AC component corresponding to the cycle frequency [39]. The cycle frequencyresolution is ∆β = 1/∆t, where ∆t is the length of the observation interval. In order to obtainreliable estimates, the time-frequency resolution must greatly exceed unity such that ∆t∆ f 1,where ∆ f is the frequency resolution [40]. As a consequence, ∆β ∆ f .

Second order cyclostationarity gives rise to specific signal-dependent correlation patternsfor β 6= 0 that can be used to identify and classify signals. Conversely, n(t) is wide-sense sta-tionary such that Rβ

n (τ) = 0 for β 6= 0, which allows signals to be distinguished from AWGN.The cyclic periodogram is used to analyze the correlation patters and is defined as [39] [40]

Sβ

XT ( f ) =1T

XT (t, f +β/2)X∗T (t, f −β/2) (2.5)

where T can represent either T = 1/∆ f or T = ∆t and XT (t,v) is the complex envelope of thenarrowband component of x(t) centered at v, which is defined as

XT (t,v) =∫ t+T/2

t−T/2x(u)e− j2πvudu. (2.6)

The cyclic periodogram of equation (2.5) can also be defined in terms of its Fourier transformsuch that

Sβ

XT ( f ) =∫ T/2

−T/2Rβ

x (τ)e− j2π f τdτ. (2.7)

An estimate of the cyclic periodogram can be obtained in the digital domain for a fixednumber of samples and with either time or frequency smoothing. The time (∆t, T → 1/∆ f )


X(k- i/2 +m)

X(k+ i/2 +m)

ADC

LO

N-FFTSignalDetectLNARF

f =F /2C S

*

x(n)

ΣM

NM1

2γCD

( ) 2

2S (f ) xΔt k Δf

βi

TS

Figure 2.2: Digital realization of cyclic periodogram based feature detector.

and frequency (∆ f , T → ∆t) smoothed cyclic periodograms are approximately equal under thecondition that ∆t∆ f 1. Here the focus is on the frequency smoothed cyclic periodogramwhere X∆t(·) is computed with the N-FFT and the correlation energy averaged over M FFTbins. The frequency smoothed cyclic periodogram for discrete time and frequency is definedas [41]

Sβix∆t ( fk)∆ f =

1MN

M−bM/2c

∑m=b−M/2c

X∆t

(fk +

⌊βi

2

⌋+m∆ f

)·X∗∆t

(fk−

⌈βi

2

⌉+m∆ f

)(2.8)

where ∆β = Fs/N such that βi = i ·∆β and⌈βi

2

⌉=

⌈i2

⌉∆β

⌊βi

2

⌋=

⌊i2

⌋∆β . (2.9)

The magnitude of the cyclic power spectrum is given by∣∣∣Sβi

x∆t ( fk)∆ f

∣∣∣2. The frequency res-olution is ∆ f = M ·Fs/N since the frequency is averaged across M FFT bins while the timeresolution is ∆t = N ·Ts since N samples are required to compute the FFT. Therefore, the time-resolution product is ∆t∆ f = M where M 1. The parameters β and f form a bi-frequencyplane that is bounded by the diamond-shaped region given by−(Fs/2−∆ f )≤ f ≤ (Fs/2−∆ f )

and −(Fs−∆ f )≤ β ≤ (Fs−∆ f ).A digital implementation of the cyclic periodogram following direct downconversion is

illustrated in Figure 2.2, which consists of an N-FFT block and the summation of M correla-tions for a single ( f ,β ) bi-frequency estimate. The 1/N term normalizes the FFT gain and islumped together with the frequency averaging operation. The magnitude-squared is computedto obtain the cyclic power spectrum estimate, which is compared to a threshold, γ2

CD, to detectthe presence of a signal. In theory γ2

CD → 0 as T → ∞ but residual estimation error due tofinite number of samples prevents complete signal separation from noise and γ2

CD is chosen tomeet a specified PD and PFA pair. The computational complexity of the cyclic periodogram isO (NM+(N/2) log2 N). Efficient methods to implement the cyclic spectrum exist such as theFFT accumulation method (FAM) and the strip spectral correlation algorithm (SSCA) [41].


Table 2.1: Window function properties.

Windowa Side lobe Fall off DC Gain ENBWb 3-dB BW 6-dB BW(dBc) (dB/octave) ( fw)c ( fw)c ( fw)c

Rectangle −13 −6 1.0 1.0 0.89 1.21Triangle −27 −12 0.5 1.33 1.28 1.78

Hann −32 −18 0.5 1.5 1.44 2.0cos4 (x) −47 −30 0.38 1.94 1.86 2.59

Hamming −43 −6 0.54 1.36 1.3 1.81Blackman −58 −18 0.42 1.73 1.68 2.35a Refer to [45] for additional window functions and properties.b Equivalent noise bandwidth: the BW of a rectangular filter that passes the same

amount of broadband noise.c FFT bins for a digital implementation.

The cyclostationary feature detector is sensitive to sampling offset which can diminish theamplitude of features in the cyclic spectrum [13]. Additionally, there exists an SNR wall sincecomplete signal separation from noise is not achieved. However, the SNR wall is reduced bya factor of

√NC such that SNRwall = (ρ2−1)/(ρ

√NC), where NC is the number of samples

taken during the coherence time [42]. In addition, a low pass filter with a cutoff frequencyfc = Fs/2 is required prior to a high speed ADC to prevent aliasing.

In summary, the cyclostationary feature detector is able to detect and classify signals in lowSNR environments but is computationally intensive as computations are required over multiplecycle frequencies. Cyclostationary feature detection is most effective when applied to smallsegments of the spectrum for signal detection so as to reduce the processing delay.

2.4 STFT-based Energy Detector

The STFT [43] [44] augments the Fourier transform with a window function that shapes thefrequency response and restricts its integral to a finite time segment. The continuous-timeSTFT is defined as

Xτ ( f ) =∫

τ/2

−τ/2x(t)w(t,τ)e− j2π f tdt (2.10)

where w(t,τ) is the window function and τ is the period of the window function. The band-width (BW) is on the order of 1/τ [39] while the detection bandwidth (DBW) is set by the 3-dBbandwidth of the window function. The magnitude of the power spectrum can be calculateddirectly as the magnitude-squared of the STFT such that |Sxx ( f )|2 = |Xτ ( f )|2.

Selection of the widow function depends on a number of factors such as highest side-lobe,side-lobe fall off, DC gain and BW. Table 2.1 lists the properties of some common windowfunctions used in DSP.


Figure 2.3: Mixed-signal realization of STFT-based energy detector.

As illustrated in Figure 2.3, the STFT can be implemented directly with two mixing/mul-tiplication stages followed by an integration stage. The input RF signal is mixed with the LOsignal to obtain an IF signal that is multiplied by a window function, w(t), prior to integration.An ADC synchronized to the end of the integration period samples the STFT with signal TW

and the magnitude-squared is computed in the digital domain to obtain a spectral estimate atthe LO frequency. A threshold detector compares the spectrum estimate with a threshold basedon the noise floor estimate, γ2

ED, to determine if a signal is present, where γ2ED is chosen to meet

a specified PD and PFA pair.The STFT-based energy detector is limited by noise uncertainty and the SNR wall as for

the FFT-based energy detector. However, the ADC speed requirements are relaxed as the inte-gration time is much lower than the symbol period and the low pass filter is eliminated. Themethod of cooperative spectrum sensing can be equally applied while cyclostationary featuredetection can be performed directly on the output of the STFT for detailed sensing in segmentsof spectrum identified as potentially vacant.

In summary, the STFT-based energy detector is a low complexity architecture that reducesthe ADC speed requirements and incorporates low pass filtering thereby reducing power con-sumption over FFT-based energy detection. Although limited by noise uncertainty, it can besuccessfully utilized in cooperative cognitive networks to meet detection requirements in lowSNR environments. Alternatively, energy detection can be utilized to quickly identify potentialvacant portions of spectrum to perform detailed sensing with a method such as cyclostationaryfeature detection.

2.5 Conclusion

This chapter presented an overview of spectrum sensing techniques with a focus on non-coherent detection methods. The digital architectures are based on the FFT while the analogarchitecture is based on the application of windowing functions.

There are a number of factors to consider when choosing between digital and analog ar-chitectures for spectrum sensing. These include DBW, acquisition/processing time and power


Table 2.2: Comparison between STFT and FFT-based energy detectors.

STFT-based Energy Detector FFT-based Energy DetectorDetector Type analog digital

Sampling frequency fw fsDetection BW ≈ fw fs/NFFT

Acquisition Time 1/ fw NFFT/ fsBW ≈ fw fs/2

ADC requirementsa ≥ 7-bit at ≤ 1MSPS ≥ 7-bit at ≥ 10MSPSAnti-alias filter no yes

Processing serial parallelOutput latency small large

a Refer to J. Park [46].

dissipation. A comparison between STFT and FFT-based energy detectors is given in Ta-ble 2.2. In the case of a fixed DBW, ∆ f , both detectors have the same acquisition time, 1/∆ f ,while the FFT-based energy detector will require a sampling frequency scaled by the FFT size,fs = NFFT · ∆ f . Conversely, the STFT-based detector requires half the number of samples(NFFT/2) to cover the same BW. The main advantage of the STFT-based detector over digi-tal implementations is the power dissipation, which is dominated by the ADC component inboth implementations. For example, if ∆ f = 100kHz and NFFT = 128, the STFT-based detec-tor requires a total acquisition time of 640µs to cover 6.4MHz with fw = 100kHz while theFFT-based detector requires 10µs with fs = 12.8MHz or 128× fw. As ADC power dissipationscales with sampling frequency, a significant reduction in power dissipation can be achievedwith STFT-based energy detection.

Chapter 3

Integrating Mixer Architecture

3.1 Introduction

This chapter presents the circuit design, analysis and experimental results for the integratingmixer and its main components. The integrating mixer is implemented in IBM’s CMRF8SF0.13µm CMOS process and targets integration within portable cognitive radio transceivers forIEEE 802.22 WRAN applications such as public safety networks. Simulations are performedusing Cadence Spectre circuit simulator while experimental results are presented for a pro-totype that is fabricated, packaged and mounted on a custom PCB. Section 3.2 presents thedesign and analysis of the integrating mixer including analysis of the Hann-Hamming familyof window functions, circuit design and simulations. Section 3.3 presents the method and ex-perimental results for the prototype integrating mixer for single-tone and two-tone tests overwindow frequencies. The prototype is compared to recent spectrum sensing implementationsin Section 3.4. Lastly, conclusions are stated in Section 3.5.

3.2 Integrating Mixer Design and Analysis

The integrating mixer implements the STFT-based energy detector discussed in Section 2.4.The STFT-based energy detector is well suited to low power implementation and time-domainintegration allows sub-Nyquist sampling. In order to reduce the number of stages, the windowfunction is implemented in the current-domain while integration is incorporated within themixer by utilizing capacitive loads. The integrating mixer operates in two modes: a reset modewhere both terminals of the capacitors are connected to VDD, resetting the accumulated signaland discharging the capacitors, and an integration mode where the capacitive loads providebias current while integrating the IF signal. The integration time is set by a programmable load

20

CHAPTER 3. INTEGRATING MIXER ARCHITECTURE 21

RFSpectralEstimate

ADC

LO

( )

w(t)

CS-DAC5-bitCounter

LUT

rsclk

IF

B2T

LO

i (t)w

i (t)w

t

RF

31-bitRegister

STFT

2

Figure 3.1: Integrating mixer block diagram implementing the STFT in the analog domain(B2T: binary to thermometer encoder).

capacitor bank, which determines the window frequency and DBW.A system block diagram of the integrating mixer is illustrated in Figure 3.1, where the digi-

tal input signals rs and clk control system operation. The input rs selects the mode of oper-ation where rs=‘0’ and rs=‘1’ correspond to reset and integration modes, respectively. Thewindow function is generated by a binary counter that cycles through the binary coefficientsstored in a LUT each integration period. A binary to thermometer encoder with registered out-put drives a thermometer coded current switching digital-to-analog converter (CS-DAC) thatimplements the window function in the current-domain and is mirrored to the integrating mixer.The LO signal and ADC are supplied off chip.

The design and analysis of the integrating mixer is divided into the following sections;the Hann-Hamming family of window functions is analyzed in Section 3.2.1 while the digitalwindow generator is presented in Section 3.2.2. The design of the CS-DAC which implementsthe digital window function in the current-domain is presented in Section 3.2.3. Analysis anddesign of the two-stage integrating mixer is presented in Section 3.2.4 while simulations areprovided in Section 3.2.5.


Figure 3.2: Conceptual integration of windowing in a double balanced mixer, where the tailcurrent is replaced with iw(t).

3.2.1 Window Function

A number of functions can be selected to implement the time-domain windowing operation,including the functions listed in Table 2.1 of Section 2.4. The Hann and Hamming functionsbelong to a family of window functions that are commonly utilized to minimize spectral leak-age in the FFT and are applied here to time-limit the STFT as well as provide low pass filtering.The Hann-Hamming window function is characterized by the parameter α and the continuous-time version is defined as

w(t,τ) =

α +(1−α) · cos(2π fwt) if |t| ≤ τ/20 otherwise (3.1)

where α = 0.5 and α = 0.54 for the Hann and Hamming functions, respectively.Implementing the window function in the current-domain eliminates the window function

multiplication stage in addition to providing low pass filtering after downconversion. As il-lustrated in Figure 3.2, in the context of a double balanced mixer, the current window func-tion, iw(t), replaces the constant tail current of the input differential pair. This restricts theselection of α in equation (3.1) since a minimum non-zero current, iw,min, is required by thedifferential pair. Furthermore, multiplication corresponds to the transconductance of the inputdifferential pair (i.e. gm1, gm2) which is proportional to the square-root of current1. Conse-

1The square-law only provides a rough estimate for short-channel devices and there is a small discrepancywhen comparing the normalized values of current to the square of the normalized transconductance in 0.13µmCMOS. At a normalized current of 0.5, the discrepancy is less than 5% and is negligible above a normalizedcurrent of 0.75.


Time (1/fw

)

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Norm

aliz

ed A

mplit

ude

0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

0.95

1

iw

α=0.75

gm

α=0.85

Figure 3.3: Normalized current and transconductance window functions simulated with Spec-tre and the corresponding α-value.

quently, an expression for α is derived using transconductance, where gm,min and gm,max isthe transconductance corresponding to iw,min and iw,max, respectively. Noting that gm,min corre-sponds to the phase±π in the cosine function, an expression for α can be obtained by replacingw(t,τ)→ gm,min/gm,max and cos(2π fwt)→−1 in equation (3.1) and solving for α such that

α =1+gm,min/gm,max

2(3.2)

where gm,min/gm,max is the normalized transconductance.A minimum normalized value of iw,min/iw,max = 0.5 is selected for the mixer tail current,

which corresponds to gm,min/gm,max = 1/√

2 such that α = 0.85. In Figure 3.3, the current andtransconductance window functions are illustrated over a single period. The current windowfunction closely follows α = 0.75 substituted in equation (3.1) while the transconductance win-dow function closely follows α = 0.85 substituted in equation (3.1). The diamonds and squaresare the simulated values for the current and transconductance window functions, respectively,while the dashed and solid lines are the window functions with α = 0.75 and α = 0.85, re-spectively. There is a close correlation between the simulated and analytical values, validating


Frequency (Fs/N)

-6 -4 -2 0 2 4 6

Norm

aliz

ed A

mplit

ude (

dB

)

-40

-35

-30

-25

-20

-15

-10

-5

0

α=0.75

α=0.85

Figure 3.4: Frequency domain response of the window function for α = 0.75 and α = 0.85.

Table 3.1: Hann-Hamming window function properties for α = 0.75 and α = 0.85.

α Side lobe Fall off DC Gain ENBWa 3-dB BW 6-dB BW(dBc) (dB/octave) ( fw)b ( fw)b ( fw)b

0.75 −21.4 −4.9 0.75 1.06 1.04 1.360.85 −16.8 −6.3 0.85 1.02 0.98 1.28a ENBW = ∑n w2(nT )/ [∑n w(nT )]2b FFT bins for a digital implementation.

the use of transconductance to implement the window function.The frequency-domain response of the window function in equation (3.1) for α = 0.75 and

α = 0.85 is illustrated in Figure 3.4. As listed in Table 3.1, the initial side-lobe is −21.4dBcwith a −4.9dB/octave fall off for α = 0.75 and −16.8dBc with a −6.3dB/octave fall off forα = 0.85. In general, increasing α within the range given by 0.5≤ α ≤ 1 results in greaterside-lobe oscillations, such that the initial side-lobe is −32dBc with a −18dB/octave fall offfor α = 0.5 and −13dBc with a −6dB/octave fall off for α = 1.


en sel x

x

d

5-bitBinary

Counter

Hardwired toV or 0VDD

5x32-bitLUT

32x1 MUX

31-bitRegister

y y

y

y

y

q

clk clk

31 3155

32x1 MUX

32 32

y4 y0

rs

en_win

clk

sel

x5 5 sel

Thermometer

Binary to

Encoder

CS-DAC

Figure 3.5: Digital window generation.

3.2.2 Digital Window Generation and Synchronization

The digital portion of the integrating mixer is limited to the generation of the window functioncoefficients, setting static parameters, and synchronization of the window function with theintegration mode of operation.

The window function period corresponds to the integration period, which is sampled 32times to reduce the hardware complexity such that fclk = 32 · fw. As illustrated in Figure 3.5, thewindow function coefficients for each integration period are generated by a 5-bit counter thatcycles through the coefficients stored in a 5x32 LUT. Quantization of the window coefficientsresult in a trade-off between complexity and increased side-lobe oscillations in the frequencydomain. Here, 5-bit quantization is selected since it minimizes the complexity while onlyincurring a 0.5dB penalty on the side-lobe oscillations. The LUT is implemented with five32x1 multiplexers (MUX), where the binary coefficients are hardwired to either 0V or VDD.Each MUX implements one bit of the 5-bit window function coefficient over the 32 samplesof the integration period. A binary to thermometer encoder maps the 5-bit binary input to 31thermometer outputs that drive the CS-DAC. The thermometer output yk = f (x0,x1,x2,x3,x4)

for k = 0 : 30 is given by Table 3.2, where each output can be implemented using a sequenceof 1 to 3 logic gates. A 31-bit register is inserted after the binary to thermometer encoder inorder to prevent glitches and is sampled on the falling clock edge.

The main control signal is rs such that rs =‘0’ and rs =‘1’ correspond to the reset andintegration modes, respectively. The signal rs is synchronized with the input signal clk suchthat the integration time is exactly 32 ·Tclk while the reset time is m ·Tclk, where m is an integerchosen to allow sufficient time for the load capacitors of the integrating mixer to reset (m = 32is chosen to obtain 50% duty cycle for testing). As illustrated in Figure 3.6, the external


Figure 3.6: Digital control signal waveforms and external ADC timing.

Table 3.2: 5-bit binary to thermometer encoder logic

yk = f (x0,x1,x2,x3,x4) for k = 0 : 30y0 = x0 + x1 + x2 + x3 + x4 y11 = x2x3 + x4 y22 = x0x1x2x4 + x3x4y1 = x1 + x2 + x3 + x4 y12 = (x0 + x1) · x2x3 + x4 y23 = x3x4y2 = x0x1 + x2 + x3 + x4 y13 = x1x2x3 + x4 y24 = (x0 + x1 + x2) · x3x4y3 = x2 + x3 + x4 y14 = x0x1x2x3 + x4 y25 = (x1 + x2) · x3x4y4 = (x0 + x1) · x2 + x3 + x4 y15 = x4 y26 = (x0x1 + x2) · x3x4y5 = x1x2 + x3 + x4 y16 = (x0 + x1 + x2 + x3) · x4 y27 = x2x3x4y6 = x0x1x2 + x3 + x4 y17 = (x1 + x2 + x3) · x4 y28 = (x0 + x1) · x2x3x4y7 = x3 + x4 y18 = (x0x1 + x2 + x3) · x4 y29 = x1x2x3x4y8 = (x0 + x3 + x2) · x3 + x4 y19 = (x2 + x3) · x4 y30 = x0x1x2x3x4y9 = (x1 + x2) · x3 + x4 y20 = (x0 + x1) · x2x4 + x3x4y10 = x0x1x3 + x2x3 + x4 y21 = x1x2x4 + x3x4

ADC sampling signal, Tw, is synchronized just prior to the end of the integration period. Thethermometer coefficients set the discrete values of the window function, w(n), and are delayedby Tclk/2 as they are sampled on the falling edge of the clock. The internal signals S1 and S2

are applied to the gates of a pair of NMOS switches that either enable or disable the currentmirrors between mixer stages based on the mode of operation. In practice, the signals rs, clk,and Tw are generated by a synchronous state machine.

3.2.3 Current-Steering Digital-to-Analog Converter

A 5-bit thermometer coded CS-DAC is designed to implement the current window function.Thermometer coding with unit current sources improves the differential non-linearity (DNL)and eliminates non-linear output glitches. A register is added prior to the CS-DAC, furtherreducing output glitches.

The current window function of equation (3.1) with α = 0.75 results in a constant DCcurrent, iw,max/2, and a time-varying current, 0→ iw,max/2. As illustrated in Figure 3.7, the


Figure 3.7: 5-bit thermometer coded CS-DAC and filtering current mirror schematic (d30 : d0are the thermometer coded inputs).


Table 3.3: Cutoff frequencies of current mirror filter

fw Capacitance Cutoff Frequency1MHz 4pF 9.8MHz

1.33MHz 3pF 13.1MHz2MHz 2pF 19.7MHz4MHz 1pF 39.4MHz

CS-DAC is implemented with 31 constant unit current sources in parallel with 31 thermometercoded unit current sources. In Table 3.4, the full design parameters and values are listed forthe CS-DAC implementation. The NMOS unit current sources are implemented with a largetransistor length, L = 4.5µm, to obtain good matching while the bias voltage, VB, is chosento maintain a high effective over-drive voltage of approximately Vov = 610mV. The NMOSpair M4:M5 switches the current through the PMOS diode-connected M1 (negative path) orM2 (positive path). PMOS transistor M2 is part of a filtering current mirror that supplies thebias current for the input differential pair of the double balanced mixer. The CS-DAC utilizesseparate 1.2V supplies for each path, where VDDI is the M1 supply for the negative path andthe main VDD is the M2 supply for the positive path. This is done to measure the time-varyingcomponent of the current window function in the fabricated prototype. The current dissipatedby a single unit current source is approximately 4µA, which results in a constant current of128µA dissipated through M2 with another 128µA switched between M1 and M2. The totalcurrent provided by the CS-DAC is 0.55mA to 1.1mA.

A lowpass filter is built into the current mirror to prevent aliasing and smooth the coarsetransitions of the CS-DAC [47], where the cut-off frequency is set based on the integrationperiod. A 4kΩ resistor and four parallel 1pF switched capacitors set the cutoff frequency, fc,such that fc ' 10 · fw, as per Table 3.3. A cutoff frequency 10 · fw provides smoothing whiledelaying the window function by Tw/28, where the delay of the ideal response is Tw/64. Theactual pole of the current mirror with the PMOS switches in cutoff is approximately 100MHzin simulations, which is 2.5 to 10 times the cutoff frequency.

3.2.4 Integrating Mixer Circuit Design

As illustrated in Figure 3.8, the proposed integrating mixer consists of a folded mixer withcapacitive loads that implements current-domain windowing in the first stage and downconver-sion mixing and integration in the second stage. The current window function is implementedwith the 5-bit thermometer coded CS-DAC of Section 3.2.3 while design parameters and val-ues are listed in Table 3.4. An active mixer is selected rather than a passive mixer in orderto provide sufficient gain in the absence of a LNA. A folded mixer is utilized to maximizethe transconductance of the input differential pair in the first stage while minimizing the bias


Figure 3.8: Integrating mixer schematic with optional bleeding current sources (IBL) and outputbuffer indicated with dashed-lines.


Table 3.4: Integrating mixer design parameters.

Integrating Mixer CS-DACParameter Value Parameter ValueM1,M2 50µm/120nm M1,M2 25µm/150nmM3,M4 40µm/150nm M3 118µm/150nmM5,M6,M7,M8 4µm/120nm M4,M5 300nm/180nmM9,M10 16µm/150nm M6 540nm/4.5µmM11,M12 2µm/150nm C 1pFM13,M14,M15,M16 21.6µm/250nm R 4kΩ

C 50pF VDD, VDDI 1.2Viw 0.55mA→ 1.1mAVDD 1.2V

current provided by the capacitive loads in the second stage.In the first stage, the current window function provides the tail current of the PMOS dif-

ferential pair (M3:M4). The corresponding values of gm3 and gm4 implement the windowmultiplication. The differential pair operates linearly over a differential swing of 800mV forthe RF signal with a common mode voltage of VCM = 325mV. The output currents are thenmirrored to the second stage with a gain of approximately 1/8. The second stage of the in-tegrating mixer consists of a mixing quad (M5:M8) with capacitive loads, which implementdownconversion mixing and integration.

In the reset mode, rs =‘0’ is applied and the PMOS transistors M1 and M2 are in deeptriode. This causes both terminals of the load capacitors to be at VDD, which discharge thecapacitors and resets the accumulated AC signal. NMOS switches, S1 and S2, disable thecurrent mirrors between the first and second mixer stages by pulling the gates of the NMOStransistors M11 and M12 to ground, which disables the LO downconversion operation in thesecond stage. This reduces the reset time of the load capacitors. The reset time constant, τreset ,can be obtained from the equivalent circuit illustrated in Figure 3.9 and is given by

τreset =

(RRS +

RSC

4

)CT (3.3)

where RRS is the on resistance of the PMOS transistors M1 and M2, RSC is the on resistance ofthe PMOS transistors that set the load capacitance, and CT = 4C is the total capacitance.

In the integration mode, rs =‘1’ is applied and the PMOS transistors M1 and M2 are incutoff. The capacitors supply bias current while simultaneously integrating the IF signal afterLO downconversion. NMOS switches, S1 and S2, enable the current mirrors between the firstand second mixer stages. The differential IF signal at the end of the integration period is themagnitude of the spectrum at the LO frequency while the DBW is set by the 3-dB BW of thewindow function. A buffered version of the IF signal is available off-chip through common-


Figure 3.9: Integrating mixer equivalent circuit for discharging capacitive loads during the resetmode.

Table 3.5: Integrating mixer modes

fw Integration Period Capacitive Load (Branch) Detection BW1MHz 1µs 200pF 0.98MHz

1.33MHz 0.75µs 150pF 1.3MHz2MHz 0.5µs 100pF 1.96MHz4MHz 0.25µs 50pF 3.92MHz

drain buffers (M13:M16), which allows debugging of the analog integrator waveforms. A biasvoltage of VOB = 300mV is applied to the common-drain buffers.

The implementation strategy for the integrating mixer can be divided into the individualdesign requirements of each stage. In the first stage, the transconductance of the input differen-tial pair should be maximized in order to maximize the sensitivity. This requires the first stageto dominate the current budget, consuming upwards of 90% of the current when including theCS-DAC. The first stage is sized based on the peak current provided by the CS-DAC and re-quires a trade-off between the transconductance and the input signal swing. A slightly longertransistor length than the process minimum was applied to reduce non-linearity. In the secondstage, the current is minimized to reduce the capacitor size and load. This current dependson the sizing of the first stage and the minimum transistor width. A first order approximationof the voltage drop across the capacitors is ∆VC = IC∆t/C. In order to achieve an integrationtime of 1µs and estimating a maximum current of IC = 62.5µA for each branch of the mixer,200pF loads are required for a voltage drop of 300mV. The capacitive loads are divided intofour 50pF parallel capacitors and PMOS switches are utilized to obtain four programmablewindow frequencies/integration times as per Table 3.5, where the capacitive load per branchand the corresponding DBW are indicated.

The optional bleeding current sources in Figure 3.8 provide a constant DC current, IBL,which reduces the current requirement of the load capacitors. The bleeding current sources areimplemented as PMOS transistors with a common gate voltage, VBL, which is set externally tofix the magnitude of the DC current such that IBL can be disabled by applying a bias voltage ofVBL = VDD. This reduces the size requirement of the capacitive loads in addition to reducing


the flicker noise contribution of the mixing quad (M5:M8). However, as a consequence of in-serting the bleeding current sources, some RF current flows into the bleeding circuit by currentdivision, thereby decreasing the conversion gain [48].

The total sensing time, tsense, for a specified frequency range, fend − fstart , and frequencystep, fstep, is given by

tsense =

(fend− fstart

fstep+1)× (Nave (Tw + treset)+ tsw) (3.4)

where Nave is the number of spectrum averages at a single LO frequency, Tw is the windowperiod, treset is the time to discharge the load capacitors during the reset period, and tsw isthe settling time of the LO signal. The maximum frequency step is fstep = DBW while theminimum value of treset can be estimated from the RC time constant in equation (3.3) for thereset mode. The value of tsw depends on the settling time of the applied LO signal.

In contrast to direct implementation of the STFT, the treset term in equation (3.4) increasesthe sensing time and should be minimized. In general, the overall sensing time should be min-imized to reduce the overhead associated with spectrum sensing and maximize the spectrumutilization.

3.2.5 Simulations

The integrating mixer is implemented in IBM’s CMRF8SF 0.13µm CMOS process with thedesign parameters in Table 3.4. Transient simulations are performed in Cadence Spectre cir-cuit simulator over process corners and temperature. The process corners are slow-slow (SS),typical-typical (TT) and fast-fast (FF) while the temperature ranges from 27C to 70C.

The time to reset the load capacitors prior to integration can be estimated by the capac-itor discharge voltage and the RC time constant of equation (3.3). In order to discharge thecapacitor voltage to 10% of the initial voltage, ∆Vc = 0.1, the reset time is given by

treset =−[(

RRS +RSC

4

)CT

]log(∆Vc) (3.5)

=−[(

90Ω+90Ω

4

)200pF

]log(0.1)

= 51.8ns

where RRS = 90Ω, RSC = 90Ω, and CT = 200pF. The simulated reset time is 32.6ns (corner:TT 27C), which is approximately 1/3 less than the 51.8ns estimated in equation (3.5).

In Figure 3.10, the integrator waveforms are illustrated for fw = 1MHz with different fre-


(a) fRF = 950MHz and fLO = 950MHz (b) fRF = 950MHz and fLO = 949MHz

(c) fRF = 950MHz and fLO = 948MHz (d) fRF = 950MHz and fLO = 947MHz

Figure 3.10: Integrating mixer integrator waveform simulation for fw = 1MHz and windowing.

Table 3.6: Integrating mixer corner simulation result summary.

Corner SS 27 SS 70 TT 27 TT 70 FF 27 FF 70BW (GHz) 1.47 1.2 2.36 2.19 3.97 3.67

1dB Comp (dBm) −0.5 −1.7 +2.4 +2.6 +2.8 +2.6

quency offsets (∆ f = fRF− fLO). The integrator is reset during the first 0.2µs which is followedby 1µs of signal integration. In Figure 3.10a, there is no frequency offset, ∆ f = 0, and a con-stant DC value is accumulated over the integration period. In the case of a frequency offset,∆ f 6= 0, the integrator waveform is sinusoidal with a frequency that corresponds to the offset,which is illustrated in Figures 3.10b−3.10d. The effect of windowing is visible with the shap-ing of the integrator waveforms, which in this case applies an elliptic curve to the waveforms.

The integrating mixer is simulated over process corners and temperature for a windowfrequency of 1MHz. In Figure 3.11, the BW is illustrated for an RF input of +2dBm. As listedin Table 3.6, the BW ranges from 1.2GHz to 3.97GHz. During the slow-slow corner, one of theinput pair transistors is in cutoff for an input of +2dBm, which causes the reduction in BW. InFigure 3.12, the linearity at 0.95GHz is illustrated for an RF input that ranges from −16dBmto +8dBm. The output power scales linearly with input power, with a 1dB compression pointthat ranges from−1.7dBm to +2.8dBm. The 1dB compression is at or above +2.4dBm for all


Frequency (GHz)

0.1 0.95 1.95 2.95 3.95

IF O

utp

ut

Am

plit

ud

e (

dB

V)

-28

-26

-24

-22

-20

-18

-16

-14

-12

SS 27oC

SS 70oC

TT 27oC

TT 70oC

FF 27oC

FF 70oC

Figure 3.11: Integrating mixer integration power over process corners for RF input of +2dBm.

Input RF Power (dBm)

-16.02 -10 -3.98 2.04 8.06

IF O

utp

ut

Am

plit

ud

e (

dB

V)

-38

-34

-30

-26

-22

-18

-14

-10 SS 27oC

SS 70oC

TT 27oC

TT 70oC

FF 27oC

FF 70oC

Figure 3.12: Integrating mixer integration linearity over process corners for fRF = fLO =0.95GHz.


Table 3.7: Integrating mixer power summary.

Supply Voltage Simulateda CircuitVDD 1.2V 1147µW Two-stage Mixer, CS-DAC (positive half)VDDI 1.2V 115µW CS-DAC (negative half)VDDD 1.2V 208µW Window generation logic

1470µWa Corner: TT 27C.

corners except slow-slow.Transient noise simulations for the integrator output is performed with no RF input signal at

the common mode voltage. The average output noise power is −114.7dBm/Hz over a 2.4GHzBW for the TT 27 corner, where the ENBW is 1.02MHz for fw = 1MHz. This is equivalentto an average RMS output voltage of 59µV.

In Table 3.7, the power breakdown is listed for a single integrating mixer. The total powerdissipation is 1470µW when a 50% duty cycle for rs applied. The digital component consist-ing of window generation and control logic, accounts for 14% of the total power dissipation.

3.2.6 Conclusion

The integrating mixer architecture implements the STFT-based energy detector for spectrumsensing. A folded double balanced mixer design is utilized to implement current-domain win-dowing in the first stage while downconversion mixing and integration is implemented in thesecond stage. Implementation of the window function in the current-domain reduces the num-ber of multiplication stages but also limits the selection of the window function, which causeshigher side-lobes with less roll off in the frequency domain. This restriction can be eliminatedby utilizing an array of folded mixers that are connected to common capacitive loads. Theintegration time is proportional to the size of the load capacitors. This results in a trade-offbetween the DBW and area since the 3-dB BW of the window function sets the DBW. If largercapacitors are utilized the DBW would improve while maintaining the same power dissipationat the cost of area. Flexible DBW is achieved with a bank of programmable load capacitors.

A prototype integrating mixer was designed in IBM’s CMRF8SF 0.13µm CMOS process.Simulations demonstrate a BW range from 1.2GHz to 3.97GHz over process corners and tem-perature with a 1dB compression point at or above +2.4dBm for all corners except slow-slow. The total power dissipation is 1470µW for a single integrating mixer, which increases to2617µW for a quadrature integrating mixer implementation.


Figure 3.13: Die microphotograph of integrating mixer prototype (C: capacitor, M: mixer, DIG:digital).

3.3 Integrating Mixer Implementation

The prototype integrating mixer described in Section 3.2 was implemented in IBM’s CMRF8SF0.13µm CMOS process with a 1.2V supply and low-Vt devices for analog components. Thecapacitive loads were implemented with metal-insulator-metal capacitors (MIMCAPs) whilethe digital window generation logic is isolated from the analog circuitry in a guard ring andlocated directly under the MIMCAPs. A die microphotograph is shown in Figure 3.13. Thesilicon area of the prototype is 0.18mm2, which, if not including MIMCAPs, is 0.06mm2. Theprototype die is packaged in a 44 pin quad-flat no-leads package (QFN) and mounted on acustom PCB.

Single-tone and two-tone tests over window frequencies were conducted to characterize theintegrating mixer prototype and examine its performance. Spectrum estimates, BW, dynamicrange (DR), 1dB compression, total harmonic distortion (THD), output third-order interceptpoints (OIP3) and power dissipation are presented. The test setup for the integrating mixerprototype is presented in Section 3.3.1. Integrator waveforms are discussed in Section 3.3.2while measurement results are presented in Section 3.3.3.


Prototype

FPGAEP4CE22

5V/2.5VTranslator

NI 6534 Interface(68-pin)Bias

Voltages

Regulators

Buffer ADC16-bit

JTAG(10 Pin)

Clock(SMA)

Power(2 BNCs)

Supply Voltages

RF Input(2 SMAs)

LO Input(2 SMAs)

Buffered IF Output(2 SMAs)

Reset & Digital Settings

Diff.

Diff.

Diff.

Diff.IF Output

Figure 3.14: Integrating mixer PCB block diagram.

Table 3.8: List of key components on the integrating mixer PCB.

Item Manufacturer Part Number DescriptionADC Analog Devices AD7626 10MSPS 16-bit SAR ADC

Analog Devices ADA4932 Differential ADC driverBuffer Analog Devices ADA4899 IF signal buffer

Bias Voltage Texas Instruments OPA350 Op amp (unity gain buffer)Texas Instruments TPS7912 1.2V LDO regulator

FPGA Altera EP4CE22E22 Cyclone IV

RegulatorsTexas Instruments TPS7912 1.2V LDO regulatorTexas Instruments TPS7925 2.5V LDO regulatorTexas Instruments TPS79650 5V LDO regulator

Translator Texas Instruments SN74LVCH16T245 2.5V to 5V translator

3.3.1 Test Setup

A 4-layer PCB was designed and fabricated as a testbed for the prototype. The PCB providessupply voltages, bias voltages, analog-to-digital conversion, memory and configures the proto-type. A block diagram of the PCB is illustrated in Figure 3.14 while the main components arelisted in Table 3.8. The differential IF analog output of the prototype is digitized with a 16-bitdifferential SAR ADC and stored in SRAM on the field-programmable gate array (FPGA). Anon-chip buffered version of the differential IF analog output is sent directly to a pair of SMAconnectors. The FPGA serves three main functions: (1) system control, synchronization, anddigital settings; (2) initialization of data conversion, data acquisition and storage in SRAM;and (3) communication between the PCB and Matlab on a host computer through the NationalInstruments 6534 data acquisition board (NI DAQ). The bias voltages are generated with a lownoise OP AMP in unity gain configuration with a potentiometer. A stacked capacitor with lowequivalent series resistance (ESR) and insertion loss ≥ 30dB over DC to 5GHz provides de-


Figure 3.15: Populated integrating mixer PCB photograpgh.

coupling over a wide bandwidth [49]. The fabricated PCB measures 122mm by 147mm andthe populated PCB is shown in Figure 3.15, where the design under test (DUT) is indicated.

External equipment is used to provide the RF signal, LO signal, clock signal, power andconfiguration data to the PCB as illustrated in Figure 3.16. The computer controls the exter-nal signal generators using GPIB, transmits configuration data and receives the digital outputstored on the FPGA from the prototype via the NI DAQ. The LO signal is provided by theRohde & Schwarz SMT 03, which allows the relative phase offset to be adjusted. When theLO signal generator is synchronized with the RF signal generator, the in-phase and quadraturecomponents can be captured using only a single integrating mixer by adjusting the phase offset90 in successive samples. The RF signal is provided by the Agilent E4422B signal generatorfor a single tone while for a two-tone signal, the Agilent 83712B signal generator is coupledwith the former through the passive coupler ZFRSC-42 from mini circuits. Krytar double ar-row 180 hybrid couplers are utilized for single-ended to differential conversion for the LOand RF signals. The clock signal is provided by the Agilent 83712B or Wavetech 395 signalgenerators. Lastly, the Tektronix TDS3052B oscilloscope is used to probe rs and differentialIF signals directly from the PCB.


AgilentE4422B

Agilent83712B

O180 HybridCoupler

O180 HybridCoupler

RF Input

LO Input

PCB withPrototype

Clock

Krytar

Krytar

++

AgilentE3631A

Computer(Matlab)

GPIBDC power

NI 6534Interface

Rhode & SchwarzSMT 03

fsync

Diff.

Diff.

Figure 3.16: Test setup for integrating mixer.

3.3.2 Integrator Waveforms

Integrator waveforms are illustrated in Figure 3.17, which demonstrate the operation of theintegrating mixer. In each screen capture, the top signal (channel 2) is the rs signal while thebottom signal (channel 1) is the differential IF signal from the on-chip output buffers, VIFB.The input RF signal in each case is a sinusoid at fRF = 3GHz.

In Figure 3.17a, there is no frequency offset and the DC value is clearly integrated over a1µs period when rs =‘1’, reaching a maximum value at the end of the period. The spectrummagnitude at the LO frequency is the difference between the final and initial value of the in-tegrator waveform (polarity is phase dependent). There is a sharp drop in the differential IFsignal when rs=‘0’ as the IF signal resets and the capacitors discharge. In Figure 3.17b, thereis a 2MHz offset as fLO = 2.998GHz and the signal across the integrator is sinusoidal, approx-imately spanning two periods. There are multiple peaks/valleys and the final integrator valueis no longer the maximum amplitude during the integration period. The non-linear shaping ofthe sinusoidal IF signal is in part due to the window function and a slight DC offset present. Inaddition, a small amount of the LO signal is integrated when rs=‘0’ due to some leakage be-tween the LO and IF ports during the reset mode. However, this does not affect the amplitudecalculation.

3.3.3 Measurement Results

The spectrum estimates in this section are computed with a single integrating mixer and arebased on the RMS value of the measured output samples, VRMS. The LO and RF inputs areunsynchronized and samples are computed with a random phase offset. For a sinusoidal input


Reset Integration

Spectrum Amplitude

(a) fRF − fLO = 0MHz.

Reset Integration

Spectrum Amplitude

(b) fRF − fLO = 2MHz.

Figure 3.17: Integrator waveforms (channel 1: VIF , channel 2: rs).


Frequency (GHz)

0.495 0.4975 0.5 0.5025 0.505

Po

we

r (d

Bm

)

-25

-20

-15

-10

-5

0

5

Figure 3.18: Integrating Mixer: spectrum estimates for a tone at 0.5GHz with +2dBm of powerand fw = 1MHz.

tone, the magnitude of the power spectrum at the LO frequency is defined as

|Sxx ( fLO)|= 2√

2 ·VRMS ( fLO) , (3.6)

where a full derivation of equation (3.6) is given in Appendix A.The measured power spectrum of a tone at 0.5GHz with an input power of +2dBm is

illustrated in Figure 3.18. The spectrum overlays 10 spectrum estimates with fw = 1MHz andthe LO frequency swept over 0.5MHz intervals, which shows spreading of the input signal.The side-lobe oscillations are suppressed in excess of 18dB and the DBW is approximately1MHz. In Figure 3.19, measured spectrum estimates are illustrated for all values of the windowfrequency for a tone at 2.99GHz with an input power of +2dBm and the LO frequency is sweptover 1MHz intervals. As expected, side-lobe oscillations are largest for fw = 4MHz.

The DR is calculated directly from the power spectrum estimate and is the difference indecibels between the maximum input signal and the noise floor. The DR is measured in 0.1GHzintervals over an LO frequency range 0.5GHz to 3GHz for an input tone with +2dBm of power.In Figure 3.20 the DR is illustrated for window frequencies fw = 1MHz and fw = 2MHz with


Frequency (GHz)

2.982 2.984 2.986 2.988 2.99 2.992 2.994 2.996 2.998

Po

we

r (d

Bm

)

-25

-20

-15

-10

-5

0

5

fw

=1MHz

fw

=1.33MHz

fw

=2MHz

fw

=4MHz

Figure 3.19: Integrating mixer: spectrum estimates for a tone at 2.99GHz with +2dBm ofpower and fw = 1MHz, fw = 1.33MHz, fw = 2MHz, and fw = 4MHz.

Table 3.9: Integrating mixer: measurement result summary.

fw DBW DRave BW Integration Gain 1dB Compression1MHz 0.98MHz 25.0dB 2.15GHz −12.2dB +1.0dBm

1.33MHz 1.3MHz 24.6dB 2.20GHz −10.1dB −1.0dBm2MHz 1.96MHz 25.2dB 2.20GHz −16.1dB +1.5dBm4MHz 3.92MHz 22.0dB 2.20GHz −17.3dB +2.0dBm

linear regression applied for the line of best fit. For fw = 1MHz, the BW is 2.15GHz and theaverage DR is 25dB while for fw = 2MHz, the BW is 2.2GHz and the average DR is 25.2dB.The results for fw = 1.33MHz and fw = 4MHz are listed in Table 3.9 and illustrated in FigureB.1 of Appendix B.

There is a constant integration gain associated with each window frequency, which is pro-portional to DC voltage drop across the capacitive loads. In Figure 3.21, the 1dB compressioncurves are illustrated for fw = 1MHz and fw = 2MHz. The 1dB compression points are +1dBmfor fw = 1MHz with an integration gain of −12.2dB and +1.5dBm for fw = 2MHz with anintegration gain of−16.1dB. The results for fw = 1.33MHz and fw = 4MHz are listed in Table3.9 and illustrated in Figure B.2 of Appendix B. The THD for a tone at 0.5GHz with an input


Frequency (GHz)

0.5 1 1.5 2 2.5 3

DR

(dB

)

19

21

23

25

27

DRave

=25.0dB

BW=2.15GHz

fw

=1MHz

(a) fw = 1MHz

Frequency (GHz)

0.5 1 1.5 2 2.5 3

DR

(d

B)

20

22

24

26

28

DRave

=25.2dB

BW=2.2GHz

fw

=2MHz

(b) fw = 2MHz

Figure 3.20: Integrating mixer: dynamic range over 0.5GHz to 3GHz with line of best fit forfw = 1MHz and fw = 2MHz.


Input Power (dBm)

-12 -10 -8 -6 -4 -2 0 2

Outp

ut P

ow

er

(dB

V)

-25

-23

-21

-19

-17

-15

-13

-111dB Comp=+1.0dBm

fw

=1MHz

(a) fw = 1MHz

Input Power (dBm)

-12 -10 -8 -6 -4 -2 0 2

Outp

ut P

ow

er

(dB

V)

-29

-27

-25

-23

-21

-19

-17

-15

-13

1dB Comp=+1.5dBm

fw

=2MHz

(b) fw = 2MHz

Figure 3.21: Integrating mixer: 1dB compression for fw = 1MHz and fw = 2MHz.


Table 3.10: Integrating mixer: power summary.

Supply Voltage Measured Simulateda CircuitVDD 1.2V 1185µW 1147µW Two-stage Mixer, CS-DAC (positive half)VDDI 1.2V 130µW 115µW CS-DAC (negative half)VDDD 1.2V 234µW 208µW Window generation logic

1549µW 1470µWa Corner: TT 27.

power of −3dBm is 3.9%.Two-tone testing is applied across the full bandwidth in order to measure the IMD prod-

ucts and compute the OIP3. For +2dBm input tones at 1GHz and 1.5GHz, IMD products of−15.6dBm and −17.1dBm are measured at 0.5GHz and 2GHz, respectively. This results in aOIP3 of +11.2dBm.

The overall performance of the integrating mixer prototype is summarized in Table 3.9,which lists the DR, integration gain, and 1dB compression point for each window frequency.The total power dissipation is 1549µW with a full breakdown listed in Table 3.10. The mea-sured power dissipation is within 6% of the simulated.

3.3.4 Conclusion

A prototype of the integrating mixer was implemented in IBM’s CMRF8SF 0.13µm CMOSprocess, fabricated, packaged, and mounted on a custom PCB for laboratory testing. Theintegrating mixer prototype achieves an average DR of 24.2dB and a BW of 2.2GHz over thefour window frequencies. The BW is slightly lower than the simulated value of 2.4GHz for thetypical-typical corners and the measured power dissipation is within 6% of the simulated valueas shown in Table 3.10. The 1dB compression point is slightly lower than the simulated valueof +2.4dBm to +2.6dBm for the typical-typical corners with fw = 1MHz.

3.4 Comparisons

In Table 3.11, the integrating mixer prototype is compared to recent mixed-signal spectrumsensing implementations that are based on energy detection [15] [16] [17] [50]. The STFT isimplemented in [15] and [16], while a RSSI circuit is implemented in [17]. The RSSI energydetector utilizes limiting amplifiers, programmable current mirrors, and a LPF to realize arectifier-based energy detector with variable sensitivity. A wideband spectrum sensing solutionis proposed in [50], which implements a wavelet-based energy detector with edge detection forUWB signals and is the only implementation that does not target IEEE 802.22 WRAN.


Table 3.11: Comparison of mixed-signal spectrum sensing implementations based on energydetection.

[15] [16] [17] [50] Integrating Mixer(1st Prototype)

Technology 0.18µm 0.18µm 90nm 65nm 0.13µmSupply (V) 1.8 1.8 1.2 1.0 1.2P (mW) 43.2a 23.8a 13.9b 26.4−47.9c 2.6d

DR (dB) 32 24 29−48 35 22−25.2Range (GHz) 0.4−0.9 0.4−0.9 0.03−2.4 3.1−10.6 0.05−2.2Window or Wavelet cos4 x cos4 x n/a Triangular Hann (α = 0.85)fw (MHz) 0.025−1 0.025−1 n/a 66−132 1−4DBW (MHz) 0.05−2 0.05−2 0.2−30 n/a 0.98−3.92RX Sensitivity (dBm) −74 −72.5 −83 −75 n/aDR/P (dB/mW) 0.7 1.0 2.1−3.4 0.7−1.3c 8.5−9.7a Power for analog correlator and digital window generation.b Power for mixer, BB filter and RSSI circuitry.c Power for LNA, QPLL, correlator, and wavelet generator over LO frequency range.d Estimated power for a dual mixer based on single mixer.

The integrating mixer prototype achieves greater than 5× reduction in power consumptionand an average DR of 24.2dB, which is slightly above the average DR of [16]. This leads to thehighest DR/P value of 8.5− 9.7dB/mW, where DR/P is used to measure the implementationefficiency. The higher the value of DR/P, the less power required per 1-dB of DR. The RSSIdesign in [17] obtains the second largest frequency range and the largest DR at 48dB, how-ever, the high DR is only achieved in the wide-DR mode which covers input powers between−30dBm to +18dBm where the overall gain is dependent on the mode of the RSSI detector.The wavelet-based implementation of [50] achieves the widest BW and the second largest DRbut has a much wider DBW (on the order of wavelet frequency) and does not operate below3.1GHz. The higher power consumption of the STFT implementations in [15] and [16] are inpart due to direct realization of the STFT (with two double balanced mixers and an integrator)and the high resolution DAC utilized for the digital window generation.

The comparison works included here are complete receiver designs with LNA and gainstages prior to the spectrum sensing implementation. The receiver with the minimum sensitiv-ity is [17], which obtains a sensitivity of −83dBm after 67dB of gain in the analog front end.The sensitivity of [15], [16] and [50], are −74dBm, −72.5dBm, and −75dBm, respectively.The average noise floor for the integrating mixer prototype is−22.1dBm. In order to match thesensitivity of−83dBm obtained by [17], the proposed design would require an analog front endwith a LNA and gain stages that provide 60.1dB, which is less gain than that required by [17].

The DR of the proposed design, 24.2dB, is a trade-off with the resultant low power dissi-pation of 2.6mW. However, even at 24.2dB the DR matches or is within range of recent imple-


mentations while achieving the lowest power dissipation. The DBW of the proposed design,which ranges from 0.98MHz to 3.92MHz, is limited by the integrating capacitor size. If largercapacitors were utilized the DBW would improve while maintaining the same power dissipa-tion at the cost of area. With the trend of increasing BW and the need for fast and low-powersolutions, even a minimum DBW of 0.98MHz may be an acceptable design trade-off.

3.5 Conclusion

This chapter introduced the integrating mixer architecture that implements the STFT-basedenergy detector for spectrum sensing. The architecture utilizes a folded double balanced mixerdesign to implement current-domain windowing in the first stage while downconversion mixingand integration is implemented in the second stage. Flexible DBW is achieved with a bank ofprogrammable load capacitors.

A prototype of the integrating mixer was implemented in IBM’s CMRF8SF 0.13µm CMOSprocess, fabricated, packaged, and mounted on a custom PCB for laboratory testing. The inte-grating mixer prototype achieves an average DR of 24.2dB and a BW of 2.2GHz across fourwindow frequencies, which range from 1MHz to 4MHz. This corresponds to a DBW rangefrom 0.98MHz to 3.92MHz, respectively. The design achieves an OIP3 of +11.2dBm with1dB compression that ranges from −1dBm to +2dBm across window frequencies. The totalpower dissipation for a single integrating mixer is 1549µW, which increases to approximately2604µW for a quadrature implementation. One full sweep over the entire 808MHz DTV fre-quency range with dual integrating mixers takes 1.7ms with fw = 1MHz and a rs signal with50% duty ratio, which is well under the < 2s sensing limit for IEEE 802.22 WRAN. That timedrops to 0.1ms with fw = 4MHz. Note that while a 50% duty ratio was utilized for testing, amuch higher duty ratio (e.g. 90%) can be applied since the required reset time is much lowerthan the integration time. This reduces the sweep time by nearly a factor of two.

In comparison to recent mixed-signal spectrum sensing implementations, the integratingmixer prototype achieves greater than 5× reduction in power consumption while achieving anaverage DR that falls within the reported range. The design incorporates mixing and basebandfiltering which further reduces the overall power consumption beyond the spectrum sensingcomponent when implemented within a full receiver2.

The integrating mixer architecture is well suited for integration within low power cogni-tive radio transceivers that target portable IEEE 802.22 WRAN applications. The integratingmixer prototype can be utilized with cooperative spectrum sensing or as the first in a dual-stage sensing process to quickly identify potential vacant spectrum for detailed sensing with

2During spectrum sensing operation.


cyclostationary feature detection and exceeds the BW requirements of IEEE 802.22 WRAN.

Chapter 4

Integrating Mixer SAR Architecture

4.1 Introduction

This chapter presents the circuit design, analysis and experimental results for the integratingmixer SAR and its main components. The integrating mixer SAR is implemented in IBM’sCMRF8SF 0.13µm CMOS process and targets integration within portable cognitive radiotransceivers for IEEE 802.22 WRAN applications such as public safety networks. Simulationsare performed using Cadence Spectre circuit simulator while experimental results are presentedfor a prototype that is fabricated, packaged and mounted on a custom PCB. Section 4.2 presentsthe design and analysis of the integrating mixer SAR including the incorporation of a binary-weighted SAR ADC within the integrating mixer architecture, analysis and implementation ofthe Hann window function, circuit design and simulations. Section 4.3 presents the method andexperimental results for the prototype integrating mixer SAR for single-tone and two-tone testsover window and sampling frequencies. In section 4.4, the prototype is compared to recentspectrum sensing implementations and the integrating mixer prototype from Chapter 3. Lastly,conclusions are stated in Section 4.5.

4.2 Integrating Mixer SAR Design and Analysis

The integrating mixer SAR implements the STFT in the analog domain and digitizes its ampli-tude at the end of the integration period. The architecture can be used to realize a STFT-basedenergy detector and is an extension of the integrating mixer proposed in Chapter 3. Here anarray of mixers are connected to a common subset of binary-weighted capacitive loads, whichintegrate the IF signal and act as the sampling capacitors for an integrated SAR ADC. Thewindow function is once again implemented in the current-domain, however, the array struc-

49

CHAPTER 4. INTEGRATING MIXER SAR ARCHITECTURE 50

Figure 4.1: Block diagram of the integrating mixer SAR illustrated for a single path of anSTFT-based spectral estimate (B2T: binary to thermometer encoder).

ture removes current restrictions on the selection of the window function. This improves theside-lobe reduction and fall off in the frequency domain. The integrating mixer SAR oper-ates in three modes: a reset mode where both terminals of the load capacitors are connectedto VDD, resetting the accumulated signal and discharging the capacitors; an integration/sam-ple mode where the capacitive loads provide bias current while integrating and sampling theIF signal; and a conversion mode where charge redistribution is applied to the sampled STFTsignal across the binary-weighted load capacitors of the SAR ADC.

A system block diagram of the integrating mixer SAR is illustrated in Figure 4.1, wherethe digital input signals rs, clk win, clk sar and en sar control system operation. Theinput rs selects the mode of operation where rs =‘0’ and rs =‘1’ correspond to reset andintegration modes, respectively. The window function is generated by a 5-bit parallel binarycounter that cycles through the binary coefficients stored in a LUT each integration period ata frequency set by clk win. A binary to thermometer encoder with registered output drivesa distributed 5-bit thermometer coded CS-DAC that implements the window function in thecurrent-domain and is mirrored to the integrating mixer SAR. The en sar signal triggers a


CN-1

CN-1

VREF

C0

C0

C0

C0

+

VCM

CN-2

CN-2

C1

C1

VX+

VIN-

VREF

VIN+

VCM

VX-

SAR ControlLogic

OutputCode

Figure 4.2: N-bit differential SAR architecture with bit cycling for bit bN−1.

SAR conversion at a frequency set by clk sar and cannot switch modes until the conversionprocess is complete. The LO signal is supplied off chip.

The design and analysis of the integrating mixer SAR is divided into the following sec-tions; the differential SAR architecture is modified in Section 4.2.1 for incorporation withinthe integrating mixer. The window function and its implementation is discussed in Section4.2.2. Analysis and design of the two-stage integrating mixer SAR is presented in Section4.2.3 while simulations are provided in Section 4.2.4.

4.2.1 Binary-Weighted SAR ADC

The integrating mixer utilizes programmable capacitor banks in a double balanced mixer topol-ogy, which integrates and samples the IF signal over a period set by the load capacitance. Thesampling operation performed by the load capacitor array makes it possible to incorporate aSAR ADC within the integrating mixer architecture. This is accomplished by re-sizing a subsetof the capacitors in the capacitor load array of the integrating mixer and modifying the commonmode voltage of the conventional SAR process in order to re-utilize the capacitor load arrayfor charge redistribution.

The architecture of an N-bit differential binary-weighted SAR ADC is illustrated in Fig-ure 4.2, where CN−1 = 2N−1CU and CU is a unit capacitor. There are three modes of operation:sample, hold, and cycle. In the sample mode, the capacitors of the plus-branch and minus-branch are switched to the input signals VIN+ and VIN−, respectively, such that charges of−2NCUVIN+ and −2NCUVIN− are stored in each branch, while VCM is connected to each com-mon bus such that VX+ =VCM and VX− =VCM. In the hold mode, the capacitors are switched


to 0V and VCM is disconnected such that VX+ =VCM−VIN+ and VX− =VCM−VIN− as thecharges stored in the sampling mode are redistributed. In the cycle mode, charge redistribu-tion is applied to evaluate a series of N comparisons, determining an N-bit conversion startingwith the MSB and ending with the LSB. In the first comparison, CN−1 is switched to VREF

and CN−2 → C0 are switched to 0V in the plus-branch while CN−1 is switched to 0V andCN−2→C0 are switched to VREF in the minus-branch. The capacitance forms a 1 : 1 divider ineach branch such that VX+ =VCM−VIN++1/2VREF and VX−=VCM−VIN−+1/2VREF . There-fore, if VX+ < VX− bit bN−1 =‘1’ and the switches are fixed for CN−1, otherwise bN−1 =‘0’and the switches are reversed. In general for the k-th bit under test, Ck is switched to VREF andCk−1→C0 are switched to 0V in the plus-branch while Ck is switched to 0V and Ck−1→C0

are switched to VREF in the minus-branch. If VX+ < VX− bit bk =‘1’ and the switches for Ck

are fixed, otherwise Ck is switched to 0V in the plus-branch while Ck is switched to VREF in theminus-branch and bk =‘0’.

In order to incorporate a SAR ADC in the integrating mixer architecture, the load capaci-tors are binary-weighted while VX+ and VX− in the SAR architecture of Figure 4.2 share theirrespective buses with the supply voltage, VDD. A switch is added to each bus to disconnect VDD

during a conversion, however, utilization of common buses restricts the selection of the com-mon mode voltage to VCM =VDD, instead of the typical selection of VCM =VDD/2. This raisesthe maximum voltage on the VX+ and VX− buses during charge redistribution to 1.75 ·VDD

rather than 1.25 ·VDD (if VCM =VDD/2), which can lead to gate failure in the absence of thickoxide devices or bootstrapping. The switch arrays applied to the capacitors of the plus- andminus-branches allow operation in a combined integration/sample mode and distinct reset andconversion modes.

The SAR conversion rate within the integrating mixer architecture is limited by capacitorpre-charge in the sample mode, charge redistribution in the conversion mode1, and capacitordischarge in the reset mode. In Figure 4.3, the equivalent circuits2 are illustrated for eachoperating mode. As in [51], the switch resistance is assumed to be binary scaled for circuitsimplification and the RC time constants for the sample mode, τsamp, conversion mode, τconv,

1Equivalent to the cycle mode for a conventional SAR ADC.2Equivalent circuits are shown for a single branch of the differential architecture.


(a) Equivalent circuit for sample mode pre-charge (τsamp calculation).

(b) Equivalent circuit for charge redistribution (τconv calculation).

(c) Equivalent circuit for capacitor discharge (τreset calculation).

Figure 4.3: Equivalent circuits for binary-weighted SAR operating modes including capacitordischarging for application in the integrating mixer architecture.


and reset mode, τreset , are given by

τsamp =

(RS +

RSC

2N +RCM

)CT (4.1)

τconv =RSC

2N CT (4.2)

τreset =

(RRS +

RSC

2N +RCM

)CT (4.3)

where RS is the source resistance, RSC is the on resistance of the PMOS transistors that set theload capacitance, RCM is the common mode resistance, RRS is the on resistance of the PMOStransistors3 that reset the load capacitors during the reset mode, and CT = 2NCU is the totalcapacitance. The time constant for the reset mode in equation (4.3) differs from that given inequation (3.3) for the integrating mixer in Chapter 3 since the latter did not apply binary scaledswitches and the supply voltage is not switched.

The SAR logic is implemented using a similar approach as [52], with a combined sequencerand code register that switch the binary-weighted capacitors during charge redistribution andincrementally store the bit comparison result in a code register. An 11-bit differential sequenceris illustrated Figure 4.4, which is realized with a shift register and set/clear D flip-flops (DFF)with complementary outputs. The even numbered DFFs in the sequencer correspond to con-secutive binary weights in decreasing order while the odd numbered DFFs add a clock delayto allow the comparator to settle prior to sampling the bit. The q and q outputs of the coderegister correspond to the minus and plus weights of the differential architecture, respectively,since a PMOS transistor is used to switch logic-‘1’ while an NMOS transistor is used to switchlogic-‘0’. A SAR process is triggered when en sar =‘1’, which causes the first DFF in thesequencer to be set (q =‘1’) while the remaining DFFs are cleared (q =‘0’). The sequencerpropagates the set-state at the clk sar frequency and concludes once the final DFF is set. Asillustrated in Figure 4.5, a bit comparison is a three step process: (1) the sequencer sets thecorresponding DFF in the code register, setting S+ and S− for charge redistribution; (2) thecomparator is triggered by en cycle during the next clock cycle; (3) and finally, the next bitcomparison samples the current bit value and sets b(n) during the third clock cycle.

4.2.2 Window Function and Digital Generation

A number of functions can be selected to implement the time-domain windowing operation,including the functions listed in Table 2.1 of Section 2.4. The Hann function is chosen to time-limit the STFT and provide low pass filtering since it achieves a favorable balance between

3Corresponds to transistors M3 and M4 in Figure 4.7


done

‘0’

‘0’

‘0’

‘1’ ‘1’ ‘1’

‘1’ ‘1’ ‘1’ ‘1’

‘1’

comp_val

clk_sar

rs_sys

en_sar

SE

QU

EN

CE

RC

OD

E R

EG

IST

ER

d

clk

clr

set

q

q

d

clk

clr

set

q

q

d

clk

clr

set

q

q

d

clk

clr

set

q

q

d

clk

clr

set

q

q

d

clk

clr

set

q

q

d

clk

clr

set

q

q

d

clk

clr

set

q

q

d

clk

clr

set

q

q

d

clk

clr

set

q

q

d

clk

clr

set

q

q

d

clk

clr

set

q

q

S (10)+ S (10)- S (9)+ S (9)-

S (0)+ S (0)-

Figure 4.4: SAR control logic: differential sequencer and code register.


Figure 4.5: Integrating mixer SAR control and output waveforms.


Frequency (Fs/N)

-6 -4 -2 0 2 4 6

No

rma

lize

d A

mp

litu

de

(d

B)

-60

-50

-40

-30

-20

-10

0

α=0.5

α=0.85

Figure 4.6: Frequency domain response of the window function for α = 0.5 and α = 0.85.

side-lobe reduction, roll off and 3-dB BW. The continuous time version of the Hann windowfunction is defined as

w(t,τ) =

0.5+0.5 · cos(2π fwt) if |t| ≤ τ/20 otherwise (4.4)

which is equivalent to α = 0.5 substituted in equation (3.1).As for the integrating mixer in Chapter 3, the window function is implemented in the

current-domain with 5-bit quantization. The integrating mixer SAR utilizes an array of 16folded mixer cells with a 3-level CS-DAC, which realize a distributed 5-bit thermometer codedCS-DAC. The current window function is generated by switching individual cells on/off in athermometer sequence, where the sum of the currents is the value of the window function.This removes the minimum current restriction on the selection of the window function, whichimproves the achievable side-lobe reduction and fall off. In Figure 4.6, the frequency domainresponse of the Hann window function (α = 0.5) is compared to the transconductance windowfunction (α = 0.85) implemented for the integrating mixer in Chapter 3. The initial side-lobe is−32dBc with a −18dB/octave fall off for α = 0.5 while the initial side-lobe is only −16.8dBcwith a −6.3dB/octave fall off for α = 0.85. One disadvantage for α = 0.5 is the greater 3-dB


BW of the window function, which increases the DBW.The digital window coefficients are generated using the scheme discussed in Section 3.2.2

with clk→ clk win. The window function is sampled 32 times to reduce the hardware com-plexity such that fclk win = 32 · fw. The window function coefficients for each integration periodare generated by a 5-bit counter that cycles through the coefficients stored in a 5x32 LUT. Here,5-bit quantization is selected since it minimizes the complexity while only incurring a 0.9dBpenalty on the initial side-lobe with a −11.1dB/octave roll off. The LUT is implemented withfive 32x1 multiplexers, where each MUX implements one bit of the 5-bit window function co-efficient over the 32 samples of the integration period. A binary to thermometer encoder mapsthe 5-bit binary input to 31 thermometer outputs that drive the distributed 5-bit CS-DAC. A31-bit register is inserted after the binary to thermometer encoder in order to prevent glitchesand is sampled on the falling clock edge.

The main control signals are rs and en sar. The reset and integration modes correspondto rs =‘0’ and rs =‘1’, respectively, and remain valid until en sar =‘1’ triggers a SARconversion. The signal rs is synchronized with the input signal clk win such that the in-tegration time is exactly 32 ·Tclk win while the reset time is m ·Tclk win, where m is an integerchosen to allow sufficient time for the load capacitors of the integrating mixer to reset and aSAR conversion to complete. As illustrated in Figure 4.5, the signal en sar is synchronizedjust prior to the end of the integration period. During a SAR conversion, the signal rs int

prevents accidental reset of the capacitors during a conversion while the signal en int dis-connects the supply voltage. The signals S1 and S2 are applied to the gates of a pair of NMOSswitches that either enable or disable the current mirrors between mixer stages based on themode of operation.

4.2.3 Integrating Mixer SAR Circuit Design

As illustrated in Figure 4.7, the proposed integrating mixer SAR consists of a folded mixerarray that is connected to binary-weighted load capacitors that form the sampling capacitors ofan N-bit differential SAR ADC. The first stage of the mixer implements current domain win-dowing while the second stage implements downconversion mixing, integration and chargeredistribution. The design parameters and values are listed Table 4.1. The current windowfunction implements a 5-bit quantized version of the Hann window in equation (4.4) and uti-lizes the digital control scheme discussed in Section 4.2.2. The binary-weighted capacitorsare implemented with a unit capacitance of CU = 62.5fF such that Ck = 2k ·CU . In addition,a programmable load capacitor, CL, sets the integration time and realizes the four integrationmodes listed in Table 4.2.


Figure 4.7: Integrating mixer SAR schematic with control signals rs int and en int.


Table 4.1: Integrating mixer SAR design parameters.

Integrating Mixer ComparatorPart Value Part ValueM1,M2,M3,M4 27µm/120nm M1,M2,M3,M4,M5 1.08µm/180nmM5,M6 940nm/120nm M6,M7,M8,M9 2.16µm/180nmM7,M8,M9,M10 280nm/160nm M10,M11 4.32µm/180nmM11,M12 480nm/180nm M12 7.56µm/120nmM13,M14 160nm/180nm VDD 1.2Viw [0,11.5µA,23µA]CU 62.5fFVDD 1.2VVDDA 1.1VN 11

Table 4.2: Integrating mixer SAR modes

fw Integration Period CL (Branch) CTOTAL (Branch) Detection BW250kHz 4.0µs 384pF 512pF 360kHz333kHz 3.0µs 256pF 384pF 480kHz500kHz 2.0µs 128pF 256pF 720kHz1MHz 1.0µs − 128pF 1.44MHz

The array consists of 16 folded mixers with 3-level CS-DACs that are driven by a DWG,which turns on/off individual cells to implement the window function. The mixer array re-moves current restrictions on the window function while the 3-level CS-DAC array realizesa distributed 5-bit thermometer coded CS-DAC. The supply voltage, VDDA, is connected tothe VOUT+ and VOUT− buses through the PMOS transistors M1 and M2 using control signalen int, which is enabled during the integration/sample and reset modes. These commonbuses are the inputs to a comparator that is clocked during charge redistribution in the con-version mode. PMOS transistors M3 and M4 are utilized to reset the capacitive loads andare controlled by the signal rs int, which is enabled only when rs =‘0’ and conv =‘0’ toprevent accidental resetting of the capacitors during a conversion.

The mixer array cells utilize a folded architecture to maximize the transconductance of theinput differential pair in the first stage while minimizing the current provided by the capacitiveloads in the second stage. In the first stage, the current from the 3-level CS-DAC is mirrored tothe PMOS differential pair (M5:M6). The transconductance values gm5 and gm6 implement thewindow multiplication. The input differential pair operates linearly over a differential swingof 600mV with a common-mode voltage of 475mV. The output currents are mirrored to thesecond stage with a gain of approximately 1/3. The second stage consists of a mixing quad(M7:M10) that connects to the load capacitors through switching arrays that toggle betweenVIF+/−, VREF and 0V based on the operating mode. The mixing quad has a common-modevoltage of 1V and the LO has a voltage swing of 400mV.


In the reset mode, the signals en int =‘0’ and rs int =‘0’ while the capacitor arraysare switched to the VIF+/− signals. The PMOS transistors M1:M4 are in deep triode suchthat VDDA is applied to both the VOUT+/− buses and the VIF+/− outputs. This causes the loadcapacitors to discharge and resets the accumulated IF signal. NMOS switches, S1 and S2,disable the current mirrors between the first and second mixer stages by pulling the gates ofNMOS transistors M13 and M14 to ground, which disables the LO downconversion operationin the second stage. This reduces the reset time of the load capacitors.

In the integration/sample mode, rs int=‘1’ and en int=‘0’ while the capacitor arraysare switched to the VIF+/− signals. The PMOS transistors M1:M2 are in deep triode such thatVDDA is applied to VOUT+/− while M3:M4 are in cutoff. The capacitors supply bias currentwhile simultaneously integrating the IF signal after LO downconversion. NMOS switches, S1

and S2, enable the current mirrors between the first and second mixer stages. The differential IFsignal at the end of the integration period is the magnitude of the spectrum at the LO frequencywhile the DBW is set by the 3-dB BW of the window function.

In the conversion mode, the internal signal conv=‘1’ after a SAR conversion is triggered,which causes the signals en int =‘1’ and rs int =‘1’. Consequently, the PMOS transis-tors M1:M4 are in cutoff disconnecting VDDA from VOUT+/−. In addition, PMOS switchesare used to disconnect CL from VOUT+/− to isolate the binary-weighted capacitors. Chargeredistribution is applied iteratively to digitize the sampled IF signal.

The comparator input voltage fluctuates due to charge redistribution during the SAR pro-cess. The maximum voltage that occurs on VOUT+/− occurs during comparison with 3/4VREF

such that VOUT+/−(max) = VDDA−VIF+/−+ 3/4VREF . This causes a potential voltage limi-tation in the absence of thick oxide devices. In the target IBM CMRF8SF process, standarddevices are limited to a maximum of 1.6V while the standard supply is 1.2V. The integrat-ing mixer SAR is designed to operate with a maximum voltage drop of 0.6V across the out-put VIF+/− voltage, which results in a maximum voltage of VOUT+/− = 1.425V. In orderto reduce the maximum voltage, a supply of VDDA = 1.1V is utilized and a saturation circuitdisables integration once a drop of 0.6V is detected, which limits the maximum voltage toVOUT+/− = 1.325V. In Figure 4.8, the range of comparator input voltages, VIN+/−, are illus-trated over the iterations of a SAR conversion for N = 11.

The Schinkel double-tail voltage sense amplifier is selected to implement the comparatorsince it simultaneously achieves fast latching and low offset by maximizing current in thelatching stage and minimizing current in the input stage, respectively [53]. A schematic of thedouble-tail voltage sense amplifier is illustrated in Figure 4.9, where design parameters andvalues are listed in Table 4.1. Initially, en =‘0’ and the NMOS transistors M6 and M9 pullVOUT+/− to 0V since the VDI+/− lines are pre-charged to VDD by the PMOS transistors M4


Iteration

1 2 3 4 5 6 7 8 9 10 11

Vo

lta

ge

(V

)

0.2

0.4

0.6

0.8

1

1.2

1.4

Figure 4.8: Comparator input voltage versus SAR iteration.

and M5. When en =‘1’, an input dependent voltage builds up, ∆VDI , until NMOS transistorsM6 and M9 cause one of the cross-coupled inverters to be clamped to 0V setting VOUT+/−.The SR latch is implemented with cross coupled nand gates such that S and R are enabled withlogic-‘0’, while the comparator outputs are reset to a logic-‘1’.

The total sensing time, tsense, for a specified frequency range, fend − fstart , and frequencystep, fstep, is given by

tsense =

(fend− fstart

fstep+1)× (Nave (Tw + treset + tconv)+ tsw) (4.5)

where Nave is the number of spectrum averages at a single LO frequency, Tw is the windowperiod, treset is the time to discharge the load capacitors during the reset period, tconv is theconversion time, and tsw is the settling time of the LO signal. The maximum frequency step isfstep = DBW while the minimum value of treset can be estimated from the RC time constant inequation (4.3) for the reset mode. Similarly, the minimum value of tconv can be estimated fromthe RC time constants in equations (4.1) to (4.2). The value of tsw depends on the settling timeof the applied LO signal.

In contrast to direct implementation of the STFT, the treset and tconv terms in equation (3.4)


VDD

en

en

VIN+ VIN-

VDD

en

VOUT- VOUT+

R

S Q

Q

VOUT+

VOUT-

comp_val

M2 M3

M1

M4 M5

M6

M11M10

M12

M7 M8 M9

VDI- VDI+

Figure 4.9: Double-tail voltage sense amplifier with SR latch, used as the SAR ADC compara-tor.


Time (1/fw

)

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

No

rma

lize

d A

mp

litu

de

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

gm,total

α=0.5

Figure 4.10: Normalized total transconductance window function and corresponding α-value.

increase the sensing time and should be minimized. In general, the overall sensing time shouldbe minimized to reduce the overhead associated with spectrum sensing and maximize the spec-trum utilization.

4.2.4 Simulations

The integrating mixer SAR is implemented in IBM’s CMRF8SF 0.13µm CMOS process withthe design parameters listed in Table 4.1. Transient simulations are performed in CadenceSpectre circuit simulator over process corners and temperature. The corners range from slow-slow (SS) to typical-typical (TT) while the temperatures range from 27C to 70C.

The window function is implemented as the sum of the input pair transconductance fromthe mixer array. In Figure 4.10, the simulated value (corner: SS 27C) of the normalizedtotal transconductance window function is compared to the Hann window function (α = 0.5),which is given by equation (4.4). The total transconductance, gm,total , closely follows the Hannwindow function.

The time to reset the binary-weighted capacitors prior to integration can be estimated by thecapacitor discharge voltage and the RC time constant of equation (4.3). In order to discharge


Frequency (GHz)

0.05 0.495 0.95 1.95 2.95 3.95

Am

plit

ude (

dB

V)

-26

-24

-22

-20

-18

-16

-14

-12

-10

SS 27oC

SS 70oC

TT 27oC

TT 70oC

Figure 4.11: Integrating mixer SAR integration power over process corners for RF input of+2dBm.

the capacitor voltage to 10% of the initial voltage, ∆Vc = 0.1, the reset time is given by

treset =−[(

RRS +RSC

2N +RCM

)CT

]log(∆Vc) (4.6)

=−[(

90Ω+245Ω

211 +90Ω

)128pF

]log(0.1)

= 53ns

where RRS = 90Ω, RSC = 245Ω, RCM = 90Ω, and CT = 128pF. The simulated reset time is47.5ns (corner: SS 27C), which is close to the 53ns estimated in equation (4.6).

The integrating mixer SAR is simulated over process corners and temperature for a win-dow frequency of 1MHz. In Figure 4.11, the BW is illustrated for an RF input of +2dBm.As listed in Table 4.3, the BW ranges from 1.95GHz to 2.43GHz. The integration floor is−59.6dBV, which results in a maximum DR of 45.6dB. In Figure 4.12, the linearity is il-lustrated over process corners and temperatures. The 1dB compression point ranges from−0.2dBm to +2.6dBm.

Transient noise simulations for the integrator output is performed with no RF input signal


Input RF Amplitude (dBm)

-16 -14 -12 -10 -8 -6 -4 -2 0 2

IF O

utp

ut A

mplit

ude (

dB

V)

-35

-30

-25

-20

-15

-10

SS 27oC

SS 70oC

TT 27oC

TT 70oC

Figure 4.12: Integrating mixer SAR integration linearity over process corners for fRF = fLO =0.5GHz.

Table 4.3: Integrating mixer SAR corner simulation summary.

Corner SS 27 SS 70 TT 27 TT 70BW (GHz) 1.95 1.96 2.41 2.431dB Comp (dBm) −0.2 +1.6 +1.4 +2.6

at the common mode voltage. The average output noise power is −104.5dBm/Hz over a 2GHzBW for the SS 27 corner, where the ENBW is 1.5MHz for fw = 1MHz. This is equivalent toan average RMS output voltage of 230µV. The quantization noise of the SAR ADC is given byVFS/(2N

√12), where VFS is the full scale voltage. This results in an RMS quantization voltage

of 310µV. As such, the integrator noise is below the quantization noise of the design.In Table 4.4, the power breakdown is listed for a quadrature integrating mixer SAR. The

total power dissipation is 941µW when a 50% duty signal is applied for rs. The digitalcomponent, which consists of the window generation and SAR control logic, accounts of 14%of the total power dissipation.


Table 4.4: Integrating mixer SAR power simulation summary.

Supply Voltage Simulateda CircuitVDD 1.2V 380µW Input pair, SA Latch, CS-DAC (positive half)VDDI 1.2V 380µW CS-DAC (negative half)VDDA 1.1V 46µW Second stage of mixerVDDD 1.2V 135µW SAR & window generation logic

941µWa Corner: SS 27.

4.2.5 Conclusion

The integrating mixer SAR architecture implements the STFT-based energy detector for spec-trum sensing. The architecture utilizes an array of folded mixers that are connected to a com-mon subset of binary-weighted capacitive loads, which double as the sampling capacitors of an11-bit SAR ADC. The first mixer stage implements current-domain windowing while the sec-ond stage implements downconversion mixing, integration and charge redistribution. The arraystructure removes current restrictions on the selection of the window function, which improvesside-lobe reduction and fall off in the frequency domain. The integration time is proportionalto the size of the total load capacitance. This results in a trade-off between the DBW and areasince the 3-dB BW of the window function sets the DBW.

A prototype integrating mixer SAR was designed in IBM’s CMRF8SF 0.13µm CMOSprocess. Simulations demonstrate a BW range from 1.95GHz to 2.43GHz over process cornersand temperature with a 1dB compression point that ranges from −0.2dBm to +2.6dBm. Thetotal power dissipation is 941µW for a quadrature integrating mixer. In comparison to theintegrating mixer of Chapter 3, the integrating mixer SAR achieves superior power dissipationand incorporates SAR conversion at the cost of reduced BW and lower 1dB compression.

4.3 Integrating Mixer SAR Implementation

The prototype integrating mixer SAR described in Section 4.2 was implemented in IBM’sCMRF8SF 0.13µm CMOS process with 1.2V and 1.1V supplies and low-Vt devices for ana-log components. The capacitive loads were implemented with MIMCAPs while the digitalwindow generation and SAR logic is isolated from the analog circuitry in guard rings and lo-cated directly under the MIMCAPs. A unit capacitor size of 62.5fF was applied for the SARADC. In order to minimize area, two types of MIMCAPs were utilized: standard MIMCAPsfor the 4 LSBs and dual MIMCAPs for the 7 MSBs. The dual MIMCAPs have twice the ca-pacitance of the standard MIMCAPs per unit area and a minimum capacitance of 680fF. Adie microphotograph is shown in Figure 4.13. The binary-weighted SAR capacitor arrays are


BWCAIP+

BWCAIP-

BWCAQ+

BWCAQ-

C C C C

C C C C

DIG

C

C

C

C

C

C

C

C

C

C

M

SA

SA

1.135mm

1.17mm

SAR

SAR

Figure 4.13: Die microphotograph of integrating mixer SAR prototype (BWCA: binary-weighted capacitor array [SAR ADC], C: load capacitor [CL], DIG: digital [window], IP: in-phase, M: mixer [includes CS-DAC], Q: quadrature, SA: switch array, SAR [control logic]).

surrounded by 64pF capacitors that combine to form CL, which sets the integration time. Thesilicon area of the prototype is 1.33mm2. The prototype die is packaged in a 52 pin QFNpackage and mounted on a custom designed PCB.

Single-tone and two-tone tests over window and sampling frequency were conducted tocharacterize the integrating mixer SAR prototype and examine its performance. Spectrum es-timates, BW, DR, 1dB compression, THD, OIP3 and power dissipation are presented. Testresults for the SAR ADC include SNR, signal-to-noise-and-distortion ratio (SNDR), spurious-free dynamic range (SFDR), IMD and power dissipation over sampling frequency. The testsetup for the integrating mixer SAR prototype is presented in Section 4.3.1 while the measure-ment results are provided in three sections. In Section 4.3.2, measurement results are presentedfor the 11-bit SAR ADC when isolated from the integrating mixer. In Section 4.3.3, analogmeasurement results are presented for the integrating mixer without SAR conversion in orderto analyze the results without any quantization effects. Lastly, in Section 4.3.4, measurementresults are presented for the full prototype.


Prototype FPGAEP4CE22

5V/2.5VTranslator

NI 6534 Interface(68-pin)

RF Input(2 SMAs)

LO InputI/Q

(4 SMAs)

Serial Data I/Q

Control Signals

Clock(SMA)

BiasVoltages

Jumpers

Digital Settings

Regulators

Power(2 BNCs)

Supply Voltages

JTAG(10 Pin)

Clock Signals

PushbuttonReset

Diff.

Diff.

Figure 4.14: Integrating mixer SAR PCB block diagram.

Table 4.5: List of key components on the integrating mixer SAR PCB.

Item Manufacturer Part Number DescriptionBias Voltage Texas Instruments OPA350 Op amp (unity gain buffer)

Texas Instruments TPS79912 1.2V LDO regulatorFPGA Altera EP4CE22E22 Cyclone IV

RegulatorsAnalog Devices ADP123 0.8V to 5V LDO regulator

Texas Instruments TPS79912 1.2V LDO regulatorTexas Instruments TPS79925 2.5V LDO regulatorTexas Instruments TPS79650 5V LDO regulator

Translator Texas Instruments SN74LVCH16T245 2.5V to 5V translator

4.3.1 Test Setup

A 4-layer PCB was designed and fabricated as a testbed for the prototype. The PCB providessupply voltages, bias voltages, memory, and configures the prototype. A push button reset and7-segment LCD for debugging is also available on the PCB. A block diagram of the PCB isillustrated in Figure 4.14 while the main components are listed in Table 4.5. The differential IFanalog output can be probed from test points on the PCB and the digitized value is transmittedserially and stored on the FPGA. The FPGA serves three main functions: (1) system control andsynchronization; (2) initialization of data conversion, data acquisition and storage in SRAM;and (3) communication between the PCB and Matlab on a host computer through the NI DAQ.The bias voltages are generated with a low noise OP AMP in unity gain configuration with apotentiometer. A stacked capacitor with low ESR and insertion loss ≥ 30dB over DC to 5GHzprovides decoupling over a wide bandwidth [49]. The fabricated PCB measures 124mm by149mm and is illustrated in Figure 4.15, where the DUT is indicated.

External equipment is used to provide the RF signal, LO signal, clock signal, power andconfiguration data to the PCB as illustrated in Figure 4.16. The computer controls the exter-


Figure 4.15: Populated integrating mixer SAR PCB photograpgh.

AgilentE4422B / 83712B

Stanford ResearchDS360

O180 HybridCoupler

O180 HybridCoupler

RF Input

LO Input

PCB withPrototype

IF Input (Diff.)

Krytar

Krytar

++

AgilentE3631A

Computer(Matlab)

GPIBDC power

NI 6534Interface

Rhode & SchwarzSMT 03 / SMB100A

fsync

Agilent83712B / 8110A

Clock

SAR ADC Testing

Diff.

Diff.

I

Q

Figure 4.16: Test setup for integrating mixer SAR.


nal signal generators using GPIB, transmits configuration data and receives the digital outputstored on the FPGA from the prototype via the NI DAQ. The LO signal is provided by theRohde & Schwarz SMT 03 or SMB100A, which allow the relative phase offset to be adjusted.When the LO signal generator is synchronized to the RF signal generator, the in-phase andquadrature components can be captured using only a single integrating mixer SAR by adjust-ing the phase offset 90 in successive samples. The RF signal is provided by the AgilentE4422B or 83712B signal generator for a single tone while for a two-tone signal, the two sig-nal generators are coupled through the passive coupler ZFRSC-42 from mini circuits. Krytardouble arrow 180 hybrid couplers are utilized for single-ended to differential conversion forthe LO and RF signals. The clock signal is provided by the Agilent 83712B signal generator orAgilent 8110A pulse generator. The Stanford Research DS360 signal generator is utilized forsingle-tone and two-tone ADC testing for its superior linearity and low noise characteristics.Lastly, the Tektronix TDS3052B oscilloscope is used to probe rs and differential IF signalsdirectly from the PCB.

4.3.2 SAR ADC Measurement Results

In order to characterize the integrated 11-bit SAR ADC, the converter is isolated from the inte-grating mixer SAR prototype by applying the input signal directly to the IF port4 of the mixerand setting the mixer LO common mode voltage to 0V, thereby cutting off the LO switchingpairs and tail currents in the mixer. The SAR ADC is designed to operate for an input voltagebetween 0.6V ≤ VIF+/− ≤ 1.1V for a 1V differential voltage, which restricts the maximuminput to −6.85dBFS and the maximum converter resolution to 9.86-bit.

Operation of the SAR ADC prototype is confirmed up to a clock frequency of 11.5MHz,however, a SAR clock frequency of 10MHz is applied to be consistent with the measurementresults of the full system that are presented in Section 4.3.4. A master clock frequency of80MHz is applied to the FPGA to generate clk sar and clk win5 signals of 10MHz and8MHz, respectively, for 250kSPS operation. The capacitors of the SAR ADC are reset prior tothe sample mode for a minimum of 825ns, the majority of which is used for serial data trans-mission. The input signal frequency is selected for coherent testing such that fin = fs ·Mc/2M,where Mc ≥ 5 is the number of cycles and is chosen to be a prime number while 2M are thepoints in the FFT. The estimated number of bits (ENOB) is defined as

ENOB≡ SNDR(dB)−1.766.02

. (4.7)

4Bidirectional: input during ADC testing and output during integration mode of operation.5The clk win signal can be disabled during ADC characterization.


Frequency (kHz)

0 20 40 60 80 100

Po

we

r (d

BF

S)

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

HD2

-68.3dBFS

16384-pt FFT

NBW=12.2Hz

HD3

-60.8dBFS

-6.85dBFS

@ 15.61kHz

Figure 4.17: SAR ADC: measured output power spectrum for fs = 200kHz.

The peak SNDR of 45.4dB at −6.85dBFS 15.6128kHz input is observed with fs = 200kHzwhile consuming a total of 134µW from 1.1V/1.2V supplies. Figure 4.17 illustrates the mea-sured spectrum at peak SNDR. The third-order harmonic is 54dB below the input tone, whichindicates the converter is limited by thermal noise rather than the linearity. The peak ENOB is7.25-bits, which is 2.6-bits lower than the ideal converter resolution.

The SNDR, SNR, and SFDR performance is measured versus input amplitude, samplingfrequency, and input frequency. In Figure 4.18a, the input signal amplitude is increased from−30.42dBFS to−6.80dBFS. The SNDR increases linearly with input signal amplitude and theextrapolated SNDR value at 0dBFS is 52.14dB, which results in an ENOB of 8.37-bits. In Fig-ure 4.18b, the sampling frequency is increased from 50kHz to 250kHz while maintaining thesame fin : fs ratio. The SNDR increases with sampling frequency at a rate of +1.33dB/100kHzwith peak SNDR at 200kHz. Similarly, the SFDR increases with sampling frequency by ata rate of +2.87dB/100kHz. In Figure 4.18c, the input signal frequency is increased from1.13kHz to 124.91kHz. There is a slight reduction in SNDR with increasing input frequencyat a rate of −0.54dB/100kHz. The power dissipation is measured over sampling frequencyfrom 50kHz to 250kHz. As illustrated in Figure 4.19, the power scales linearly with samplingfrequency to a maximum of 164µW at fs = 250kHz. The performance results are summarized


Input Amplitude (dBFS)

-30 -25 -20 -15 -10 -5 0

SF

DR

, S

NR

, S

ND

R (

dB

)

20

30

40

50

60

SFDR

SNR

SNDR

fs=200kHz

fin

=15.61kHz

(a) Input amplitude.

Sampling Frequency (kHz)

50 100 150 200 250

SF

DR

, S

NR

, S

ND

R (

dB

)

40

45

50

55

60

SFDR

SNR

SNDR

fin

=0.1565 · fs/2

-6.85dBFS

(b) Sampling frequency.

Input Frequency (kHz)

0 20 40 60 80 100 120

SF

DR

, S

NR

, S

ND

R (

dB

)

30

40

50

SFDR

SNR

SNDRfs=250kHz

-6.85dBFS

(c) Input frequency.

Figure 4.18: SAR ADC: measured SFDR, SNR, and SNDR for single-tone input versus (a)input amplitude, (b) sampling frequency, and (c) input frequency.


Table 4.6: SAR ADC: measurement result summary.

Measured SimulatedTechnology 0.13µmSupply 1.1V/1.2VBandwidth 250kHz 375kHzSNDR (Peak, 0.5 · fs) 45.4dB, 43.8dB −SNR (Peak, 0.5 · fs) 46.2dB, 44.5dB −SFDR (Peak, 0.5 · fs) 54.0dB, 52.7dB −Max Input/Full Scale 1V/2.2VPower 164.0µW 119.4µW−163.9µWa

FOM1 5154 fJ-conv-step −FOM2 136.3dB −a Corners: SS to FF.

in Table 4.6, where the figure of merits (FOM) are defined as

FOM1 (J/conv-step)≡ Power/(

2 ·BW ·2ENOB), (4.8)

FOM2 (dB)≡ SNDR(dB)+10 · log10 (BW/Power) . (4.9)

The DNL and integral non-linearity (INL) are measured by applying a full scale sinusoidalinput to the ADC and collecting the output histogram [54]. However, in this case a 15.6128kHzsinusoid at the maximum input amplitude of −6.85dBFS is applied, which results in only asubset of 935 codes used from the possible 2048 codes. The subset ranges from code 558(−500.6mV) to code 1492 (502.7mV) with 1024 the zero code. As illustrated in Figure 4.20,the DNL is +1.7/− 1 LSB while the INL is +2.3/− 3.4 LSB. As the DNL > 1, the ADCtransfer function is not guaranteed to be monotonic. The spikes in the DNL and INL that occurat codes 640 (−412.5mV) and 1152 (137.5mV) correspond to b7 : ‘0’→ ‘1’, while the spikesthat occur at codes 768 (−275mV) and 1280 (275mV) correspond to b8 : ‘0’→ ‘1’. Theseresult in 9 missing codes (DNL = −1), however, the maximum INL error is only 0.36%. Atotal of 1.47×105 samples are used for the DNL and INL, which results in a DNL error of 0.2LSB with a 95% confidence [55]. The INL limits the maximum DR of the integrating mixerSAR. A maximum INL of 3.4 LSB reduces the converter resolution by 1.77 bits, resulting in amaximum resolution of 8.09-bits6. Considering an RMS quantization noise voltage of 1.06mVfor an 8.09-bit converter with a 1V differential input, the maximum DR of the integrating mixerSAR is 46.3dB with a 220mV IF voltage drop.

A measured spectrum for a two-tone input near the band edge is illustrated in Figure 4.21.The tones are placed 7.44kHz apart near the band edge at 104.77kHz and 112.21kHz. In orderto prevent overloading, the tones are −12.87dBFS, which is 6dB lower than the peak-SNDR

6Maximum converter resolution is 9.86-bits with 1V differential input minus 1.77 bits for INL error.


Sampling Frequency (kHz)

50 100 150 200 250

Pow

er

(mW

)

0

0.05

0.1

0.15

0.2

Figure 4.19: SAR ADC: measured power versus sampling frequency.

Code

600 700 800 900 1000 1100 1200 1300 1400

DN

L (

LS

B)

-2

-1

0

1

2

DNL = +1.7 / -1 LSB

(a) DNL

Code

600 700 800 900 1000 1100 1200 1300 1400

INL

(L

SB

)

-4

-2

0

2

4

INL = +2.3 / -3.4 LSB

(b) INL

Figure 4.20: SAR ADC: measured DNL and INL.


Frequency (kHz)

0 20 40 60 80 100 120

Pow

er

(dB

FS

)

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

IMD

-51.5dBc

-12.87dBFS

7.44kHz apart

8192-pt FFT

NBW=30.5Hz

Figure 4.21: SAR ADC: measured two-tone power spectrum for fs = 250kHz.

single tone input. The measured IMD is −51.5dBc, which indicates the converter is limited bythermal noise rather than the linearity.

4.3.3 Analog Measurement Results

The measurement results in this section are computed with the in-phase integrating mixer inorder to avoid mismatch between in-phase and quadrature mixers and for direct comparison tothe results of the integrating mixer prototype presented in Section 3.3.3. The LO and RF inputsare synchronized such that a spectrum estimate can be obtained by adjusting the phase offset90 in successive samples.

The measured power spectrum of a tone at 0.5GHz with an input power of +2dBm isillustrated in Figure 4.22 for all values of the window frequency. The LO frequency is sweptover 250kHz intervals, which shows spreading of the input signal. The side-lobe oscillationsare nearly completely suppressed, which is expected as the Hann window function achieves> 30dB side-lobe reduction. As shown in Table 4.7, the measured BW ranges from 1.1GHzto 1.4GHz with an average of 1.25GHz across all window frequencies. The DR is measuredin 0.1GHz intervals over an LO frequency range 0.5GHz to 1.4GHz for an input tone with+2dBm of power. In Figure 4.23, the DR is illustrated for window frequencies fw = 250kHz


Frequency (GHz)

0.495 0.4975 0.5 0.5025 0.505

Po

we

r (d

Bm

)

-35

-30

-25

-20

-15

-10

-5

0

5

fw

=250kHz

fw

=333kHz

fw

=500kHz

fw

=1MHz

Figure 4.22: Integrating mixer SAR analog testing: spectrum estimates for a tone at 0.5GHzwith +2dBm of power and fw = 250kHz, fw = 333kHz, fw = 500kHz and fw = 1MHz.

Table 4.7: Integrating mixer SAR analog testing: measurement result summary.

fw DBW DRave BW Integration Gain 1dB Compression250kHz 360kHz 30.5dB 1.1GHz −15.1dB +0.5dBm333kHz 480kHz 25.6dB 1.4GHz −14.8dB +0.5dBm500kHz 720kHz 27.3dB 1.25GHz −15.1dB +0.5dBm1MHz 1.44MHz 30.5dB 1.2GHz −15.5dB +1.0dBm

and fw = 500kHz with linear regression applied for the line of best fit. For fw = 250kHz, theaverage DR is 30.5dB while for fw = 500kHz, the average DR is 27.3dB. The measured resultsfor fw = 333kHz and fw = 1MHz are listed in Table 4.7 and are illustrated in Figure B.3 ofAppendix B.

There is a constant integration gain associated with each window frequency, which is pro-portional to the DC voltage drop across the capacitive loads. In Figure 4.24, the 1dB compres-sion curves are illustrated for fw = 250kHz and fw = 500kHz. The 1dB compression points are+0.5dBm with an integration gain of −15.1dB for both fw = 250kHz and fw = 500kHz. Theresults for fw = 1.33MHz and fw = 4MHz are listed in Table 4.7 and illustrated in Figure B.4of Appendix B. The THD for a tone at 0.5GHz with an input power of −0.5dBm is 2.64%.

Two-tone testing is applied across the full BW in order to measure the IMD products and


Frequency (GHz)

0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4

DR

(dB

)

26

28

30

32 DRave

=30.5dB

BW=1.1GHz

fw

=250kHz

(a) fw = 250kHz

Frequency (GHz)

0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4

DR

(dB

)

24

26

28

30

DRave

=27.3dB

BW=1.25GHz

fw

=500kHz

(b) fw = 500kHz

Figure 4.23: Integrating mixer SAR analog testing: dynamic range from 0.5Ghz to 1.4GHzwith line of best fit for fw = 250kHz and fw = 500kHz.


Input Power (dBm)

-12 -10 -8 -6 -4 -2 0 2

Ou

tpu

t P

ow

er

(dB

V)

-28

-26

-24

-22

-20

-18

-16

-14

-12

1dB=+0.5dBm

fw

=250kHz

(a) fw = 250kHz

Input Power (dBm)

-12 -10 -8 -6 -4 -2 0 2

Ou

tpu

t P

ow

er

(dB

V)

-28

-26

-24

-22

-20

-18

-16

-14

-12

1dB=+0.5dBm

fw

=500kHz

(b) fw = 500kHz

Figure 4.24: Integrating mixer SAR analog testing: 1dB Compression for fw = 250kHz andfw = 500kHz.


Table 4.8: Integrating mixer SAR analog testing: third-order intercepts.

Tones (@2dBm) OIP3525MHz, 550MHz +14.1dBm700MHz, 800MHz +12.5dBm

1000MHz, 1025MHz +16.4dBm

Table 4.9: Integrating mixer SAR analog testing: power summary.

Supply Voltage Measured Simulateda CircuitVDD 1.2V 325µW 313µW Input pair, SA Latch, CS-DAC (positive half)VDDI 1.2V 407µW 391µW CS-DAC (negative half)VDDA 1.1V 43µW 44µW Second stage of mixerVDDD 1.2V 31µW 136µW Window generation logic

806µW 884µWa Corner: SS 27.

compute the OIP3. In Table 4.8, the OIP3 is measured for three pairs of input tones with apower of +2dBm. The OIP3 ranges from +12.5dBm to +16.4dBm.

The overall performance of the integrating mixer SAR prototype is summarized in Table4.7, which lists the average DR, integration gain, and 1dB compression point for each windowfrequency. The total power dissipation is 806µW with a full breakdown listed in Table 4.9.The measured power dissipation is within 9% of the simulated.

4.3.4 Digital Measurement Results

The measurement results in this section are computed with the in-phase integrating mixer inorder to avoid mismatch between in-phase and quadrature mixers and for direct comparison tothe results of the integrating mixer prototype presented in Section 3.3.3. The LO and RF inputsare synchronized such that a spectrum estimate can be obtained by adjusting the phase offset90 in successive samples.

The measured power spectrum of a tone at 0.5GHz with an input power of +2dBm isillustrated in Figure 4.25 for all values of the window frequency. The LO frequency is sweptover 250kHz intervals, which shows spreading of the input signal. The side-lobe oscillationsare nearly completely suppressed, which is expected as the Hann window function achieves> 30dB side-lobe reduction. As shown in Table 4.10, the measured BW is 1.25GHz across thetested window frequencies. The DR is measured in 0.1GHz intervals over an LO frequencyrange 0.5GHz to 1.3GHz for an input tone with +2dBm of power. In Figure 4.26, the DRis illustrated for window frequencies fw = 250kHz and fw = 500kHz with linear regressionapplied for the line of best fit. For fw = 250kHz, the average DR is 27.9dB while for fw =

500kHz, the average DR is 25.7dB.There is a constant integration gain associated with each window frequency, which is pro-


Frequency (GHz)

0.498 0.499 0.5 0.501 0.502

Po

we

r (d

Bm

)

-35

-30

-25

-20

-15

-10

-5

0

5

fw

=250kHz

fw

=500kHz

Figure 4.25: Integrating mixer SAR digital testing: spectrum estimates for a tone at 0.5GHzwith +2dBm of power and fw = 250kHz and fw = 500kHz.

Table 4.10: Integrating mixer SAR digital testing: measurement result summary.

fw DBW DRave BW Integration Gain 1dB Comp.250kHz 360kHz 27.9dB 1.25GHz −13.9dB +0.2dBm500kHz 720kHz 25.7dB 1.25GHz −13.5dB +0.2dBm

portional to the DC voltage drop across the capacitive loads. In Figure 4.27, the 1dB com-pression curves are illustrated for fw = 250kHz and fw = 500kHz. The 1dB compressionpoints are +0.2dBm for fw = 250kHz with an integration gain of −13.9dB and +0.2dBm forfw = 500kHz with an integration gain of −13.5dB. The THD for a tone at 0.5GHz with aninput power of −0.5dBm is 0.79%.

Two-tone testing is applied across the full BW in order to measure the IMD products andcompute the OIP3. In Table 4.11, the OIP3 is measured for three pairs of input tones with apower of +2dBm. The OIP3 ranges from +10.6dBm to +13.4dBm.

The overall performance of the integrating mixer SAR prototype is summarized in Table4.10, which lists the DR, integration gain, and 1dB compression point for each window fre-quency. The total power dissipation is 878µW with a full breakdown listed in Table 4.12. Themeasured power dissipation is within 7% of the simulated.


Frequency (GHz)

0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3

DR

(dB

)

24

26

28

30 DRave

=27.9dB

BW=1.25GHz

fw

=250kHz

(a) fw = 250kHz.

Frequency (GHz)

0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3

DR

(dB

)

24

26

28

30DR

ave=25.7dB

BW=1.25GHz

fw

=500kHz

(b) fw = 500kHz.

Figure 4.26: Inetgrating mixer SAR digital testing: dynamic range over 0.5GHz to 1.3GHzwith line of best fit for fw = 250kHz and fw = 500kHz.


Input Power (dBm)

-12 -10 -8 -6 -4 -2 0 2

Ou

tpu

t P

ow

er

(dB

V)

-28

-26

-24

-22

-20

-18

-16

-14

-12

-101dB=+0.2dBm

fw

=250kHz

(a) fw = 250kHz

Input Power (dBm)

-12 -10 -8 -6 -4 -2 0 2

Ou

tpu

t P

ow

er

(dB

V)

-28

-26

-24

-22

-20

-18

-16

-14

-12

-101dB=+0.2dBm

fw

=500kHz

(b) fw = 500kHz

Figure 4.27: Integrating mixer SAR digital testing: 1dB compression for fw = 250kHz andfw = 500kHz.


Table 4.11: Integrating mixer SAR digital testing: third-order intercepts.

Tones (@2dBm) OIP3525MHz, 550MHz +12.7dBm800MHz, 1000MHz +13.4dBm

1175MHz, 1200MHz +10.6dBm

Table 4.12: Integrating mixer SAR digital testing: power summary.

Supply Voltage Measured Simulateda CircuitVDD 1.2V 329µW 380µW Input pair, SA Latch, CS-DAC (positive half)VDDI 1.2V 408µW 380µW CS-DAC (negative half)VDDA 1.1V 48µW 46µW Second stage of mixerVDDD 1.2V 93µW 135µW SAR & window generation logic

878µW 941µWa Corner: SS 27.

4.3.5 Conclusion

A prototype of the integrating mixer SAR was implemented in IBM’s CMRF8SF 0.13µmCMOS process, fabricated, packaged, and mounted on a custom PCB for laboratory testing.The measured results for the SAR ADC in Section 4.3.2 indicate a peak SNDR of 45.4dB atfs = 200kHz for an ENOB of 7.25-bits, which is 2.61-bits lower than expected. This is partlydue to mismatch between the 1pF unit capacitors implementing the the 7 MSB capacitors, the62.5fF unit capacitors implementing the 4 LSB capacitors and the 64pF load capacitors thatsurround the binary-weighted SAR capacitor arrays. The capacitor layout can be improvedby using the common centroid technique, which minimizes gradients between capacitors. Inaddition, the 9 missing codes increase the INL error and contribute to the reduced ENOB.

The measured results for the integrating mixer without SAR conversion in Section 4.3.3indicate an average DR of 28.4dB and average BW of 1.25GHz across all window frequencies.The BW is lower than the simulated values shown in Table 4.3 over design corners, which varyfrom 1.95GHz to 2.43GHz. The measured results for BW are closest to the slow-slow corner.This is supported by the power dissipation results shown in Table 4.9, where the simulatedresults are for the slow-slow corner and are within 9% of the measured results. The 1dBcompression point is within the −0.2dBm to +1.6dBm range simulated with the slow-slowcorner.

The measurements results for the full integrating mixer SAR prototype in Section 4.3.4were conducted for only two of the four window frequencies: fw = 250kHz and fw = 500kHz.The results indicate an average DR of 26.8dB over a 1.25GHz BW for the tested windowfrequencies. In comparison to the analog measurement results, there is a 2.1dB loss with directSAR conversion for the average DR over the same window frequencies. The 1dB compressionpoint is slightly lower at +0.2dBm while the average integration gain increases by +1.4dB. In


addition, the OIP3 ranges from +10.6dBm to +13.4dBm, which on average is a 2.1dB loss.

4.4 Comparisons

In Table 4.13, the integrating mixer SAR prototype is compared to recent mixed-signal spec-trum sensing implementations that are based on energy detection [15] [16] [17] [50] and thefirst integrating mixer prototype. The STFT is implemented in [15] and [16], while a RSSIcircuit is implemented in [17]. The RSSI energy detector utilizes limiting amplifiers, pro-grammable current mirrors, and a LPF to realize a rectifier-based energy detector with variablesensitivity. A wideband spectrum sensing solution is proposed in [50], which implements awavelet-based energy detector with edge detection for UWB signals and is the only implemen-tation that does not target IEEE 802.22 WRAN.

In comparison to recent spectrum sensing implementations, the integrating mixer SAR pro-totype achieves greater than 15× reduction in power dissipation and an average DR of 26.8dB,which is slightly higher than the average DR of [16]. This leads to the highest DR/P value of28.6− 31dB/mW, where DR/P is used to measure the implementation efficiency. The higherthe value of DR/P, the less power required per 1-dB of DR. The RSSI design in [17] obtainsthe second largest frequency range and the largest DR at 48dB, however, the high DR is onlyachieved in the wide-DR mode which covers input powers between −30dBm to +18dBmwhere the overall gain is dependent on the mode of the RSSI detector. The wavelet-basedimplementation of [50] achieves the widest BW and the second largest DR but has a muchwider DBW (on the order of the wavelet frequency) and does not operate below 3.1GHz. Thehigher power consumption of the STFT implementations in [15] and [16] are in part due todirect realization of the STFT (with two double balanced mixers and an integrator) and thehigh resolution DAC utilized for the digital window generation.

The comparison works included here are complete receiver designs with LNA and gainstages prior to the spectrum sensing implementation. The receiver with the minimum sensitiv-ity is [17], which obtains a sensitivity of −83dBm after 67dB of gain in the analog front end.The sensitivity of [15], [16] and [50], are −74dBm, −72.5dBm, and −75dBm, respectively.The average noise floor for the integrating mixer SAR prototype is−25dBm. In order to matchthe sensitivity of−83dBm obtained by [17], the proposed design would require an analog frontend with a LNA and gain stages that provide 58dB. This is less gain than that required by [17].

In comparison to the first integrating mixer prototype, the second integrating mixer SARprototype decreases the power dissipation by over 60% while slightly increasing the averageDR to 26.8dB. As a consequence, the second prototype achieves a higher DR/P value of 28.6−31dB/mW. The second prototype improves the minimum DBW from 980kHz to 360kHz,


Tabl

e4.

13:C

ompa

riso

nof

mix

ed-s

igna

lspe

ctru

mse

nsin

gim

plem

enta

tions

base

don

ener

gyde

tect

ion.

[15]

[16]

[17]

[50]

Inte

grat

ing

Mix

erIn

tegr

atin

gM

ixer

SAR

(1st

Prot

otyp

e)(2

ndPr

otot

ype)

Tech

nolo

gy0.

18µ

m0.

18µ

m90

nm65

nm0.

13µ

m0.

13µ

mSu

pply

(V)

1.8

1.8

1.2

1.0

1.2

1.2/

1.1

P(m

W)

43.2

a23

.8a

13.9

b26

.4−

47.9

c2.

6d0.

9D

R(d

B)

3224

29−

4835

22−

25.2

25.7−

27.9

Ran

ge(G

Hz)

0.4−

0.9

0.4−

0.9

0.03−

2.4

3.1−

10.6

0.05−

2.2

0.05−

1.25

Win

dow

orW

avel

etco

s4x

cos4

xn/

aTr

iang

ular

Han

n(α

=0.

85)

Han

n(α

=0.

5)f w

(MH

z)0.

025−

10.

025−

1n/

a66−

132

1−4

0.25−

1D

BW

(MH

z)0.

05−

20.

05−

20.

2−30

n/a

0.98−

3.92

0.36−

1.44

RX

Sens

itivi

ty(d

Bm

)−

74−

72.5

−83

−75

n/a

n/a

DR

/P(d

B/m

W)

0.7

1.0

2.1−

3.4

0.7−

1.3

8.5−

9.7

28.6−

31a

Pow

erfo

rana

log

corr

elat

oran

ddi

gita

lwin

dow

gene

ratio

n.b

Pow

erfo

rmix

er,B

Bfil

tera

ndR

SSIc

ircu

itry.

cPo

wer

forL

NA

,QPL

L,a

nalo

gco

rrel

ator

,and

wav

elet

gene

rato

rove

rLO

freq

uenc

yra

nge.

dE

stim

ated

pow

erfo

radu

alm

ixer

base

don

sing

lem

ixer

.


however, the BW is reduced from 2.2GHz to 1.25GHz. The power reduction is due in partto the reduced maximum tail current of the input differential pair (1.1mA to 0.356mA) aswell as the reduced average value of the current window function over the integration period(0.75 · iw,max to 0.5 · iw,max). The reduced power is a trade-off with BW, which is reduced alongwith the power dissipation.

The DR of the proposed design, 26.8dB, is a trade-off with the resultant low power dis-sipation of 0.9mW. However, even at 26.8dB the DR matches or is within range of recentimplementations while achieving the lowest power dissipation. The DBW of the proposed de-sign, which ranges from 360kHz to 1.44MHz, is limited by the integrating capacitor size. Iflarger capacitors were utilized the DBW would improve while maintaining the same powerdissipation at the cost of area, which has been confirmed by the second prototype. With thetrend of increasing BW and the need for fast and low-power solutions, even a minimum DBWof 360kHz may be an acceptable design trade-off.

4.5 Conclusion

This chapter introduced the integrating mixer SAR architecture that implements the STFT-based energy detector for spectrum sensing. The architecture utilizes an array of folded mixersthat are connected to a common subset of binary-weighted capacitive loads, which double asthe sampling capacitors of an 11-bit SAR ADC. The first mixer stage implements current-domain windowing while the second stage implements downconversion mixing, integrationand charge redistribution.

A prototype of the integrating mixer SAR was implemented in IBM’s CMRF8SF 0.13µmprocess, fabricated, packaged, and mounted on a custom PCB for laboratory testing. Theintegrating mixer SAR prototype achieves an average DR of 26.8dB and a BW of 1.25GHzacross window frequencies of 250kHz and 500kHz, which correspond to DBWs of 360kHzand 720kHz, respectively. The design achieves a minimum OIP3 of +10.6dBm and a 1dBcompression of +0.2dBm. The total power dissipation for a quadrature integrating mixer SARis 878µW, which includes 11-bit SAR conversion. One full sweep over the entire 808MHzDTV frequency range takes 18ms with fw = 250kHz and a rs signal with 50% duty ratio,which is well under the < 2s sensing limit for IEEE 802.22 WRAN. That time drops to 6.7mswith fw = 500kHz.

The integrating mixer SAR prototype improves upon the performance of the integratingmixer prototype of Chapter 3 with the former achieving lower power dissipation, finer DBW,improved DR, and increased side-lobe suppression while digitizing the final value of the STFT.The main drawback of the integrating mixer SAR prototype is decreased BW and a slight reduc-


tion in linearity. In comparison to recent mixed-signal spectrum sensing implementations, theintegrating mixer SAR prototype achieves greater than 15× reduction in power consumptionwhile achieving an average DR that falls within the reported range. The design incorporatesmixing, baseband filtering and analog-to-digital conversion which further reduces the overallpower consumption beyond the spectrum sensing component when implemented within a fullreceiver7.

The integrating mixer architecture is well suited for integration within low power cogni-tive radio transceivers that target portable IEEE 802.22 WRAN applications. The integratingmixer prototype can be utilized with cooperative spectrum sensing or as the first in a dual-stage sensing process to quickly identify potential vacant spectrum for detailed sensing withcyclostationary feature detection and exceeds the BW requirements of IEEE 802.22 WRAN.

7During spectrum sensing operation.

Chapter 5

Conclusion

This dissertation focused on mixed-signal architectures for spectrum sensing with an emphasison non-coherent signal detection for implementation in cognitive radio networks. The inef-ficient use of the radio spectrum requires a new approach to spectrum allocation, which hasopened the door to spectrum sharing techniques such as cognitive radio. Spectrum sensing isthe enabling technology, which detects unused segments of the frequency spectrum for datatransmission.

A novel integrating mixer architecture for mixed-signal spectrum sensing was introducedthat implements the STFT-based energy detector. The architecture consists of a folded doublebalanced mixer with capacitive loads that implements current-domain windowing in the firststage while downconversion mixing and integration is implemented in the second stage. Aprototype integrating mixer was designed and fabricated in IBM’s CMRF8SF 0.13µm CMOSprocess. The measured results indicate an average DR of 24.2dB across a 2.2GHz BW overwindow frequencies, which range from 1MHz to 4MHz. The power dissipation is 1.55mW fora single integrating mixer. One full sweep over the entire 808MHz DTV frequency range withdual integrating mixers takes 1.7ms with fw = 1MHz (DBW = 0.98MHz) and a rs signal with50% duty ratio, which is well under the < 2s sensing limit for IEEE 802.22 WRAN.

The integrating mixer architecture was extended by utilizing binary-weighted load capaci-tors, which integrates the IF signal and acts as the sampling capacitors for an integrated SARADC. The integrating mixer SAR architecture consists of an array of folded double balancedmixers connected to common binary-weighted load capacitors. Current-domain windowingis implemented in the first stage while the second stage implements downconversion mixing,integration and SAR conversion. The array structure removes current restrictions on the selec-tion of the window function, which improves side-lobe reduction and fall off in the frequencydomain. A prototype integrating mixer SAR was designed and fabricated in IBM’s CMRF8SF0.13µm CMOS process. The measured results indicate an average DR of 26.8dB across a

89

CHAPTER 5. CONCLUSION 90

1.25GHz BW over window frequencies, which range from 250kHz to 500kHz. The integratedSAR ADC achieves a peak SNDR of 45.4dB at 200kHz for an ENOB of 7.25. The powerdissipation is 0.88mW for a full quadrature integrating mixer SAR. One full sweep over theentire 808MHz DTV frequency range takes 18ms with fw = 250kHz (DBW = 360kHz) anda rs signal with 50% duty ratio, which is well under the < 2s sensing limit for IEEE 802.22WRAN.

The effect of technology scaling on the integrating mixer architectures is twofold. First,as the supply voltage is reduced at a faster rate than the threshold voltage, the headroom forbiasing is reduced. This affects all analog circuits. Second, the magnitude of the spectrum isdependent upon the differential voltage drop across the capacitive loads in the second stageand as the supply voltage is reduced, the magnitude is reduced along with the DR. One way toovercome the DR reduction is to increase the current of the first stage, thereby increasing thesensitivity (i.e. transconductance) and reducing the common DC offset at the integrator output.Alternatively, the folded mixers can be connected to two sets of capacitive loads, where thetwo sets are interleaved and an ADC samples the integrator output iteratively. In this way, oneset of capacitive loads can reset while the other set integrates the IF signal and the magnitudeis the sum of the integrator samples. This method can also be used to reduce the area impactof the capacitors while increasing the integration period so as to achieve finer DBW.

In comparison to recent spectrum sensing implementations, the integrating mixer proto-types achieve the lowest power dissipation while achieving a DR that falls within the reportedrange. The prototypes incorporate mixing and baseband filtering while in addition, the secondprototype incorporates analog-to-digital conversion. This further reduces the overall powerconsumption in addition to that of the spectrum sensing component. The integrating mixerprototypes are well suited for integration within low power cognitive radio transceivers thattarget portable IEEE 802.22 WRAN applications such as public safety networks.

5.1 Future Work

The STFT-based integrating mixer prototypes implemented partial direct downconversion re-ceivers without a LNA or gain stages. This necessitated the use of an active mixer to maximizethe gain in order to compete with full receiver implementations that incorporated spectrumsensing. A full receiver implementation with LNA provides enough gain to allow for the useof a passive mixer that could, in turn, improve linearity. In addition, the integrating mixer pro-totypes could be used for the second downconversion stage in a Weaver receiver architecturein order to incorporate image rejection.

Several improvements can be realized in the implementation of the integrating mixer SAR,

CHAPTER 5. CONCLUSION 91

which can lead to increased performance of the integrated SAR ADC. A common centroid lay-out for the the binary-weighted capacitor array and a single unit capacitor size would minimizegradients between capacitors and result in better matching. In addition, serial transmissioncannot take place during a conversion which limits the maximum sampling rate. A dedicatedregister for the serial output can eliminate that condition and maximize the sampling rate.

A novel area that may benefit from spectrum sensing is wireline transceivers, namely serial-to-deserial (SERDES) transceivers. Spectrum sensing could be utilized to estimate the channelimpulse response since the input spectrum is a known quantity. The channel impulse responsecould then be utilized for adaptation of the decision feedback equalizer and to prevent equalizerdrift over time.

Appendix A

Spectrum Amplitude Estimation

In this section a method is derived to estimate the amplitude spectrum of a sinusoidal inputtone with a single downconversion mixer.

A transmitted signal s(t) is defined as

s(t) = Asin [2π fRFt +θ ] (A.1)

where A is the transmitted symbol and θ is the unknown phase offset between the transmitterand receiver.

The received downconverted signal is given by

x(t) =s(t) · sin[2π fLOt]

=Asin [2π fRFt +θ ] · sin[2π fLOt]

=A2cos [2π ( fRF − fLO) t +θ ]− cos [2π ( fRF + fLO) t +θ ] (A.2)

After lowpass filtering, the higher frequency term ( fRF + fLO) is removed such that

x(t)' A2

cos [2π f∆t +θ ] (A.3)

where f∆ = fRF − fLO.The received signal in equation (A.3) is a sinusoid with a fixed offset. However, if x(t) is

sampled at random time intervals, the offset will be a random variable 0 ≤ θr ≤ 2π . There-fore, x(t) can be modeled as a discrete-time sampled sequence, x(n), with a random phase

92

APPENDIX A. SPECTRUM AMPLITUDE ESTIMATION 93

component, θr(n). The RMS voltage for N samples of x(n) is given by

VRMS ( fLO) =

√1N

N

∑n=1

[A2

cos [2π f∆n+θr(n)]]2

(A.4)

where VRMS ( fLO)' A/2√

2 for N 1.Therefore, the magnitude of the amplitude spectrum is

|Sxx ( fLO)|= 2√

2 ·VRMS ( fLO) . (A.5)

Appendix B

Additional Implementation Results

94

APPENDIX B. ADDITIONAL IMPLEMENTATION RESULTS 95

Frequency (GHz)

0.5 1 1.5 2 2.5 3

DR

(d

B)

20

22

24

26

28

DRave

=24.6dB

BW=2.2GHz

fw

=1.33MHz

(a) fw = 1.33MHz

Frequency (GHz)

0.5 1 1.5 2 2.5 3

DR

(d

B)

17

19

21

23

25

DRave

=22.0dB

BW=2.2GHz

fw

=4MHz

(b) fw = 4MHz

Figure B.1: Integrating mixer: dynamic range from 0.5Ghz to 3GHz with line of best fit forfw=1.33MHz and fw=4MHz.


Input Power (dBm)

-12 -10 -8 -6 -4 -2 0 2

Outp

ut P

ow

er

(dB

V)

-23

-21

-19

-17

-15

-13

-11

-91dB Comp=-1.0dBm

fw

=1.33MHz

(a) fw = 1.33MHz

Input Power (dBm)

-12 -10 -8 -6 -4 -2 0 2

Outp

ut P

ow

er

(dB

V)

-30

-28

-26

-24

-22

-20

-18

-16 1dB Comp=+2.0dBm

fw

=4MHz

(b) fw = 4MHz.

Figure B.2: Integrating mixer: 1dB compression for fw = 1.33MHz and fw =4MHz.


Frequency (GHz)

0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4

DR

(dB

)

23

24

25

26

27

28

DRave

=25.6dB

BW=1.4GHz

fw

=333kHz

(a) fw = 333kHz

Frequency (GHz)

0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4

DR

(dB

)

28

30

32 DRave

=30.5dB

BW=1.2GHz

fw

=1MHz

(b) fw = 1MHz

Figure B.3: Integrating mixer SAR analog testing: dynamic range from 0.5Ghz to 1.4GHz withline of best fit for fw = 333kHz and fw = 1MHz.


Input Power (dBm)

-12 -10 -8 -6 -4 -2 0 2

Ou

tpu

t P

ow

er

(dB

V)

-28

-26

-24

-22

-20

-18

-16

-14

-12

1dB=+0.5dBm

fw

=333kHz

(a) fw = 333kHz

Input Power (dBm)

-12 -10 -8 -6 -4 -2 0 2

Ou

tpu

t P

ow

er

(dB

V)

-28

-26

-24

-22

-20

-18

-16

-14

-12

1dB=+1dBm

fw

=1MHz

(b) fw = 1MHz.

Figure B.4: Integrating mixer SAR analog testing: 1dB compression for fw = 333kHz andfw =1MHz.

Bibliography

[1] National Telecommunications and Information Administration, “United StatesFrequency Allocations,” Washington, DC, 2003. [Online]. Available:https://www.ntia.doc.gov/files/ntia/publications/2003-allochrt.pdf

[2] Federal Communications Commission, “First report and order: Revision of part 15 of thecommission’s rules regarding ultra-wideband transmission systems (et docket 98-153),”FCC Docket No. 02-48, February 2002.

[3] ——, “Report and order: Revision of part 15 of the commission’s rules regarding oper-ation in the 57-64 ghz band (et docket no. 07-113),” FCC Docket No. 13-112, August2013.

[4] J. Yang, R. W. Brodersen, and D. Tse, “Addressing the dynamic range problem in cog-nitive radios,” in IEEE International Conference on Communications, June 2007, pp.5183–5188.

[5] Federal Communications Commission, “Spectrum policy task force report,” ET DocketNo. 02-155, November 2002.

[6] M.A. McHenry, D. McCloskey, D. Robertson, and J.T. MacDonald, “Spectrumoccupany measurements, Chicago, Illinois, November 16-18, 2005,” Vienna,VA, pp. 1–53, 2005. [Online]. Available: http://www.sharedspectrum.com/wp-content/uploads/NSF Chicago 2005-11 measurements v12.pdf

[7] A. Abidi, “The path to the software-defined radio receiver,” Solid-State Circuits, IEEE

Journal of, vol. 42, no. 5, pp. 954–966, May 2007.

[8] IEEE Standard for Information Technology, “Part 22: Cognitive Wireless RAN MediumAccess Control (MAC) and Physical Layer (PHY) Specifications: Policies and Proce-dures for Operation in the TV Bands,” New York, NY, July 2011.

99

BIBLIOGRAPHY 100

[9] ECMA, “ECMA-392: MAC and PHY for Operation in TV White Space,” Geneva,Switzerland, June 2012.

[10] M. Mueck, A. Piipponen, K. Kalliojarvi, G. Dimitrakopoulos, K. Tsagkaris, P. De-mestichas, F. Casadevall, J. Perez-Romero, O. Sallent, G. Baldini, S. Filin, H. Harada,M. Debbah, T. Haustein, J. Gebert, B. Deschamps, P. Bender, M. Street, S. Kandeepan,J. Lota, and A. Hayar, “ETSI reconfigurable radio systems: status and future directions onsoftware defined radio and cognitive radio standards,” IEEE Communications Magazine,vol. 48, no. 9, pp. 78–86, Sept 2010.

[11] Federal Communications Commission, “Notice of proposed rulemaking: Amendmentof the commissions rules to provide spectrum for the operation of medical body areanetworks,” ET Docket No. 08-59, June 2009.

[12] J. Wang, M. Ghosh, and K. Challapali, “Emerging cognitive radio applications: A sur-vey,” Communications Magazine, IEEE, vol. 49, no. 3, pp. 74–81, March 2011.

[13] D. Cabric, “Cognitive radios: system design perspective,” Ph.D. dissertation, Departmentof Electrical Engineering and Computer Science, University of California, Berkeley, CA,2007.

[14] H. O. Kpojime and G. A. Safdar, “Interference mitigation in cognitive-radio-based fem-tocells,” IEEE Communications Surveys & Tutorials, vol. 17, no. 3, pp. 1511–1534, ThirdQuarter 2015.

[15] J. Park, T. Song, J. Hur, S. M. Lee, J. Choi, K. Kim, K. Lim, C.-H. Lee, H. Kim, andJ. Laskar, “A fully integrated UHF-band CMOS receiver with multi-resolution spectrumsensing (MRSS) functionality for IEEE 802.22 cognitive radio applications,” Solid-State

Circuits, IEEE Journal of, vol. 44, no. 1, pp. 258–268, Jan 2009.

[16] T. Song, J. Park, S. M. Lee, J. Choi, K. Kim, C.-H. Lee, K. Lim, and J. Laskar, “A 122-mw low-power multiresolution spectrum-sensing IC with self-deactivated partial swingtechniques,” Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 57, no. 3,pp. 188–192, March 2010.

[17] M. Kitsunezuka, H. Kodama, N. Oshima, K. Kunihiro, T. Maeda, and M. Fukaishi, “A 30-MHz-2.4-GHz CMOS receiver with integrated RF filter and dynamic-range-scalable en-ergy detector for cognitive radio systems,” Solid-State Circuits, IEEE Journal of, vol. 47,no. 5, pp. 1084–1093, May 2012.

BIBLIOGRAPHY 101

[18] K.-L. Du and W. H. Mow, “Affordable cyclostationarity-based spectrum sensing for cog-nitive radio with smart antennas,” Vehicular Technology, IEEE Transactions on, vol. 59,no. 4, pp. 1877–1886, May 2010.

[19] P. Sutton, K. Nolan, and L. Doyle, “Cyclostationary signatures in practical cognitive radioapplications,” Selected Areas in Communications, IEEE Journal on, vol. 26, no. 1, pp.13–24, Jan 2008.

[20] J. Proakis, Digital Communications, 4th ed. New York, NY: McGraw-Hill, 2001.

[21] Y. Zeng and Y. C. Liang, “Eigenvalue-based spectrum sensing algorithms for cognitiveradio,” IEEE Transactions on Communications, vol. 57, no. 6, pp. 1784–1793, June 2009.

[22] B. Razavi, “Cognitive radio design challenges and techniques,” IEEE Journal of Solid-

State Circuits, vol. 45, no. 8, pp. 1542–1553, Aug 2010.

[23] T. Christen, T. Burger, and Q. Huang, “A 0.13µm CMOS EDGE/UMTS/WLAN tri-mode∆Σ ADC with -92dB THD,” in 2007 IEEE International Solid-State Circuits Conference.

Digest of Technical Papers, Feb 2007, pp. 240–599.

[24] Z. M. Lee, C. Y. Wang, and J. T. Wu, “A CMOS 15-bit 125-MS/s time-interleaved ADCwith digital background calibration,” IEEE Journal of Solid-State Circuits, vol. 42, no. 10,pp. 2149–2160, Oct 2007.

[25] A. Venca, N. Ghittori, A. Bosi, and C. Nani, “A 0.076mm2 12b 26.5mw 600MS/s 4×-interleaved subranging SAR-∆Σ ADC with on-chip buffer in 28nm CMOS,” in 2016 IEEE

International Solid-State Circuits Conference (ISSCC), Jan 2016, pp. 470–472.

[26] S. Singh, M. Govindarajan, T. S. Venkatesh, W. Evans, A. Kansal, and S. S. Murali, “A23fj/conv-step 12b 290MS/s time interleaved pipelined SAR ADC,” in European Solid-

State Circuits Conference (ESSCIRC), Sept 2015, pp. 319–322.

[27] T. Tomioka, R. Sakata, T. Horiguchi, T. Tomizawa, and K. Inoue, “A/D converter clippingnoise suppression for high-sensitivity carrier-sensing of cognitive radio transceiver,” inIEEE Global Telecommunications Conference, Nov 2007, pp. 4170–4174.

[28] Q. Gu, RF System Design of Transceivers for Wireless Communications. New York,NY: Springer Science, 2005.

[29] L. Der and B. Razavi, “A 2-GHz CMOS image-reject receiver with LMS calibration,”IEEE Journal of Solid-State Circuits, vol. 38, no. 2, pp. 167–175, Feb 2003.

BIBLIOGRAPHY 102

[30] J. Xu, J. Chen, and J. Zheng, “Design of Weaver topology,” Electronics Letters, vol. 37,no. 18, pp. 1133–1135, Aug 2001.

[31] K. Banovic and A. Carusone, “A 1.55mw mixed-signal integrating mixer for direct spec-trum estimation in 0.13µm CMOS,” in Solid State Circuits Conference (A-SSCC), Nov2012, pp. 89–92.

[32] K. Banovic, “Mixed-signal architectures for spectrum sensing.” Poster presented at theBroadcom Technical Conference, June 2013.

[33] K. Banovic and T. Carusone, “A sub-mW spectrum sensing architecture for portable IEEE802.22 cognitive radio applications.” Submitted to the IEEE International Symposium

on Circuits and Systems (ISCAS), May 2017.

[34] Y. Hu, “CORDIC-based VLSI architectures for digital signal processing,” Signal Pro-

cessing Magazine, IEEE, vol. 9, no. 3, pp. 16–35, July 1992.

[35] R. Tandra and A. Sahai, “SNR walls for signal detection,” Selected Topics in Signal Pro-

cessing, IEEE Journal of, vol. 2, no. 1, pp. 4–17, Feb 2008.

[36] S. Atapattu, C. Tellambura, and H. Jiang, “Energy detection based cooperative spectrumsensing in cognitive radio networks,” Wireless Communications, IEEE Transactions on,vol. 10, no. 4, pp. 1232–1241, April 2011.

[37] J. Ma, G. Zhao, and Y. Li, “Soft combination and detection for cooperative spectrumsensing in cognitive radio networks,” IEEE Transactions on Wireless Communications,vol. 7, no. 11, pp. 4502–4507, November 2008.

[38] S. Bae and H. Kim, “Unlimited cooperative sensing with energy detection for cognitiveradio,” Journal of Communications and Networks, vol. 16, no. 2, pp. 172–182, April2014.

[39] W. Gardner, “Signal interception: a unifying theoretical framework for feature detection,”Communications, IEEE Transactions on, vol. 36, no. 8, pp. 897–906, Aug 1988.

[40] ——, “Measurement of spectral correlation,” Acoustics, Speech and Signal Processing,

IEEE Transactions on, vol. 34, no. 5, pp. 1111–1123, Oct 1986.

[41] R. S. Roberts, “Architectures for digital cyclic spectral analysis,” Ph.D. dissertation,Department of Electrical Engineering and Computer Science, University of California,Davis, CA, 1989.

BIBLIOGRAPHY 103

[42] R. Tandra and A. Sahai, “SNR walls for feature detectors,” in New Frontiers in Dynamic

Spectrum Access Networks, IEEE International Symposium on, April 2007, pp. 559–570.

[43] J. Allen, “Short term spectral analysis, synthesis, and modification by discrete fouriertransform,” IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. 25,no. 3, pp. 235–238, Jun 1977.

[44] M. Portnoff, “Magnitude-phase relationships for short-time fourier transforms based ongaussian analysis windows,” in Acoustics, Speech, and Signal Processing, IEEE Interna-

tional Conference on ICASSP ’79., vol. 4, Apr 1979, pp. 186–189.

[45] F. J. Harris, “On the use of windows for harmonic analysis with the discrete fourier trans-form,” Proceedings of the IEEE, vol. 66, no. 1, pp. 51–83, Jan 1978.

[46] J. Park, “CMOS analog spectrum processing techniques for cognitive radio applications,”Ph.D. dissertation, School of Electrical and Computer Engineering, Georgia Institute ofTechnology, Atlanta, GA, 2009.

[47] A. Rusznyak, “Filtering current mirror,” Circuits, Devices and Systems, IEE Proceedings

-, vol. 149, no. 4, pp. 218–220, Aug 2002.

[48] J. Park, C.-H. Lee, B.-S. Kim, and J. Laskar, “Design and analysis of low flicker-noiseCMOS mixers for direct-conversion receivers,” Microwave Theory and Techniques, IEEE

Transactions on, vol. 54, no. 12, pp. 4372–4380, Dec 2006.

[49] Johanson Dielectrics, “X2Y Filter & Decoupling Capacitors,” California, 2015. [Online].Available: http://www.johansondielectrics.com/x2y-filter-decoupling-capacitors.com

[50] N.-S. Kim and J. M. Rabaey, “A 3.1-10.6GHz wavelet-based dual-resolution spectrumsensing with harmonic rejection mixers,” in European Solid-State Circuits Conference

(ESSCIRC), Sept 2015, pp. 303–306.

[51] J. L. McCreary and P. R. Gray, “All-MOS charge redistribution analog-to-digital conver-sion techniques - part I,” IEEE Journal of Solid-State Circuits, vol. 10, no. 6, pp. 371–379,Dec 1975.

[52] T. Anderson, “Optimum control logic for successive approximation analog-to-digital con-verters,” JPL Technical Report, vol. XIII, pp. 168–176, February 1973.

[53] D. Schinkel, E. Mensink, E. Klumperink, E. van Tuijl, and B. Nauta, “A double-taillatch-type voltage sense amplifier with 18ps setup+hold time,” in Solid-State Circuits

Conference, IEEE International, Feb 2007, pp. 314–315.

BIBLIOGRAPHY 104

[54] M. Bossche, J. Schoukens, and J. Renneboog, “Dynamic testing and diagnostics of A/Dconverters,” Circuits and Systems, IEEE Transactions on, vol. 33, no. 8, pp. 775–785,Aug 1986.

[55] J. Blair, “Histogram measurement of ADC nonlinearities using sine waves,” Instrumen-

tation and Measurement, IEEE Transactions on, vol. 43, no. 3, pp. 373–383, Jun 1994.

by kevin banovic´ · and amer samarah for their advice on circuit design and practical information...

Documents