11

CAD Reference Flow for 3D Via-Last Integrated Circuits

Chang-Tzu Lin (林昌賜)

Information and CommunicationsResearch Lab. (ICL), ITRI, Taiwan

15th ASP-DAC, Jan. 20, 2010

215th ASP-DAC, Jan. 20, 2010

Outline

Introduction to 3D Integration

3D CAD Reference Flow in ITRI

Conclusions

3

Motivation for 3D Integration

Challenges below 22 nmProcess Variation

New materials = $$$Advanced Lithography

Extreme UV, or E-beamBoth = $$$

Thin/Small, Multi-functionHigh performance, Low power Heterogeneous integration...

15th ASP-DAC, Jan. 20, 2010

Source: ITRS, 2007

415th ASP-DAC, Jan. 20, 2010

Keys of 3D Integration

Source: Leti (Fr), D43D, 2009

, size = 2 µm x 2 µm

Source: ZyCube / Tohoku, MRS, 2009

515th ASP-DAC, Jan. 20, 2010

Outline

Introduction to 3D Integration

3D CAD Reference Flow in ITRI

Conclusions

615th ASP-DAC, Jan. 20, 2010

TSV-Related Terminologies

Through silicon via (TSV)Front metal (FM)Front via (FV)Front pad (FP)Back metal (BM)Back pad (BP)

715th ASP-DAC, Jan. 20, 2010

ITRI Integration Approach

Treat each TSV as a cell through silicon to FMScalable face-to-back bondingAlign BP with TSV to eliminate BP placement

815th ASP-DAC, Jan. 20, 2010

Layer Partition

TSMC 90nm-G process with TSV and FP cells

915th ASP-DAC, Jan. 20, 2010

Multi-Tier P&R Methodology

Technology Lef: FM/FV Liberty: FP/STC Wire Model: FM/FV GDS: FP/STC/FTC FP/STC Location Clock Skew

2D OA

Timing ConstraintsNetlists

Floorplanning

TSV-Aware Placement with Via-Alignment

Constraint

Multi-Tier Balanced CTS

Timing-Driven Routing

DRC/LVS Verification

Multi-Tier Mergence:DSPF and GDSII

Parasitic Extration

Timing Analysis

10

TSV-aware Placement with Via-alignment Constraints

Theorem 1: The alignment constraints can always be satisfied, if the placement of FP and STC is performed from the topmost tier to the bottommost tier.

15th ASP-DAC, Jan. 20, 2010

TSV

FPFM

BEOL

BM

Legal

Tier 1

Tier 2

Tier 3 Illegal: overlap

Property 1: On the same tier, no cell and block, except for the FP, can overlap with the STC, and no metal line can be routed over.

Property 2: On the same tier, any cell or block, except for the FP, can overlap with the FP, and any metal line can be routed over.

Chang-Tzu Lin

1115th ASP-DAC, Jan. 20, 2010

Multi-Tier Balanced CTS

Clock Root

Tier 1

Tier 2

Tier 3

+ 0.1ns

+ 0.2nsSkew

0.2ns

Skew- 0.1ns

1215th ASP-DAC, Jan. 20, 2010

3-Tier Case with Power TSV

Support 2 kinds of TSV diameters 5um Signal , 50um Power/Ground

(c) Top Tier(a) Bottom Tier (b) Middle Tier

1315th ASP-DAC, Jan. 20, 2010

Clock Tree Synthesis Results

1415th ASP-DAC, Jan. 20, 2010

Routing – DRC/LVS

Design rules are provided for the five extra mask layers

3D LVS need to evolve to tackle the vertical interconnect issues across tiers

15

PortText_A PortText_B PortText_C PortText_D PortText_E

Tier (n)

PortText_M PortText_N PortText_O

PortText_B PortText_A PortText_C PortText_D PortText_E

Tier (n+1)

PortText_W PortText_X PortText_Y PortText_Z

PortText_B PortText_A

PortText_A PortText_B

PASSMis-alignment

Mis-SizeMis-port

Mis-port

Different LVS Checking Types

15th ASP-DAC, Jan. 20, 2010

FPTSV/BM

1615th ASP-DAC, Jan. 20, 2010

BEOL & FM Routing

FV

FM

TSV

1715th ASP-DAC, Jan. 20, 2010

Outline

Introduction to 3D Integration

3D CAD Reference Flow in ITRI

Conclusions

1815th ASP-DAC, Jan. 20, 2010

Conclusions

Multi-Tier P&R Methodology TSV co-placement Via alignment constraintsBalanced CTSDRC/LVS

Future works on 3D IntegrationThermal Mechanical

1915th ASP-DAC, Jan. 20, 2010

THANKSTHANKS FORFOR YOURYOUR ATTENTIONATTENTION謝謝您的聆聽謝謝您的聆聽

CAD Reference Flow for 3D Via-Last Integrated CircuitsOutlineMotivation for 3D Integration Keys of 3D IntegrationOutlineTSV-Related Terminologies ITRI Integration ApproachLayer PartitionMulti-Tier P&R Methodology TSV-aware Placement with Via-alignment ConstraintsMulti-Tier Balanced CTS3-Tier Case with Power TSVClock Tree Synthesis Results Routing – DRC/LVS Different LVS Checking TypesBEOL & FM Routing OutlineConclusions

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