cĂn bẢn vỀ khuẾch ĐẠi Âm thanh lỚp d.doc

7/23/2019 CN BN V KHUCH I M THANH LP D.doc

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CN BN V KHUCH I M THANH LP DJun Honda & Jonathan Adams

Th no l mt b khuch i m thanh lp D Nguyn l hot ngMt b khuch i m thanh lp D v c bn l mt b khuch i ngt m hoc b khuch i xung

c iu ch rng (PWM). C mt s lp khuch i khc nhau; bt u ta hy nhc li cc lp:

A Class D audio amplifier is basically a switching amplifier or PWM amplifier. There are a number of different classes ofamplifiers. We will take a look at the definitions for the main classifications as an introduction:

Lp A trong khuch i lp A, tng ra hot ng lin tc trong ton chu k, hay ni cch khc llun lun c dng phn cc chy qua tng ra. Kiu ny c mo thp nht v tuyn tnh ln nhtnhng li c hiu sut thp nht, ch t khong 20%. Mch in hnh c thit k khng c s phihp gia cc linh kin pha (in p) cao v pha (in p) thp.

Class A In a Class A amplifier, the output devices are continuously conducting for the entire cycle, or in other words there isalways bias current flowing in the output devices. This topology has the least distortion and is the most linear, but at the same time isthe least efficient at about 20%. The design is typically not complementary with a high and low side output devices.

Lp B kiu khuch i ny hot ng ngc li vi kiu khuch i lp A. Cc linh kin tng ra ch

dn trong mt na chu k dng sin (mt linh kin dn trong bn k dng cn linh kin cn li dn trongbn k m), hay ni cch khc, nu khng c tn hiu a vo th s khng c dng in chy trong mchtng ra. Kiu khuch i ny c hiu sut cao hn so vi khuch i lp A, vo khong 50% nhng cmt s khuyt im v tuyn tnh ti im chuyn tip do mt mt khong thi gian linh kin ny ttv linh kin kia m.

Class B This type of amplifier operates in the opposite way to Class A amplifiers. The output devices only conduct for half thesinusoidal cycle (one conducts in the positive region, and one conducts in the negative region), or in other words, if there is no inputsignal then there is no current flow in the output devices. This class of amplifier is obviously more efficient than Class A, at about50%, but has some issue with linearity at the crossover point, due to the time it takes to turn one device off and turn the other deviceon.

Lp AB Kiu khuch i ny l t hp ca hai loi khuch i k trn, hin nay l mt trong nhngkiu khuch i cng sut ph bin nht. y c 2 linh kin tng ra c php dn ng thi nhng mc thp gn vi im ngt. Do tng linh kin dn trong hn mt na chu k nhng khng phi lton k, nn khc phc c cc nhc im km tuyn tnh ca loi B v hiu sut thp ca loi A.

Hiu sut ca khuch i lp AB vo khong 50%.Class AB This type of amplifier is a combination of the above two types, and is currently one of the most common types ofpower amplifier in existence. Here both devices are allowed to conduct at the same time, but just a small amount near the crossoverpoint. Hence each device is conducting for more than half a cycle but less than the whole cycle, so the inherent non-linearity of ClassB designs is overcome, without the inefficiencies of a Class A design. Efficiencies for Class AB amplifiers is about 50%.

Lp D Nh ni trn, loi khuch i ny l mt b khuch i chuyn mch hay PWM. Ti liuny s tp trung phn tch v lp khuch i ny. Trong kiu khuch i ny, cc b chuyn mch hocl ng hon ton hoc m hon ton, nn lm gim ng k tn hao cng sut trong cc linh kin tng ra. Hiu sut c th t ti 90-95%. Tn hiu m tn c s dng iu bin mt tn hiu sngmang PWM iu khin tng ra, vi tng cui l b lc thng thp (LPF) loi b tn hiu sng mangPWM c tn s cao.

Class D This class of amplifier is a switching or PWM amplifier as mentioned above. This class of amplifier is the main focusof this application note. In this type of amplifier, the switches are either fully on or fully off, significantly reducing the power losses inthe output devices. Efficiencies of 90-95% are possible. The audio signal is used to modulate a PWM carrier signal which drives theoutput devices, with the last stage being a low pass filter to remove the high frequency PWM carrier frequency.

T cc loi khuch i k trn, cc lp A, B v AB c gi chung l khuch i tuyn tnh. Trongphn sau, ta s tho lun v s khc nhau gia khuch i tuyn tnh v khuch i lp D. Trong hnh 1l s khi ca mt b khuch i tuyn tnh. Trong b khuch i tuyn tnh, tn hiu lun lun tn tidi dng tng t v cc transistor li ra hot ng nh nhng b iu khin tuyn tnh to nn inp ra. Kt qu l in p b st qua linh kin tng ra, lm gim hiu sut.

From the above amplifier classifications, classes A, B and AB are all what is termed linear amplifiers. We will discuss thedifferences between Linear and Class D amplifiers in the next section. The block diagram of a linear amplifier is shown below in fig 1.In a linear amplifier the signals always remain in the analog domain, and the output transistors act as linear regulators to modulatethe output voltage. This results in a voltage drop across the output devices, which reduces efficiency.

B khuch i lp D c nhiu dng khc nhau, mt s loi c th c li vo tn hiu s, loi khc lic th c li vo tn hiu tng t. y ta s bn v loi c tn hiu li vo tng t.


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Class D amplifiers take on many different forms, some can have digital inputs and some can have analog inputs. Here we willfocus on the type which have analog inputs.

Hnh 1 trn y trnh by s khi c bn ca mt b khuch i lp D na cu, vi dng sng timi tng. Mch ny s dng mt ng hi tip t li ra ca na cu b cho s bin i trong in pbus.

Fig 1 above shows the basic block diagram for a Half Bridge Class D amplifier, with the waveforms at each stage. This circuituses feedback from the output of the half-bridge to help compensate for variations in the bus voltages.

Nhng mt b khuch i lp D lm vic nh th no? Mt b khuch i lp D hot ng rt gingvi mt b ngun di rng hay ngun iu ch rng xung, m sau ny ta s c dp ch ra s ging

nhau . Ta hy bt u vi mt gi thit rng tn hiu vo l tn hiu audio vi mc chun. l tn hiudng sin vi tn s trong khong t 20Hz n 20.000Hz. Tn hiu ny c so snh vi sng dng rngca hay tam gic tn s cao to nn tn hiu PWM nh ta thy trong hnh 2a di y. Sau , tnhiu PWM ny c dng iu khin tng cng sut to nn tn hiu s khuch i, v cui cngc lc thng thp lc ht sng mang PWM tn s cao v khi phc tn hiu sin ban u (xem hnh2b)

So how does a Class D amplifier work? A Class D amplifier works in very much the same way as a PWM power supply (we willshow the analogy later). Lets start with an assumption that the input signal is a standard audio line level signal. This audio line levelsignal is sinusoidal with a frequency ranging from 20Hz to 20kHz typically. This signal is compared with a high frequency triangle orsawtooth waveform to create the PWM signal as seen in fig 2a below. This PWM signal is then used to drive the power stage,creating the amplified digital signal, and finally a low pass filter is applied to the signal to filter out the PWM carrier frequency andretrieve the sinusoidal audio signal (also seen in fig 2b).

Fig 2) Class D Amplifier Waveforms

So snh gia khuch i tuyn tnh vi khuch i lp DTopology Comparison Linear vs. Class DTrong phn ny ta s tho lun v s khc nhau gia cc b khuch i cng sut tuyn tnh (lp A

v AB) vi khuch i lp D. S khc nhau c bn nht gia chng l hiu sut. gn nh l l doquan trng nht pht minh ra khuch i lp DIn this section we will discuss the differences between linear (Class A and Class AB) amplifiers, and Class D digital power

amplifiers. The primary and main difference between linear and Class D amplifiers is the efficiency. This is the whole reason for theinvention of Class D amplifiers.

Cc b khuch i tuyn tnh di dng hon chnh vn rt tuyn tnh, nhng c hiu sut thpch vo khong 50% i vi mt b khuch i lp AB, trong khi khuch i lp D c hiu sut caohn nhiu, trong thc t c th t ti trn 90%. Trn hnh 3 cho thy cc ng cong hiu sut inhnh ca b khuch i tuyn tnh v khuch i lp D.


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The Linear amplifiers is inherently very linear in terms of its performance, but it is also very inefficient at about 50% typically fora Class AB amplifier, whereas a Class D amplifier is much more efficient, with values in the order of 90% in practical designs. Fig 3below shows typical efficiency curves for linear and Class D amplifiers.

Xt v khuch i, vi khuch i tuyn tnh, khuch i l khng i, khng b nh hng biin p bus, trong khi vi khuch i lp D th khuch i li t l vi in p bus. iu c nghal t s trit (thi) ngun nui - power supply rejection ratio (PSRR) ca khuch i lp D l bng 0 dB,trong khi PSRR ca khuch i tuyn tnh l rt tt. Do , trong khuch i lp D, ngi ta thng dng

hi tip b cho s thay i in p bus.Gain With Linear amplifiers the gain is constant irrespective of bus voltage variations, however with Class D amplifiers thegain is proportional to the bus voltage. This means that the power supply rejection ratio (PSRR) of a Class D amplifier is 0dB,whereas the PSRR of a linear amplifier is very good. It is common in Class D amplifiers to use feedback to compensate for the busvoltage variations.

Lung nng lng trong khuch i tuyn tnh, lun lun c nng lng i t ngun ra ti v trongkhuch i lp D cng vy. Tuy nhin vi khuch i lp D na cu th li khc, do lung nng lng cth c hai hng gy nn hin tng gi l bm bus, do t bus c np nh nng lng t ti quayv ngun. iu ny xy ra ch yu tn s thp, di 100Hz.

Energy Flow In linear amplifiers the energy flow is always from supply to the load, and in Full bridge Class D amplifiers this isalso true. A half-bridge Class D amplifier however is different, as the energy flow can be bi-directional, which leads to the Buspumping phenomena, which causes the bus capacitors to be charged up by the energy flow from the load back to the supply. Thisoccurs mainly at the low audio frequencies i.e. below 100Hz.

Fig 3 Linear and Class D Amplifier Efficiencies

Tnh tng ng vi b so snh o chiuAnalogy to a Synchronous Buck ConverterS tng ng n gin gia mt b khuch i lp D vi mt b so snh o chiu ng b. Ta c

th thy s tng ng c bn trong hnh 4 di y.A simple analogy can be made between a Class D amplifier and a synchronous buck converter.The topologies are essentially the same as can be seen below in fig 4.

Fig 4 Topologies for Synchronous Buck Converter and a Class D amplifier

S khc nhau c bn gia hai mch ny l ch tn hiu tham chiu ca so snh o chiu ng bl mt tn hiu thay i chm t mch hi tip (l mt in p c nh), cn trong trng hp khuch i

lp D th tn hiu tham chiu l tn hiu m tn thay i lin tc. iu c ngha l trong b so snh ochiu ng b th y xung l tng i c nh, trong khi y xung ca khuch i lp D ththay i lin tc vi xp trung bnh l 50%.

The main difference between the two circuits is that the reference signal for the synchronous buck converter is a slow changingsignal from the feedback circuit(a fixed voltage), in the case of the Class D amplifier the reference signal is an audio signal which iscontinuously changing. This means that the duty cycle is relatively fixed in the synch buck converter, whereas the duty iscontinuously changing in the Class D amplifier with an average duty of 50%.

Trong b so snh o chiu ng b, dng din lun lun hng v ti, nhng trong khuch i lpD th dng i theo c hai hng.

In the synch buck converter the load current direction is always towards the load, but in Class D the current flows in bothdirections.


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S khc nhau cui cng l ch cch thc s dng cc MOSFET sao cho ti u. B so snh ochiu ng b u tin cho s khc nhau gia cc MOSFET pha (in p) cao v (in p) thp cRDS(on) i vi y xung ln v Qg thp i vi y xung nh. B khuch i lp D c c hai u tin vi c hai MOSFET, vi cng gi tr RDS(on) vi c pha (in p) cao ln pha (in p) thp.

The final difference is in the way the MOSFETs are optimized. The Synch buck converter is optimized differently for the highand low side MOSFETs, with lower RDS(on) for longer duty and low Qg for short duty. The Class D amplifier has the same optimizationfor both of the MOSFETs, with the same RDS(on) for high and low side.

Tn hao cng sut trong cc MOSFETPower Losses in the MOSFETsTn hao trong cc b chuyn mch cng sut l rt khc nhau gia b khuch i tuyn tnh v b

khuch i lp D. Trc tin, ta hy xt tn hao trong b khuch i lp AB. tn hao c th c xcnh bi:

The losses in the power switches are very different between linear amplifiers and Class D amplifiers. First lets look at the lossesin a linear Class AB amplifier. The losses can be defined as:

tdtKR

VtK

VP

L

CCCCC

= sin2)sin1(221

0

Trong K l t s gia tn hiu li vo VBUS v in p li ra.Where K is the ratio of Vbus to output voltage.Do ta c th n gin ha biu thc tn hao chuyn mch i vi khuch i tuyn tnh nh sau:

This can then be simplified down to the following equation for the linear amplifier Power switch losses:

=

2

2

8

22KK

R

VP

L

CC

tot

Ch rng tn hao cng sut khng lin quan ti cc thng s ca cc linh kin tng ra. Hnh 5sau y cho thy tn hao cng sut theo K.

Note that the power loss is not related to the output device parameters. Fig 5) below shows the power loss vs K.

Fig 5) Power Loss vs. K for Linear Class AB AmplifierBy gi ta xt n khuch i lp D:Now lets look at the losses for a Class D amplifier.Tn hao cng sut tng cng tng ra ca khuch i lp D c tnh theo biu thc sau:The total power loss in the output devices for a Class D amplifier are given by:PTOTAL = PSW + Pcond + PGDPsw l tn hao chuyn mch v c tnh theo biu thc: PSW = COSS VBUS

2fPWM + IDVDStffPWM

Psw are the switching losses and are given by the equation:Pcond l tn hao do dn v c tnh theo biu thc:Pcond are the conduction losses and are given by the equation:

Pcond = OL

onDSP

R

R )(

PGD l tn hao iu khin cc ca ca FET v c tnh theo biu thc:Pgd are the gate drive losses and are given by the equation:

PGD = 2QgVGS fPWMNh ta c th thy trong khuch i lp D, tn hao tng ra ph thuc vo cc thng s ca cc linh

kin nn cn u tin s dng cc linh kin c hiu sut cao nht, trn c s cc thng s QG, RDS(on), COSSv tf. Hnh 6 sau y cho ta thy tn hao cng sut theo K ca b khuch i lp D.


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As can be seen in a Class D amplifier the output losses are dependant on the parameters of the device used, so optimization isneeded to have the most effective device, based on Qg, RDS(on), COSS, and tf. Fig 6 below shows the power losses vs K for the Class Damplifier.

Fig 6 Power Loss vs. K for Class D Amplifie

Bng 1: So snh gia khuch i na cu v khuch i cuTable 1: Topology Comparison (Half-bridge vs. Full-bridge)

S ging nhau gia cc b khuch i lp AB, lp D l c th phn thnh hai cu hnh l: na cu v

ton cuSimilar to conventional Class AB amplifiers, Class D amplifiers can be categorized into two topologies, half-bridge and full-bridge configurations.

Mi cu hnh u c u v nhc im. Ni ngn gn th b khuch i na cu n gin hn trongkhi khuch i cu th cho m thanh hon ho hn. Mt b khuch i ton cu i hi phi c hai bkhuch i na cu, cho nn cn nhiu linh kin hn. Tuy nhin cu trc kiu vi sai ca cu hnh khuchi ton cu cho php loi b cc thnh phn hi bc chn v bc l v thnh phn mt chiu ging nhtrong khuch i lp AB. Cu hnh khuch i ton cu cho php s dng s iu ch rng xungtt hn, chng hn nh b iu ch rng xung 3 mc, nh qu trnh lng t ha tn hiu nn c t lihn.

Each topology has pros and cons. In brief, a half-bridge is potentially simpler, while a full-bridge is better in audio performance.The full-bridge topology requires two half-bridge amplifiers, and thus, more components. However, the differential output structure ofthe bridge topology inherently can cancel even the order of harmonic distortion components and DC offsets, as in Class ABamplifiers. A fullbridge topology allows of the use of a better PWM modulation scheme, such as the three level PWM whichessentially has fewe errors due to quantization.

Trong cu hnh na cu, ngun cung cp c th b nng lng c bm ngc li t b khuchi, do in p vo thng ging mnh khi b khuch i xut ra tn hiu m tn c tn s thp. Vic trnng lng v ngun cung cp l c im c bn ca khuch i lp D.

In the half-bridge topology, the power supply might suffer from the energy being pumped back from the amplifier, resulting insevere bus voltage fluctuations when the amplifier outputs low frequency audio signals to the load. This kickback energy to thepower supply is a fundamental characteristic of Class D amplification.

Nhnh chuyn mch b trong b khuch i ton cu lm bo ton nng lng ca nhnh i dinnn nng lng c bm ngc li ngun cung cp.

Complementary switching legs in the full-bridge tend to consume energy from the other side of the leg, so there is no energybeing pumped back towards the power supply.


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Bng 1 trnh by tng qut v s so snh ni trnTable 1 shows the summary of the comparison.

Hnh 7 Nguyn nhn chnh ca s gim phm chtFig 7: Major Cause of Degradation

Mt tng khuch i lp D l tng khng mo v khng nhiu pht sinh trong di m tn, c th tti hiu sut 100%.

An ideal Class D amplifying stage has no distortion and no noise generation in the audible band, along with providing 100%efficiency.

Tuy nhin, nh trn hnh 7 ta thy, cc b khuch i lp D thc t c nhng nhc im nh phtsinh mo v nhiu. Nguyn nhn ca chng l do mo khi chuyn mch trong tng khuch i lp D vdo:

However, as shown in Fig 7, practical Class D amplifiers have imperfections that generate distortions and noise. Theimperfections are caused by the distorted switching waveform being generated by the Class D stage. The causes are:

1. S phi tuyn trong tn hiu PWM t b iu ch n tng chuyn mch do phn gii b gii hnv/ hoc s thay i thi gian xut hin tn hiu

Nonlinearity in the PWM signal from modulator to switching stage due to limited resolution and/or jitter in timing2. Sai lch thi gian thm vo do iu khin cc cng nh thi gian ngt, ton/toff, v tr/tf.Timing errors added by the gate drivers, such as dead-time, ton/toff, and tr/tf* dead-time: thi gian m thit b in va mi phn ng vi mt tc nhn kch thch, nn khng th phn ng

vi tc nhn kch thch tip theo = thi gian ngt3. Nhng c tnh khng mong mun trong cc linh kin chuyn mch, nh in tr ON hn ch, tc

chuyn mch b hn ch hay cc c tnh ca diode.Unwanted characteristics in the switching devices, such as finite ON resistance, finite switching speed or body diode

characteristics.4. Cc thnh phn k sinh gy nn nhiu lon ngn hn ti sn xung

Parasitic components that cause ringing on transient edges5. in p ngun cung cp b thng ging do tr khng ra ca n v tn hiu quay tr v li vo quang ngun

Power supply voltage fluctuations due to its finite output impedance and reactive power flowing through the DC bus6. Tnh phi tuyn trong b lc thng thp li raNon-linearity in the output LPF.Ni chung, sai lch thi gian xut hin tn hiu chuyn mch trong tn hiu ti cc ca l nguyn nhn

c bn nht gy nn mo phi tuyn. Trong thc t, li thi gian xut hin tn hiu do thi gian ngt c sng gp ng k ca tnh phi tuyn trong tng khuch i lp D. Mt lng nh thi gian ngt c hng


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chc nano giy c th gy nn mo iu ha tng cng (THD -Total Harmonic Distortion) trn 1%.Tnh ton thi gian xut hin tn hiu chuyn mch lun lun l mi quan tm u tin.

In general, switching timing error in a gate signal is the primary cause of the nonlinearity. The timing error due to dead-time inparticular has the most significant contribution of nonlinearity in a Class D stage. A small amount of deadtime in the tens of nano-seconds can easily generate more than 1% of THD (Total Harmonic Distortion). Accurate switching timing is always a primaryconcern.

Sau y ta s xt n nh hng ca thi gian ngt n tnh phi tuyn.Let us take a look at how the dead-time affects nonlinearity.

Hnh 8: Mo iu ha v thi gian ngtFig 8: THD and Dead-time

Trn c s dng sng li ra theo tn hiu li vo, hot ng ca tng ra lp D c th c phn thnh3 vng khc nhau. Trong 3 vng ny, dng sng li ra i theo cc thm khc nhau v pha in p cao vv pha in p thp.

The operation mode in a Class D output stage can be categorized into three different regions based on how the outputwaveform follows the input timing. In those three different operation regions, the output waveform follows different edges in high sideand low side input signals.

Ta xt n vng hot ng th nht, dng ra chy t tng khuch i lp D ti ti, khi dngny ln hn dng gn trong cun cm. Do t trc, pha trn ngt v pha di m, li ra c iukhin bi bn k m ca tn hiu li vo. Tc ng ny l hon ton t ng do dng o mch t phncun cm gii iu ch khng ph thuc vo thi gian xut hin tn hiu m ca mch pha di. Do thi gian xut hin tn hiu trong dng sng li ra khng b nh hng bi thi gian ngt chn vo snxung m ca (mch) pha di m lun lun i theo thi gian xut hin tn hiu li vo ca (mch) phatrn. V vy, dng sng iu ch rng xung ch b ngn li mt khong bng khong thi gian ngtchn vo tn hiu ca ca pha trn, dn n h s khuch i in p b gim i cht t (as expectedfrom the input duty cycle)

Lets examine the first operating region where the output current flows from the Class D stage to the load when the amount ofthe current is larger than the inductor ripple current. At the instant of high side turn-off and prior to low side turn-on, the output nodeis driven to the negative DC bus. This action is automatically caused by the commutation current from the demodulation inductor,regardless of low side turn-on timing. Therefore the timing in the output waveform is not influenced by the dead-time inserted into theturn-on edge of low side, and always follows the high side input timing. Consequently, the PWM waveform is shortened only by thedead-time inserted into the high side gate signal, resulting in slightly lower voltage gain as expected from the input duty cycle.

Tnh trng tng t cng xy ra vi bn k m khi dng ra chy t ti vo tng khuch i lp D.Dng ny cng ln hn dng gn trong cun cm. Trong trng hp ny, thi gian xut hin tn hiu cadng sng li ra khng b nh hng bi thi gian ngt chn vo sn xung m ca (mch) pha trn vlun lun di theo thi gian xut hin tn hiu ca li vo (mch) pha di. V vy, dng sng iu bin rng xung ch b ngn li mt khong bng thi gian ngt chn vo tn hiu ca ca pha di.

A similar situation happens to the negative operation region where the output current flows from the load to the Class D stage.The amount of the current is larger than the inductor ripple current. In this case, the timing in the output waveform is not influencedby the dead-time inserted into the turn-on edge of the high side, and always follows the low side input timing. Consequently, thePWM waveform is shortened only by the dead-time inserted into the low side gate signal.


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Cn c mt vng gia hai vng hot ng va m t trn y, thi gian xut hin tn hiu li raph thuc vo thi gian ngt. Khi m dng in li ra nh hn dng gn trong cun cm, thi gian xuthin tn hiu li ra i theo sn ngt ca tng tn hiu li vo, trong vng ny, vic m (FET) c thchin bi chuyn mch in p mc zero (ZVS -Zero Voltage Switching). V vy, trong vng gia tn hiukhng b mo.

There is a region between the two operation modes described earlier where the output timing is independent of the dead-time.When the output current is smaller than the inductor ripple current, the output timing follows the turn-off edge of each input because,

in this region, turnon is made by ZVS (Zero Voltage Switching) operation. Hence, there is no distortion in this middle region.Do dng li ra thay i theo tn hiu m tn li vo, tng khuch i lp D thay i vng hot ngca n m h s khuch i ca tng vng c khc nhau cht t. Do trong 1 chu k ca tn hiu m tn 3vng c h s khuch i khc nhau nn dng sng li ra s b mo.

As the output current varies according to the audio input signal, the Class D stage changes its operation regions, which eachhave a slightly different gain. The output waveform will be distorted by these three different gain regions in a cycle of the audiosignal.

Hnh 8 cho thy thi gian ngt nh hng ng k nh th no n mo iu ha THD. Thi gianngt 40ns gy nn mo THD = 2%. Nu thi gian ngt gim xung cn 15ns, n ch cn 0,2%. iu ch trng n vai tr ca s chuyn mch lin tc gia pha cao v pha thp cho tuyn tnh tt hn.

Fig. 8 shows how significantly dead time affects THD performance. A 40nS dead time can create 2% THD. This can beimproved to 0.2% by tightening the dead time down to 15nS. This punctuates nhn mnh the significance of seamless high side andlow side switching for better linearity.

Php o hot ng ca m thanhAudio Performance Measurement

Thit b o m thanh cn c mt b lc AES17 nh Audio Precision AP2. Tuy nhin ta c th s dngmt h phn tch m thanh c in nh HP8903B c dng cng vi mt b tin lc thng thp thchhp. iu quan trng cn lu y l tn hiu li ra ca b khuch i lp D vn cn cha sng mangc tn s chuyn mch gy nn sai lch m nhng my phn tch c th khng nhy pht hinc nhng tn hiu trong b khuch i lp D.

Audio measuring equipment with an AES17 brick wall filter, such as Audio Precision AP2, are necessary. However a classicaudio analyzer like the HP8903B can be used with appropriate pre-stage low pass filter is applied. The important consideration hereis that the output signal of a Class D amplifier still contains substantial amount of switching frequency carrier on its waveform, whichcauses a wrong reading, and those analyzers might not be immune enough to the carrier leak from a Class D amplifier.

Trn hnh 9 l mt v d v b lc.Fig. 9 shows an example of a filter.

Hnh 9: V d v b lc li ra


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Hnh 10: Shoot-through preventionTuy vy, trong sn xut i tr th mt thi gian ngt ngn li c th gy nguy him. Bi v c hai

MOSFET pha cao v pha thp c m ng thi, ngun DC c th b cc MOSFET lm cho ngnmch. Dng xuyn qua s cc ln v ph hng linh kin. Cn lu rng thi gian ngt hiu dng c thl khc nhau i vi tng linh kin mt v vi nhit ph hng linh kin .

However, a narrow dead-time can be very risky in mass production. Because once both high and low side MOSFETs are turnedon simultaneously, the DC bus voltage will be short circuited by the MOSFETs. A huge amount of shoot-through current starts toflow, which will result in device destruction. It should be noticed that the effective deadtime can be vary from unit to unit variation ofcomponent values and its die temperature.

Hnh 10 cho thy mi lin h gia thi gian ngt v lng in tch xuyn qua linh kin. iu ht scquan trng trong thc tin thit k b khuch i lp D l phi m bo rng thi gian ngt lun lun

dng m khng bao gi m bo v cc MOSFET trnh khi iu kin pht sinh dng xuyn.Fig. 10 shows the relationship between the length of the dead time and the amount of shoot-through charge. It is extremelyimportant for a reliable design of a Class D amplifier to ensure that the dead-time is always positive and never negative to preventMOSFETs from entering the shoot through condition.

Fig 11: Power Supply Pumping


10/10

Mt nguyn nhn khc lm gim cht lng ca khuch i lp D l s bm ngun m ta c th thyc khi mt b khuch i na cu a ln ti mt tn hiu tn s thp. khuch i ca tng khuchi lp D l t l thun vi in p bus, do thng ging bus gy nn mo. Do nng lng chy 2 chiuqua tng chuyn mch lp D, sau mi chu k tng khuch i tr nng lng li cho ngun cung cp.Nng lng ny chnh l nng lng tn tr trong cc cun cm trong b lc thng thp li ra. Thngthng ngun cung cp khng th hp th c nng lng t ti quay v. Do nng lng quay vc bm ln ngun v lm cho chnh tn hiu vo b thng ging.

Trong m hnh ton cu th khng xy ra hin tung bm bus bi v nng lng bm t nhnh nys c tiu th nhnh i din.

Fig 12: EMI ConsiderationsCng nh trong cc ng dng chuyn mch khc, nhiu in t (EMI - Electro-Magnetic Interference)

trong thit k b khuch i lp D l mt vn kh khn. Mt trong cc ngun nhiu chnh l dng htti chy trong MOSFET tng t nh dng xuyn.

EMI (Electro-Magnetic Interference) in Class D amplifier design is troublesome like in other switching applications. One of themajor sources of EMI comes from the reverse recovery charge of the MOSFET body diode flowing from the top rail to the bottom,similar to the shoot-through current.

Trong thi gian ngt c chn vo trnh dng xuyn, dng cm ng b lc thng thp li ra sm thng diode. Trong pha tip theo, khi kt thc thi gian ngt, nhnh MOSFET pha cn li bt u m

th diode vn trng thi dn cho n khi cc ht ti thiu s cn li c x ht. Dng ny ngc vidng in hi phc c dng mt nh nhn v gy nn nhiu lon t thnh phn cm ng trong mch inv ton khi. Do , khi thit k mch in ta phi trnh nhng ng gp to gc nhn gim thiu nhiuin t

During the dead-time inserted to prevent shoot through current, the inductor current in the output LPF turns on the body diode.In the next phase when the other side of the MOSFET starts to turn on at the end of the dead-time, the body diode stays in aconducting state unless the stored minority carrier is fully discharged . This reverse recovery current tends to have a sharp spikyshape and leads to unwanted ringing from stray inductances in PCB traces and the package. Therefore, PCB layout is crucial forboth ruggedness of the design and reduction of EMI.

Kt lunConclusionHin nay, nu chn lc cn thn cc linh kin ch cht v thit k mch in tt, trnh c cc yu t

k sinh th cc b khuch i lp D t c hon thin tng ng cc b khuch i lp ABthng thng.

S pht trin lin tc ca linh kin bn dn cho php tng trng kh nng s dng khuch i lp Dnh c hiu sut cao, mt cng sut ln v cht lng m thanh cao hn

Highly efficient Class D amplifiers now provide similar performances to conventional Class AB amplifier if key components arecarefully selected and the layout takes into account the subtle, yet significant impact of parasitic components.

Constant innovations in semiconductor technologies are increasing the use of Class D amplifiersusage due to improvements in higher efficiency, increased power density and better audio performance.

cĂn bẢn vỀ khuẾch ĐẠi Âm thanh lỚp d.doc

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