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CASE STUDY OF A MULTYCYCLE DATAPATH

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Page 1: CASE STUDY OF A MULTYCYCLE DATAPATH. Alternative Multiple Cycle Datapath (In Textbook) Minimizes Hardware: 1 memory, 1 ALU Ideal Memory Din Address 32

CASE STUDY OF A MULTYCYCLE DATAPATH

Page 2: CASE STUDY OF A MULTYCYCLE DATAPATH. Alternative Multiple Cycle Datapath (In Textbook) Minimizes Hardware: 1 memory, 1 ALU Ideal Memory Din Address 32

Alternative Multiple Cycle Datapath (In Textbook)• Minimizes Hardware: 1 memory, 1 ALU

IdealMemory

Din

Address

32

32

32Dout

MemWr32

AL

U

3232

ALUOp

ALUControl

32

IRWr

Instru

ction R

eg

32

Reg File

Ra

Rw

busW

Rb5

5

32busA

32busB

RegWr

Rs

Rt

Mu

x

0

1

Rt

Rd

PCWr

ALUSrcA

Mux 01

RegDst

Mu

x

0

1

32

PC

MemtoReg

Extend

Mu

x

0

132

0

123

4

16Imm 32

ALUSrcB

Mu

x1

0

32

Zero

ZeroPCWrCond PCSrc

32

IorD

Mem

Data R

eg

AL

U O

ut

B

A

<< 2

MemRd

PC

Page 3: CASE STUDY OF A MULTYCYCLE DATAPATH. Alternative Multiple Cycle Datapath (In Textbook) Minimizes Hardware: 1 memory, 1 ALU Ideal Memory Din Address 32

State Diagram: operations for Each CycleState Diagram: operations for Each Cycle

R-Type

IR Mem[PC]State= 00000

A R[rs]

B R[rt]

PC PC + 4

State= 00001

ALUout

A Op B

State= 01000

R[rd] ALUout

State= 01001

Go Next state= 00000

Logic Immediate

IR Mem[PC]State= 00000

A R[rs]

B R[rt]

PC PC + 4

State= 00010

ALUout

A Op ZeroExt[imm16]

State= 01010

R[rt] ALUout

State= 01011

Go Next state= 00000

Load

IR Mem[PC]State= 00000

A R[rs]

B R[rt]

PC PC + 4

State= 00011

ALUout

A Op

SignExt[imm16]

State= 01100

MDR ALUout

State= 01101

R[rt] MDR

State= 01110

Go Next state= 00000

Store

IR Mem[PC]State= 00000

A R[rs]

B R[rt]

PC PC + 4

State= 00100

ALUout

A Op

SignExt[imm16]

State= 01111

Mem[R]ALUout

State= 010000

Go Next state= 00000

Cond-Branch

IR Mem[PC]State= 00000

A R[rs], B

R[rt], Z[R[rs]-R[rt]]

PC PC + 4

State= 00101

PC (PC + 4) +

(Z=1)

(SignExt(imm16) x4)

State= 010001

Go Next state= 00000

IF

ID

EX/M

WB

Branch

IR Mem[PC]State=00000

PC [PC + 4]28-31 ,

(IMM-26)26]

State= 00110

Go Next State 00000

Page 4: CASE STUDY OF A MULTYCYCLE DATAPATH. Alternative Multiple Cycle Datapath (In Textbook) Minimizes Hardware: 1 memory, 1 ALU Ideal Memory Din Address 32

Current Op field Z Next IR PC Ops Exec Mem Write-BackState A B Ex Sr ALU S R W

M M-R Wr Dst

R

I

LW

SW

BEQ

IF

ID

Page 5: CASE STUDY OF A MULTYCYCLE DATAPATH. Alternative Multiple Cycle Datapath (In Textbook) Minimizes Hardware: 1 memory, 1 ALU Ideal Memory Din Address 32

Current Op field Z Next IR PC Ops Exec Mem Write-BackState A B Ex Sr ALU S R W

M M-R Wr Dst00000 XXXX ? 00001 100001 R-type x 01000 1 100010 I-type x 01010 1 100011 LW x 01100 1 100100 SW x 01111 1 100101 BEQ x 00111 1 100110 Jump x 00000 1 100111 xxxxxx x 00000 1 1

01000 xxxxxx x 01001 0 1 fun 101001 xxxxxx x 00000 1 0 0 1 101010 xxxxxx x 01011 0 0 or 101011 xxxxxx x 00000 1 0 0 1 001100 xxxxxx x 01101 1 0 add 101101 xxxxxx x 01110 1 0 101110 xxxxxx x 00000 1 0 1 1 001111 xxxxxx x 10000 1 0 add 110000 xxxxxx x 00000 1 0 0 1

R

I

LW

SW

BEQ

IF

ID


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