September 2008

Universidad Politécnica de Madrid

José A. Cobos, Pedro AlouCentro de Electrónica Industrial (CEI)

www.cei.upm.es

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Outline

MotivationCout, Current & voltage steps

Optimal time controlAnalog implementations

V2 , hysteresisProposed control implementation

Limitations of the proposed controlESL, OpAmp bandwidthCout tolerancesVariable frequency. Freq loop

Experimental resultsSummary

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Transient Response 5.5VIN/3.3VOUT,0-6A, 10A/uS.

CIN = 50uF COUT = 50uF

EN5365QI

Control

L vo

Vin

5MHz Integrated Converter

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Bandwidth limitations of Linear control

NON Linear Control

Robustness at very high frequency - Noise- Parasitic influence- Plant variation

Limit Bandwidth

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iL

vo

vo

CL )·V,(V kt eq1dmin ⋅≈ 2(Constant load current during the transient)

iL

Minimum time control

tmin ?

Minimum timeLinear Simulation Results

Time (sec)

Am

plitu

de 0.5

1

1.5

2

2.5

To: Y

(1)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

x 10-6

-10

0

10

20

30

40

50

To: Y

(2)

Time (µs)

ton toff

Tmin

iL (A)

Vo (V)

Linear Simulation Results

Time (sec)

Am

plitu

de 0.5

1

1.5

2

2.5

To: Y

(1)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

x 10-6

-10

0

10

20

30

40

50

To: Y

(2)

Time (µs)

ton toff

Tmin

iL (A)

Vo (V)

Vin

Minimum time control

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NON Linear Control

Optimum response for load and voltage steps

Complex implementation

Digital Solutions

Non Linear Take the system close to steady state Linear Steady state, but must not interfere (Instabilities)

Analog Solutions

Combination of Non-linear and Linear Control

Minimum time control

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V2 and VOUT Hysteretic approaches

Fast response to current steps

Two control loops:

• Fast loop: fast transients

• Slow loop: DC accuracy

Io

IL

VC

Vo

SW

Vi

Q

Q

PWM Latch

PWMComparator

IL VO IO

RC

L_+VS

_

+ _+ VREF

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Sensing output voltage ripple:noise problems

Triangular output voltage rippleneeded (ESR dominant)

Fast response to current steps

V2 and VOUT Hysteretic approaches

VC

Vo

SW

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Depending on COUT …ESR dominant Not ESR dominant

Voltage ripple provides an instantaneous measurement of

COUT current

Voltage ripple is delayed with respect to COUT current

LOAD STEP

Vout, ESR dominant

Vout, Not ESR dominant

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VOUTIL

VDRIVER

5MHz converter with 10µF ceramic Cap

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∆IoIo

ICout 0 A

ICout

Instantaneous response under current steps

iL∆Io

+-Kc*ic ref

Non Linear control: iCout Hysteretic control

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Non Linear + Linear control

Vref+-

vo

ref+-+

vout

Kc*ic ref

Regulator

ic_ref

vref

ttrack

Qc

vo

ic_ref

vref

ttrack

Qc

voVO

Kc*ic ref

Linear loop to regulate VOUT100kHz bandwidth is enough2-3µs time response for a 1V voltage step

2µs

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Equivalent RLC network + trans-impedance amplifier

Output Capacitor Current Sensor

∆VO

VS = R1·Is

Is

ICout

Cout

Output capacitor

Cs

ESL

1

2

+

-

ESRRs

R1

Output capacitor

ZCout

IS = ICout/n

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Current sensor: design goals

Objective:To design a parallel RLC networkScaled impedance magnitudeEqual phase and/or same time constants

ICout

Is

t

A

Same phases

Scaled impedance magnitude

Sensor Measurement (Is)Cout current (ICout)

ICout

Cout

ESR

ESL

IS

CS

LS

ReqLoad

ZCout Zs

n*ZCout(fSW)=Zs (fSW)

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ESL effect is given by Op Amp bandwidh

ΔBR1

LsLi ==

Where:

Rs = Sensor resistanceRi = Trans-impedance amplifier input resistanceLi = Trans-impedance amplifier input inductance 10

ΔB10

wpA w DC =

⋅<

Assuming

·is1

2

1

2

ESR

·i1

2

1

2

R1·I

ESL

1

2

1

2

1

2

Li

1

2

Ri

Cout Cs

Rs

IIN

ICout

ZCout

Output capacitor

ZsCs

Li

Ri

Rs

is

IS

wp

ADC

ΔB

w

db

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Tolerance Analysis: Influence of different ΔB

Nominal case: Simulation results

-500.00m

500.00m

0

71.00u 72.00u71.50u

TCout = Ts

ICout

IS

-500.00m

500.00m

0

71.00u 72.00u71.50u

TCout ≠ Ts

Sensor designed for 135 MHzbut ΔB is 100MHz

-500.00m

500.00m

0

71.00u 72.00u71.50u

TCout ≠ Ts

Sensor designed for 135 MHzbut ΔB is 170MHz

ICout

IS

ICout

IS

Sensor gain is affected:-15% ∆B deviation produces -

15% fSW variation

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Design specifications:Switching frequency: 5MHzCOUT resonant frequency: 1.5MHz (approx.)COUT dielectric: X7R (Thermal variation +/- 15%)System operates in inductive side

Cout

ESR

ESL

CoutMLCC

Switching Frequency

Capacitive side

Inductive side

Cout Resonant Frequency

Effect of output capacitor tolerances

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-12.40

12.46

-10.00

0

10.00

17.34u 18.27u17.50u 18.00u

AM1.I ...155.00...

If sensor is designed for inductive side, but COUT is reduced and system changes from inductive to capacitive side:

Cout actual current

Cout sensed current

Incorrect operation

Restriction: Assure by design that system always operates in the same side

Restriction to output capacitor tolerance

iCout

n⋅iS

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Worst case of fRES variation

System operates properly, remaining on inductive sideResonant frequency changes from 1.59 MHz to 2.1 MHzPhase remains unchanged

1.00m

10.00

2.00m3.00m

10.00m

20.00m30.00m

100.00m

200.00m300.00m

1.00

2.003.00

10.00k 1.00G30.00k 100.00k 300.00k 1.00Meg 3.00Meg 10.00Meg 30.00Meg 100.00Meg

5MHzNominal

case

C-25%L-25%

1.00m

10.00

2.00m3.00m

10.00m

20.00m30.00m

100.00m

200.00m300.00m

1.00

2.003.00

10.00k 1.00G30.00k 100.00k 300.00k 1.00Meg 3.00Meg 10.00Meg 30.00Meg 100.00Meg

5MHzNominal

case

C-25%L-25%

1.00u

100.00m

2.00u

10.00u20.00u

100.00u200.00u

1.00m2.00m

10.00m20.00m

10.00k 1.00G30.00k 100.00k 300.00k 1.00Meg 3.00Meg 10.00Meg 30.00Meg 100.00Meg

Nominal case

C-25%L-25%

5MHz

1.5MHzXXMHz

1.00u

100.00m

2.00u

10.00u20.00u

100.00u200.00u

1.00m2.00m

10.00m20.00m

10.00k 1.00G30.00k 100.00k 300.00k 1.00Meg 3.00Meg 10.00Meg 30.00Meg 100.00Meg

Nominal case

C-25%L-25%

5MHz

1.5MHz2.1MHz

C -25% and ESL -25% fres increases 1.32 times

“Worst” worst case of fRES variation

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Current sensor design: Experimental validation

ΔICout

ΔVs

Scaled impedances

ICout

IS

The design must regard:Tolerance of ∆B: sensor gain variationDesign restriction: fRES<fSW

Internal stability of the Op-Amp

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Limitation: frequency is not constant

Restrictions: Vin and Vout rangeOutput capacitor tolerancesCurrent sensor tolerances

ICout

vovout

Vin=5V2.7V - 5.5V

Vout=1V1V - 2VLO

AD

100 nH

ICoutH

HystereticBand

Vin rangeand

Vout range

fSW = 5 MHz7.8MHz +59 % 5MHz3.2MHz -35 %

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Frequency loop: Proposed solution

LOAD

+ - Vref- +-

Vout

sKi

1s·C·RKe

+Kc*icref

FrequencyDividerCounter

Frequency/VoltageConverter

fsw

VCR(Voltage

ControlledResistor)

FrequencyLoop

Regulator-+Vfref

V(f)

FD

sw

kf

HystereticBandAdjustment

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VOUT

VREF

1.5V

2.5V

IL

VDRIVER

1.5V

2 μs

2 μs

Experimental results of the whole system:Voltage step

-Very fast response!-Close to Minimum Control Strategy

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Experimental results of the whole system:frequency loop

VOUT

VREF

1.5V

2.5V

Verror (Hysteretic band adjustment) VDRIVER

1.5V340 mV

920 mV920 mV

Frequency loop adjusts the switching frequency to the 5MHz nominal value

4 s 4 s

Voltage Steps

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Conclusions

Hysteretic control of the output capacitor currentVery simple control strategyVery fast dynamic response, close to Minimum Time StrategyReduction of output capacitors (5x)

Based on measuring capacitor current: LimitationsAlways in the same side: Inductive or capacitiveCapacitance tolerances and Op Amp bandwidth must be regarded in the designVariable frequency, corrected by the frequency loopNot direct application to Multiphase

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Minimum time

[1] Z. Zhao, A. Prodic, "Continuous-Time Digital Controller for High-Frequency DC-DCConverters", in IEEE Transactions on Power Electronics, vol. 23, pp. 564-573, March 2008.

[2] Costabeber, A.; Corradini, L.; Mattavelli, P.; Saggini, S., “Time optimal, parameters-insensitive digital controller for DC-DC buck converters”, in Proc. Conf. PESC’08.

[3] Biel, D.; Martinez, L.; Tenor, J.; Jammes, B.; Marpinard, J.C., “Optimum dynamicperformance of a buck converter”, in Proc. IEEE ISCAS’96.

Look-up-table

[4] Yousefzadeh, V. Babazadeh, A. Ramachandran, B. Alarcon, E. Pao, L. Maksimovic, D., “Proximate Time-Optimal Digital Control for Synchronous Buck DC–DC Converters”, in IEEE Transactions on Power Electronics, vol. 23, pp. 2018 - 2026, July 2008.

[5] Yousefzadeh, V. Choudhury, S., “Nonlinear digital PID controller for DC-DC converters”, in Proceedings of the IEEE Applied Power Electronics Conference APEC’08.

[6] Haitao Hu, Yousefzadeh, V., Maksimovic, D., “Nonlinear Control for Improved Dynamic Response of Digitally Controlled DC-DC Converters”, in Proc. Conf. PESC’06, June 2006.

DIGITAL CONTROL

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Minimum time

[7] Meyer, E.; Zhang, Z.; Liu, Y.-F., “An Optimal Control Method for Buck ConvertersUsing a PracticalCapacitor Charge Balance Technique”, in IEEE Trans. Power Electron., vol. 23, Jully 2008.

V2 and Vout hysteretic controls

[8] D. Goder and W. R. Pelletier, “V2 architecture provides ultra-fast transient response in switchmode power supplies”, in Proceedings of HFPC Power Conversion 1996

[9] K. S. Leung and H. S. Chung, “Dynamic hysteresis band control of the buck converter with fasttransient response,” IEEE Trans. Circuits Syst., vol. 52, no. 7, Jul. 2005.

[10] Schuellein, G., “Current sharing of redundant synchronous buck regulators powering highperformance microprocessors using the V2 control method”, in Proceedings of the IEEE AppliedPower Electronics Conference APEC’98.

[11] Qu S., “Modeling and Design Considerations of V2 Controlled Buck Regulator”, in Proceedings ofthe IEEE Applied Power Electronics Conference APEC’01.

[12] W. Huang, “A New Control for Multi-phase Buck Converter with Fast Transient Response”, inProceedings of the IEEE Applied Power Electronics Conference APEC’01.

ANALOG CONTROL