ch11 interrupt

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INPUT/OUTPUT ORGANIZATION INTERRUPTS

CS147Summer 2001

Professor: Sin-Min LeePresented by: Jing Chen


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Transferring Data Between the CPU and I/O DeviceTypes of Interrupts

Processing InterruptsInterrupts Hardware and PriorityImplementing Interrupts Inside the CPU

Topics Covered


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What is Interrupts ?

Interrupts is a mechanism for alleviating the delaycaused by this uncertainty and for maximizing

system performance.


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Transferring DataBetween the CPU and I/O Device

Polling :One method used in small system to alleviate the problem of

I/O devices with variable delays.In polling, the CPU sends a request to transfer data to an I/Odevice. The I/O device processes the request and sets a device-ready signal when it is ready to transfer data. The CPU reads inthis signal via another I/O address and checks the value. If thesignal is set, it performs the data transfer. If not, it loops back,continually reading the value of the device ready signal.


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(continue)

Wait States: When wait states are used, the processor requests data from an

I/O device, which then asserts a wait signal that is sent to theCPU via the control bus. As long as the signal is asserted, theCPU stays in a wait states, still outputting the address of the I/Odevice and the value of the control signal needed to access thedevice, but not doing anything else .The I/O device continues toassert this wait signal until it is ready to send or receive data.Once it is ready, the I/O device de- asserts its wait signal andthe CPU completes the data transfer.


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(continue)

wait states simplifies the job of the programmer. Unlike polling , we need no additional code to accommodate the

variability of the timing of the I/O device; like polling , theCPU does not perform any useful work while waiting for theI/O device to become ready to transfer data. To make use of thiswasted CPU time, interrupts are developed.


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(continue)

Interrupts Unlike polling or wait states, they do not waste time waiting for

the I/O device to become ready.--When interrupts are used with I/O devices, the CPU may output

a request to the I/O device and, instead of polling the device orentering a wait state, the CPU then continues executinginstructions, performing useful work.

--When the device is ready to transfer data, it sends an interruptsrequest to the CPU; this is done via a dedicated signal on thecontrol bus.

--The CPU then acknowledges the interrupt, typically byasserting an interrupt acknowledge signal, and completes the

data transfer.


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Types of Interrupts

External interruptsInternal interruptsSoftware interrupts


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External Interrupts

External interrupts : are used by the CPU to interact withinput/output devices.

External interrupts improve system performance by allowingthe CPU to execute instructions, instead of just waiting for theI/O device, while still performing the required data transfers.


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Internal Interrupts

Internal interrupts : occur entirely within the CPU; noinput/output devices play any role in these interrupts.

Internal interrupts could be used to allocate CPU time todifferent tasks in a multitasking operating system. Thisinterrupts can also be used to handle exceptions that occurduring the execution of valid instructions .


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Software Interrupts

Software interrupts : are generated by specific interruptinstructions in the CPUs instruction set.


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Processing Interrupts

Who services the interrupt?An interrupt triggers a sequence of events to occurwithin the computer system. These events

acknowledge the interrupt and perform the actionsnecessary to service the interrupt. These events onlyoccur if the interrupt is enabled.Interrupt is also serviced by software which is

written by the user, is called the handler, essentially asubroutine.


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Sequence of Events

(1)

Do nothing (until the current instruction has beenexecuted)

If an execute routine is interrupted part way through, we wouldhave to save the contents of many of the internal registers of theCPU, as well as the state information within the control unit. Incontrast, it is not necessary to save this information if theexecute routine has been completed.


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Sequence of Events

(2)

Get the Address of the Handler Routine(Vectored interrupts only)

Vectored interrupts supply the CPU with information, theinterrupt vector, which is used to generate the address of thehandler routine for that interrupt.Vectored interrupts are useful for CPUs that receive interruptrequests from several devices via the same control line.


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Sequence of Events

(3)

Invoke the handler RoutineWhen the CPU accesses the handler routine, it pushes the

current value of the program counter into the stack and loadsthe address of the handler routine into the program counter. Thehandler routine then performs its tasks. When it is finished, itreturns to the correct location by popping the value of theprogram counter off the stack.


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Interrupt Hardware and Priority

Three hardware samples for interrupts:

Hardware and Timing of a non-vectored interrupt for a singledevice.Hardware and Timing of a vectored interrupt for a singledevice.Hardware of multiple non-vectored interrupts


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(a)

(b)

(a) Hardware of a non-vectored interrupt for a single device An external device sent an interrupt to the CPU by asserting its interrupt

request (IRS) signal. When the CPU is ready to process the interrupt request,it assert the its interrupt acknowledge signal (IACK), thus informing the I/Odevice that is ready to proceed.

(b) Timing of a non-vectored interrupt for a single deviceThe device set the IRQ low, which cause the CPU set the IACK low. Asthe handler routine proceeds, it transfers data between the CPU and theinterrupting device.

CPU

IRQ

IACK

Data

Device

valid

IRQ

IACK

Data

Interrupt Request

Interrupt Acknowledge

Data bus


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(a) Hardware of a vectored interrupt for a single deviceA vector interrupt is more complex. After acknowledge the interrupt,

the CPU must input an interrupt vector from the device and call aninterrupt service routine(handler); the address of this routine is afunction of the vector.(b) Timing of a vectored interrupt for a single device

CPU

IRQ

IACK

Data

Device

valid

IRQ

IACK

Data(b)

Interrupt Request


Interrupt Vector

(a)


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CPU

IRQ 0IACK 0

IRQ 1IACK 1

IRQ nIACK n

Data

Device #0

Device #1

Device #n

Hardware for multiple non-vectored interrupts In addition to enabling and disabling interrupts, we must also considerthe priority of the interrupts. In general, the second interrupt is processedif its priority is higher than that of the interrupt currently being processed.

If not, it remains pending until the current handler routine is complete.


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Two methods used for prioritizingmultiple interrupts

Daisy Chaining

Parallel Priority


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Daisy Chaining :The interrupt request signals from the devices are wire-ORedtogether. When the CPU receives an active IRQ input, it cannot knowwhich device generated the interrupt request. It sends out an

acknowledge signal and leaves it to the devices to work that outamong themselves.

CPU

IACKinIRQ Device #n D

IACKout

IRQ Device#n-1D

IRQ Device#0 D

IACKin

IACKout

IACKin

IACKout

IACK

IRQ

Data


Interrupt Request

Vector


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Device is blocked from from

interrupting by a device withhigher priority(device maynot may not be issuing aninterrupt request

00

Invalid state10

Device interrupts CPU01

Device has priority to

interrupt but does not11

StateIACKoutIACKin

Possible values of IACKin and IACKout and their statesThe invalid state (IACKin = 0 and IACKout = 1) is shownto account for all possible value of IACKin and IACKout,

but a device should never be in this state.


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CPU

Priority

encoderIRQ Device #1

IRQ Device #n

IRQ

Data

IACK

IRQ Device #00

1

n

Interrupt request

Vector


Implementing priority interrupts in parallel The IRQ input to the CPU ids generated as in the daisy chain configuration, using awired-OR of the IRQ signals from the devices. Note that buffers are needed toprevent the signals from the values input to priority encoder. Unlike daisy chaining,

however, the IACK signal simply enables a priority device requesting an interrupt.This value is placed on the data bus as the interrupt vector and is read in by theCPU, which then proceeds as before.


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The most difficult part of handling the interrupt isrecognizing it and accessing the states to process the

interrupt. This is done every execute cycle, and couldbe done in one or two ways.

1. Using separate FETCH1 and INT1 states

2. Modifying FETCH1 to support interrupts


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1. Using separate FETCH1 and INT1 statesThe branches that go to state FETCH1 are broken into twobranches. If interrupts are enabled (IE=1) and an interrupt ispending (IP=1), these states branch to the beginning of theinterrupt handler routine, state INT1, rather than to FETCH1.If either the IE or IP is 0, no interrupt is processed and theCPU proceeds to FETCH1 to continue processinginstructions.

executeroutines FETCH1

executeroutines

IEVIP

IE^IP

FETCH1

INT1


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2.Modifying FETCH1 to support interruptsThe micro-operations associated with the state can bemodified.State FETCH1 would consist of two sets of micro-operations.The CPU could branch to either FETCH2 or INT2.

FETCH 1 FETCH 2 ModifiedFETCH

INT 2

IEVIP

IE^IP

FETCH 2


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How to Access the Interrupt Handler?

1. CPU pushes the return address on to the stack

2. Reads in the interrupt vector

3.Jumps to the address corresponding to this vector,1111(vector) 0000.


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