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Decoder Memory Array2n words X m bits
m output lines
n inputlines
ROM
.
.
.
.
.
.
Figure 3-1 Basic ROM Structure
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CK
D 1
CK
D 3
CK
D 2
Clock
Q1+
Q2+
Q3+
ROM
16 Words
X 4 Bits
Q1
Q2
Q 3
X Z
Figure 3-2
Realization of a Mealy Sequential Network with a ROM
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Table 3-1 ROM Truth Table
4 4 4 ; 4
4
4
=
4&4&4&
444 ;
[[[
[[[ [[[
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Figure 3-3 ROM Realization of Figure 1-17
library BITLIB;use BITLIB.bit_pack.all;
entity ROM1_2 isport(X,CLK: in bit;
Z: out bit);end ROM1_2;
architecture ROM1 of ROM1_2 issignal Q, Qplus: bit_vector(1 to 3) := "000";type ROM is array (0 to 15) of bit_vector(3 downto 0);constant FSM_ROM: ROM :=
("1001","1010","0000","0000","0001","0000","0000","0001","1111","1100","1100","1101","0111","0100","0110","0111");
beginprocess(Q,X) -- determines the next state and outputvariable ROMValue: bit_vector(3 downto 0);begin
ROMValue := FSM_ROM(vec2int(Q & X)); -- read ROM outputQplus <= ROMValue(3 downto 1);
Z <= ROMValue(0);end process;
process(CLK)begin
if CLK='1' then Q <= Qplus; end if ; -- update state registerend process;
end ROM1;
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Figure 3-4 Programmable Logic Array Stru
.
ANDArray
ORArray
n input
lines
PLA
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+V +V +V +V
+V
+V
+V
+V
+V
A B C
A' B' C'A'B'
AC'
B
BC'
AC
F0 F1 F2 F3
Inputs
Outputs
Figure 3-5 PLA with 3 input, 5 Product Terms, and 4 Outputs
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A
B
A
C
F0 F0
A
B
A
C
A'B'
AC'
+V
X1 X2
Z ZX1X2
Figure 3-6 nMOS NOR Gate
Figure 3-7 Conversion for NOR-NOR to AND-OR
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Figure 3-8 AND-OR Array Equivalent to Figure 3-5
Table 3-2 PLA Table for Figure 3-5
Inputs Outputs
Product A B C F0 F1 F2 F3
A'B' 0 0 – 1 0 1 0
AC' 1 – 0 1 1 0 0
B – 1 – 0 1 0 1
BC' – 1 0 0 0 1 0
AC 1 – 1 0 0 0 1
ORA'B'
AC'
B
BC'
AC
A B C
AND
F0 F1 F3F2
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Figure 3-9 Multiple Output Karnaugh Maps
1
1 1
1
1
1
1
1
1
1
0100 11 10
01
00
11
10
abcd
1
1
1
1
1 1
1 1
1
0100 11 10
01
00
11
10
abcd
1
1
1
1
1
1
1
0100 11 10
01
00
11
10
abcd
F1 F2 F3
abd ab'c'
a'bd
a b c d F1 F2 F3
0 1 – 1 1 1 0
1 1 – 1 1 0 1
1 0 0 – 1 0 1
– 0 1 – 1 1 0
– 1 1 – 0 1 1
F1 = a'bd + abd + ab'c' + b'c
F2 = a'bd + b'c + bc
F3 = abd + ab'c' + bc
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Table 3-3 Reduced PLA Table
a b c d F1 F2 F3
0 1 – 1 1 1 0
1 1 – 1 1 0 1
1 0 0 – 1 0 1
– 0 1 – 1 1 0
– 1 1 – 0 1 1
Figure 3-10 PLA Realization of Equations
Inputsa b c d
Outputs
Word
Lines
a'bdabdab'c'b'cbc
F1 F2 F3
F1 = a'bd + abd + ab'c' + b'c
F2 = a'bd + b'c + bc
F3 = abd + ab'c' + bc
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Table 3-4 PLA Table (Based on Figures 1-17 and 1-19)
Product
Term Q1 Q2 Q3 X Q1:
Q2:
Q3:
Z
Q2' – 0 – – 1 0 0 0
Q1 1 – – – 0 1 0 0
Q1Q2Q3 1 1 1 – 0 0 1 0
Q1Q3'X' 1 – 0 0 0 0 1 0
Q1'Q2'X 0 0 – 1 0 0 1 0
Q3'X' – – 0 0 0 0 0 1Q3X – – 1 1 0 0 0 1
Q1: = Q2'
Q2: = Q1
Q3: = Q1Q2 Q3 + X'Q1Q3' + XQ1'Q2'
Z = X'Q3' + XQ3
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I1
I2
Output
F1
F4F5
F8
I1 I2' + I1' I2
I2
I1
(a) Unprogrammed
(b) Programmed
Figure 3-12 Combinational PAL Segment
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D Q
Q'Inverting3-StateOutputBuffer
Q'
ENClock
Q'
Q
A
B
A A B B Q Q' ' '
Programmable AND Array
Figure 3-13 Segment of a Sequential PAL
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19 I/O 8
2I1
0
7
18 I/O 7
3I2
8
15
17 O6
Q
QD
4I3
16
23
16 O5
Q
QD
5I4
24
31
0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 3120 VCC1CLK
Q 1
Q 2
Z
X
Figure 3-14a Logic Diagram for 16R4 PAL
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13 I/O 2
8I7
48
55
12 I/O 1
9I8
56
63
5I4
15 O4
Q
QD
6I5
32
39
14 O3
Q
QD
7I6
40
47
11 OE
10GND 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31
Q 3
Figure 3-14b Logic Diagram for 16R4 PAL
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OutputLogic
MacroCell
I/O1
OutputLogic
MacroCell
I/O2
OutputLogic
MacroCell
I/O3
OutputLogic
MacroCell
I/O4
OutputLogic
Macro
Cell
I/O5
OutputLogic
Macro
Cell
I/O6
OutputLogic
Macro
Cell
I/O7
OutputLogic
Macro
Cell
I/O8
OutputLogic
Macro
Cell
I/O9
OutputLogic
MacroCell
I/O0
10 12 14 16 16 14 12 10 88
Programmable AND Array
(44 x 132)
Reset
1
CLK/I0
Preset
11
I1 I11 __
Figure 3-15 Block Diagram for 22V10
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Table 3-5 Characteristics of Simple CMOS PLD's
Type No. No. of inputs I/O Macrocells= FFs AND gates perOR gate
PALCE16V10 8 + OE + Clk 8 8 8
PALCE20V8 14 8 8 8
PALCE22V10 12 10 10 8–16
PALCE24V10 14 10 10 8
PALCE29MA16 5 + Clk 16 16 4–12CY7C335 12+ OE + Clk 12 12 in/12 out 9–19
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D Q
Q _
CK
AR
SP
MUX0
1S1
OutputSelect
MUX
2
3
0
1 S S1 0
I/On
programmableinterconnects
(a) paths with S1 = S0 = 0
Figure 3-16a Output Macrocell
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D Q
Q_
CK
AR
SP
MUX0
1S1
Output
Select
MUX
2
3
0
1 S S1 0
I/On
(b) paths with S1 = S0= 1
Figure 3-16b Output Macrocell
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S5
GaRb
Sb'S1
GaRb
S2
GaRb
S3
GaRb
S4
GaRb
S11
RaGbSa'Sb
S10RaGb
S9
RaGb
S8
RaGb
S7
RaGb
S6
YaRb
Sb
S0
GaRb
S12
RaYb (Sa+Sb')
Sa Sb
Ga Ya Ra Gb Yb Rb
CLOCK
PAL22V10
Figure 3-17 Block Diagram of Traffic-Light Controller
Figure 3-18 State Graph for Traffic-Light Controller
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Figure 3-19 VHDL Code for Traffic-Light Controller
entity traffic_light isport (clk, Sa, Sb: in bit;
Ra, Rb, Ga, Gb, Ya, Yb: inout bit);
end traffic_light;
architecture behave of traffic_light issignal state, nextstate: integer range 0 to 12; type light is (R, Y, G);signal lightA, lightB: light; -- define signals for waveform output
beginprocess(state, Sa, Sb)begin
Ra <= '0'; Rb <= '0'; Ga <= '0'; Gb <= '0'; Ya <= '0'; Yb <= '0';
case state iswhen 0 to 4 => Ga <= '1'; Rb <= '1'; nextstate <= state+1;when 5 => Ga <= '1'; Rb <= '1'; if Sb = '1' then nextstate <= 6; end if ;when 6 => Ya <= '1'; Rb <= '1'; nextstate <= 7;when 7 to 10 => Ra <= '1'; Gb <= '1'; nextstate <= state+1;when 11 => Ra <= '1'; Gb <= '1';
if (Sa='1' or Sb='0') then nextstate <= 12; end if ;when 12 => Ra <= '1'; Yb <= '1'; nextstate <= 0;
end case;end process;process(clk)begin
if clk = '1' then state <= nextstate; end if ;
end process;lightA <= R when Ra='1' else Y when Ya='1' else G when Ga='1';lightB <= R when Rb='1' else Y when Yb='1' else G when Gb='1';
end behave;
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0 50 100 150 200 250 300
/clk
/sa
/sb
/state 0 1 2 3 4 5 6 7 8 9 10 11 12 0 1 2 3 4 5 6 7 8 9 10 11 12 0
/lightag y r g y r g
/lightb r g y r g y r
wave clk SA SB state lightA lightBforce clk 0 0,1 5 sec -repeat 10 secforce SA 1 0, 0 40, 1 170, 0 230, 1 250 secforce SB 0 0, 1 70, 0, 100, 1 120, 0 150, 1 210, 0 250, 1 270 sec
Figure 3-20 Test Results for Traffic-Light Controller
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Table 3-6 State Table for Traffic-Light Controller
SaSb
00 01 10 11 Ga Ya Ra Gb Yb Rb
S0 S1 S1 S1 S1 1 0 0 0 0 1 {Green A, Red B}
S1 S2 S2 S2 S2 1 0 0 0 0 1
S2 S3 S3 S3 S3 1 0 0 0 0 1
S3 S4 S4 S4 S4 1 0 0 0 0 1
S4 S5 S5 S5 S5 1 0 0 0 0 1
S5 S5 S6 S5 S6 1 0 0 0 0 1
S6 S7 S7 S7 S7 0 1 0 0 0 1 {Ya,Rb}S7 S8 S8 S8 S8 0 0 1 1 0 0 {Ra,Gb}
S8 S9 S9 S9 S9 0 0 1 1 0 0
S9 S10 S10 S10 S10 0 0 1 1 0 0
S10 S11 S11 S11 S11 0 0 1 1 0 0
S11 S12 S11 S12 S12 0 0 1 1 0 0
S12 S0 S0 S0 S0 0 0 1 0 1 0 {Ra,Yb}
D1 = Q1 Q2' + Q2 Q3 Q4
D2 = Q1'Q2'Q3 Q4 + Sa Q1 Q3 Q4 + Sb'Q1 Q3 Q4 + Q1'Q2 Q4' + Q1'Q2 Q3'
D3 = Q3 Q4' + Sb Q3'Q4 + Q2'Q3'Q4 + Sa'Sb Q1 Q4D4 = Sa'Sb Q1 Q3 + Q2'Q4' + Q1'Q4' + Sa Sb'Q2 Q3'Q4
Ga = Q1' Q3' + Q1'Q2' Ya = Q2Q3Q4' Ra = Q1 + Q2Q3Q4
Gb = Q1 Q2' + Q2Q3Q4 Yb = Q1 Q2 Rb = Q1'Q2' + Q1'Q4'+ Q1'Q3'
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CKQ' QD
FullAdder
cn+1bn
cn
CKQ' QD
FullAdder
ci+1bi
ci
Sn an
an
Si ai
ai
CKQ' QD
FullAdder
c3b2
S2 a2
a2
CKQ' QD
FullAdder
c2b1
c1
S1 a1
a1
AccumulatorRegister
Clk
Figure 3-21 Parallel Adder with Accumulator
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From Page 109
A2 A1 B2 B1 C1 C3 S2 S1
0 0 0 0 0 0 0 00 0 0 0 1 0 0 1
0 0 0 1 0 0 0 10 0 0 1 1 0 1 0
0 0 1 0 0 0 1 0
– – – – – – – –
1 1 0 1 0 1 0 01 1 0 1 1 1 0 1
1 1 1 0 0 1 0 11 1 1 0 1 1 1 0
1 1 1 1 0 1 1 0
1 1 1 1 1 1 1 1
C3 = B1 B2 C1 + A1 B2 C1 + A1 B2 B1 + A2 B1 C1 +
A2 B2+ A1 A2 C1 + A1 A2 B1+ A1 A2 C1 + A1 A2 B1
S2 = (A2'B1 B2'C1 + A1'A2'B1'B2 + A1'A2'B2 C1'+
A1 A2'B2'C1+ A1 A2'B1 B2'+ A2'B1'B2 C1'+
A1'A2 B1'B2'+ A1'A2 B2'C1'+ A2 B1 B2 C1 +
A2 B1'B2'C1' + A1 A2 B2 C1 + A1 A2 B1 B2)Ad +
Ad'A2
S1 = (A1'B1'C1 + A1'B1 C1' + A1 B1'C1' + A1 B1 C1)Ad +
Ad'A1
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Keypad
Scanner,
Debouncer,
& Decoder
1 2 3
4 5 6
7 8 9
0* #V
N
C2 C1 C0
R0
R1
R2
R3
clock
Figure 3-22 Block Diagram for Keypad Scanner
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R 0R 1R 2R 3
CK
D A QA
K
CK
D B QB
CLK
Kd
QA
Q 1'
ContactClosure
Clock
QA
t1 t2
1
00
QB
t3
R 0R 1R 2R 3
CK
DA QAK
CK
D B QB
CLK
Kd
Figure 3-23 Debouncing and Synchronizing Circuit
(a)
(c)
(b)
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Keypad Debounce Keyscan Decoder
4
R3-0
4
3 C2-0
V NKd
K
Figure 3-24 Scanner Modules
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Figure 3-25 State Graph for Scanner
S1
C0C1C2
S5
C0C1C2
S4
C2
S0
S2
C0
S3
C1
0
Kd K' K'
K/V K/V
Kd'
11 / V
Kd'
Kd
State Assignment for Q1 Q2 Q3 Q4:
S1 ← 0111, S2 ← 0100, S3 ← 0010, S4 ← 0001, S5 ← 1111
Q1: = Q1 Kd + Q2 Q3'K + Q2'Q3 K + Q2'Q4Q2: = Q2'Q3' + K + Q4Q3: = Q3' + Q1 + Q4 Kd' + Q2'K
Q4: = Q2' + Q1 + Q3 Kd' + Q3'K
V = KQ2Q3' + KQ2'Q3 + Q2'Q4
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Table 3-7 Truth Table for Decoder
R3R2R1R0C0C1C2 N3 N2 N1 N0
0 0 0 1 1 0 0 0 0 0 10 0 0 1 0 1 0 0 0 1 0
0 0 0 1 0 0 1 0 0 1 1
0 0 1 0 1 0 0 0 1 0 0
0 0 1 0 0 1 0 0 1 0 1
0 0 1 0 0 0 1 0 1 1 0
0 1 0 0 1 0 0 0 1 1 1
0 1 0 0 0 1 0 1 0 0 0
0 1 0 0 0 0 1 1 0 0 1
1 0 0 0 1 0 0 1 0 1 0 (*)
1 0 0 0 0 1 0 0 0 0 0
1 0 0 0 0 0 1 1 0 1 1 (#)
Logic equations for decoder:N3 = R2 C0' + R3 C1'N2 = R1 + R2 C0N1 = R0 C0' + R2'C2 + R1'R0'C0N0 = R1 C1 + R1'C2 + R3'R1'C1'
KeypadScanner,Debouncer,
& Decoder
1 2 3
4 5 6
7 8 9
0* #
V
N
C2 C1 C0
R0
R1
R2
R3
clock
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Figure 3-26 VHDL Code for Scanner
entity scanner isport (R0,R1,R2,R3,CLK: in bit;
C0,C1,C2: inout bit;
N0,N1,N2,N3,V: out bit);end scanner;architecture scan1 of scanner issignal Q1,QA, K, Kd: bit;alias Q2: bit is C0; -- column outputs will be the samealias Q3: bit is C1; -- as the state variables becausealias Q4: bit is C2; -- of state assignmentbegin
K <= R0 or R1 or R2 or R3; -- this is the decoder sectionN3 <= (R2 and not C0) or (R3 and not C1); N2 <= R1 or (R2 and C0);N1 <= (R0 and not C0) or (not R2 and C2) or (not R1 and not R0 and C0);N0 <= (R1 and C1) or (not R1 and C2) or (not R3 and not R1 and not C1);V <= (Q2 and not Q3 and K) or (not Q2 and Q3 and K) or (not Q2 and Q4);process(CLK) -- process to update flip-flopsbegin
if CLK = '1' thenQ1 <= (Q1 and Kd) or (Q2 and not Q3 and K) or (not Q2 and Q3 and K)
or (not Q2 and Q4);Q2 <= (not Q2 and not Q3) or K or Q4;Q3 <= not Q3 or Q1 or (Q4 and not Kd) or (not Q2 and K);Q4 <= not Q2 or Q1 or (Q3 and not Kd) or (not Q3 and K);QA <= K or (QA and not Q1); -- first debounce flip-flopKd <= QA; -- second debounce flip-flop
end if ;end process;
end scan1;
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TEST1 SCANNER
R3-0C2-0
VN3-0
CLK
Figure 3-27 Interface for Scantest
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Figure 3-28(a) VHDL for Scantest
library BITLIB;use BITLIB.bit_pack.all;
entity scantest isend scantest;
architecture test1 of scantest iscomponent scanner
port (R0,R1,R2,R3,CLK: in bit;C0,C1,C2: inout bit;N0,N1,N2,N3,V: out bit);
end component;
type arr is array(0 to 11) of integer; -- array of keys to test
constant KARRAY:arr := (2,5,8,0,3,6,9,11,1,4,7,10);signal C0,C1,C2,V,CLK,R0,R1,R2,R3: bit; -- interface signalssignal N: bit_vector(3 downto 0);signal KN: integer; -- key number to testbegin
CLK <= not CLK after 20 ns; -- generate clock signal
-- this section emulates the keypadR0 <= '1' when (C0='1' and KN=1) or (C1='1' and KN=2) or (C2='1' and KN=3)else '0';R1 <= '1' when (C0='1' and KN=4) or (C1='1' and KN=5) or (C2='1' and KN=6)else '0';R2 <= '1' when (C0='1' and KN=7) or (C1='1' and KN=8) or (C2='1' and KN=9)else '0';R3 <= '1' when (C0='1' and KN=10) or (C1='1' and KN=0) or (C2='1' and KN=11)else '0';
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Figure 3-28(b) VHDL for Scantest
process -- this section tests scannerbegin
for i in 0 to 11 loop -- test every number in key array
KN <= KARRAY(i); -- simulates keypresswait until (V='1' and rising_edge(CLK));assert (vec2int(N) = KN) -- check if output matches
report "Numbers don't match"severity error;
KN <= 15; -- equivalent to no key pressedwait until rising_edge(CLK); -- wait for scanner to resetwait until rising_edge(CLK);
wait until rising_edge(CLK);end loop;report "Test complete.";
end process;scanner1: scanner -- connect test1 to scanner
port map(R0,R1,R2,R3,CLK,C0,C1,C2,N(0),N(1),N(2),N(3),V);end test1;