Chapter 1

Parts 2,3,4

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TABLE 1.4

TABLE 1.5

What are properties and theorems good for?

Remember our example: simplification!

How do we prove properties and theorems?

FIGURE 1.8

QUIZ: Use perfect induction to prove DeMorgan’s theorem

1.3 Deriving boolean functions from truth

tables

-using the 1s → canonical SOP

-using the (compact) sum of minterms

EoL

Individual work for Monday

Read thoroughly section 1.4.

Go lightly over the VHDL code (we’re saving it for the lab!), but make sure you understand:

• The logical function in Architecture

• The waveform diagrams

End-of-chapter 17,18,19,20,22,25.

EoL

QUIZ: End-of-chapter 1.26

Describe how to obtain the dual of a Boolean

relationship.

Find the dual of X + YZW + A

QUIZ: End-of-chapter 1.26

Describe how to obtain the dual of a Boolean

relationship.

Find the dual of X + YZW + A

QUIZ: End-of-chapter 1.26

Describe how to obtain the dual of a Boolean

relationship.

Find the dual of X + YZW + A

QUIZ: Write the canonical SOP and the sum of minterms

for the function in this truth table

But, since there are more 0s than ones, isn’t it a better idea

to design based on the 0s?

Write the dual of this statement:

Consider all the lines where the function is 1, write the

minterm for each, add up the minterms.

Q: What is the dual of a minterm? A: Use duality again!

Conclusion: The entire design process has a

dual!

• Zeroes in the truth table

• Maxterms

• Product of sums

• Bar the variables that are equal to 1

Analysis vs. Design

1.4 VHDL for simple gate functions

Yet another representation:

Hardware Description Languages (HDLs)

WAVEFORMS ARE EQUIVALENT TO TRUTH TABLES!

LISTING 1.7

Derive this from the truth table!

Individual work for Wednesday

Read thoroughly section 1.4.

Go lightly over the VHDL code (we’re saving it for the lab!), but make sure you understand:

• The logical function in Architecture

• The waveform diagrams

End-of-chapter 38, 39, 45-50.

Homework for Ch.1, due Mon, Jan 30

29, 35, 37, 41, 42, 51 through 55

The homework assignments are available on the course webpage.

EoL

QUIZ: Derive canonical SOP , compact sum of minterms,

and gate diagram for this function

1.5 More about logic gates

Active-low inputs and outputs

Logically, these symbols for an inverter are

equivalent

‘B’ is for Bubble

Gate-level DeMorgan manipulations

Gate-level DeMorgan example:

From AND-OR to NAND-NAND

QUIZ: From OR-AND to …??

QUIZ: From OR-AND to NOR-NOR

Functionally complete gates

NAND is functionally complete!

NOR is also functionally complete!

Two extra-credit problems:

1] Prove that the XOR gate (by itself) is not

functionally complete.

2] Prove that XOR together with OR is functionally

complete.

FYI: IEEE symbols

(we’re not going to use them)

Remember

Homework for Ch.1, due Mon, Jan 30

29, 35, 37, 41, 42, 51 through 55

The homework assignments are available on the course webpage.

Unused slides

FIGURE P1.18

LISTING P1.50

LISTING P1.54

FIGURE P1.73

FIGURE P1.74

FIGURE P1.75

FIGURE P1.84

FIGURE P1.85

FIGURE P1.86

FIGURE P1.87