61

CHAPTER 4

COEXISTENCE OF FAST-SCALE AND SLOW-SCALE

INSTABILITY IN POWER ELECTRONIC CONVERTERS

4.1 INTRODUCTION

In this chapter, the fast-scale and slow-scale instabilities in a PFC

uk converter under NLC control which is proved advantageous compared to

other conventional control strategies are investigated. It is found that the

fundamental periodic orbit loses its stability via period-doubling bifurcation

and later bifurcates to chaos. MATLAB/Simulink software package is used to

study the qualitative behaviour of the system under parameter variations and

the simulation results are also verified with hardware implementation. The

bifurcation phenomena related to the existence of instabilities are also

analysed through mathematical derivations. It is found that both fast and slow

scale instabilities may cause distortion in the line current and degrade the

supply power factor. The results offer useful information of parameter space

for the design and operation of the converter in the desired fundamental stable

regime.

4.2 POWER FACTOR CORRECTION UK AC-DC PRE-

REGULATOR UNDER NONLINEAR CARRIER CONTROL

Almost all DC-DC converters can be used as PFC, but the boost,

uk and Single Ended Primary Inductance Converter (SEPIC) are best suited

for the implementation of PFC due to the presence of an input inductor in

62

series with the bridge rectifier. Among these converters, the uk converter is

a widely used converter as it also has several other advantages such as good

isolation, steady state performance, current limit and short circuit protection.

The uk converter inverts the polarity of output voltage and can

simultaneously buck or boost the output voltage magnitude. The NLC control

requires only output voltage sensing and the switch current sensing. The block

diagram of PFC uk converter controlled by NLC controller is shown in

Figure 4.1(a) which has two stages: the power stage and the control stage. The

power circuit has a diode bridge rectifier, from which the rectified DC voltage

is given to a DC-DC uk converter. The uk converter comprises of two

inductors (L1, L2), two capacitors (C1, C2), a switch S, a diode D1 and a load

resistance R. Here fs is the switching frequency, Ts is the switching period and

d is the duty ratio. The control circuit controls the ON-OFF of the switch

using a Set-Reset (SR) flip-flop which is set to HIGH at every positive edge

of the clock. Its ‘reset’ is triggered when the average value of the switch

current compares equal to the carrier waveform generated which in turn

depends on the output voltage loop error. Operation of the control circuit is

illustrated using the waveforms of Figure 4.1(b). The nonlinear carrier signal

for the uk converter is generated as follows.

For the AC line current and voltage to be in phase and to have the

same wave shape, the single phase rectifier should present a resistive load to

the AC system [Erickson and Maksimovic, 2004]. Accordingly, the rectifier

input current )(tiac should be proportional to the input voltage )(tvac .

e

acac R

tvti )()( . (4.1)

)sin()( tVtv mac . (4.2)

63

(a) (b)

Figure 4.1 NLC controlled PFC uk AC-DC pre-regulator (a) Schematic diagram; (b) key operation waveforms

Re is the emulated resistance and Vm is the peak value of the input

AC voltage. Then the rectified voltage vg(t) from the diode bridge rectifier is

given by:

)sin()( tVtv mg . (4.3)

For resistor emulation, it is desired that the rectified current ig (t)

averaged over a switching period Ts is proportional to the rectified voltage

vg(t) averaged over Ts.

e

sTg

sTg R

tvti

)()( . (4.4)

64

For the uk converter operating in CCM, with Vo as the DC output voltage, the low frequency portion of the switch current is (t) is equal to the low frequency portion of the rectified current ig (t).

sTgsTs titi )()( . (4.5)

osTg V

ddtv 1)( . (4.6)

Using Equations (4.4) and (4.6), eliminating sTg ti )( in

Equation (4.5), the following relation is obtained.

ddI

RV

ddti a

e

osTs

11)( . (4.7)

e

oa R

VI (4.8)

where Ia is the actuating current for the NLC generator. For every switching

period, the SR flip-flop is reset when the average of the switch current iq(t)given by:

sT

ss

q diT

ti0

)(1)( , (4.9)

becomes equal to the carrier ic(t) which is obtained by replacing sTtd in

Equation (4.7).

,1)(s

sac T

tt

TIti sTt0

)()( tiTti csc . (4.10)

65

Equation (4.10) describes the function used for generating the

nonlinear carrier signal.

4.3 MATHEMATICAL BIFURCATION ANALYSIS OF

FAST-SCALE INSTABILITY

In PFC converters, unlike DC-DC converters where the current

reference is set constant for a fixed load, here it varies in order to achieve

UPF operation. In conventional CMC converters, the reference follows the

input voltage waveform and the situation is analogous to the case of applying

a time varying ramp compensation to DC-DC converters [Herbert et al, 2003].

In NLC uk converter, ic(t) given by Equation (4.10) is approximated to an

exponential decreasing function as in Equation (4.11) with an objective of

simple implementation.

sTt

ac eAIti.

)( , (4.11)

where A is an arbitrary gain constant that scales the amplitude of the carrier

signal and the time constant of the exponential decay is specified as a fraction

of the switching period.

4.3.1 Derivation of Poincaré Map

The discrete-time map for the current through input inductor L1

takes the following form:

gnngng vdifi ,,,1, , (4.12)

where the subscripts n and n+1 denote the values at the beginning of the nth

and (n+1)th switching cycle respectively. From the feedback equation of the

closed loop system, the duty cycle of the nth switching period dn is related to

66

ig,n and vg. Upon substitution of this expression in Equation (4.12), the desired

iterative map is obtained. The system parameters are designed to operate in

CCM and hence there exist two switching states.

1. ,snss TdnTtnT switch S turned ON.

2. ,1 ssns TntTdnT switch S turned OFF.

From the slopes of the ig waveform, the subsequent equations are

written as:

1

1,

1 LV

TdTdii o

sn

sngng and 1

,

Lv

TdiTdi g

sn

ngsng . (4.13)

Stacking up the above equations, the expression for ig,n+1 is derived

as follows:

1,1,

2L

Tdvii sng

ngng . (4.14)

Expanding Equation (4.11) using Taylor series and neglecting the

higher order terms, the carrier waveform at dnTs is simplified.

sac T

tAIti .1)( and nasnc dAITdi 1)( . (4.15)

The duty ratio of the nth switching period is found from the carrier

and switch current equations, as the SR flip flop is reset when they become

equal. The current through the switch at dnTs is the sum of the two inductor

currents ig(dnTs) and iL2(dnTs).

67

sn

Lnnag

TdidAI

Lv 1 . (4.16)

where 21

111LLL

. (4.17)

Further simplification of Equations (4.14) and (4.16) gives the

relationship between ig,n+1 and ig,n.

g

as

Lnangng

vAILf

LL

iAIii

2211

,1, . (4.18)

4.3.2 Derivation of Critical Phase Angle at which Period-doubling

Occurs

As only the inner current loop dynamics near the steady state is of

interest, a small disturbance ig,n is introduced to ig,n. The disturbance at

(n+1)th instant ig,n+1 is then given as follows:

)(2

1 2,

111, Oi

AILLfvLLv

i ngasg

gng . (4.19)

The linearised map with the characteristic multiplier or eigenvalue

is obtained by safely neglecting the O( 2) terms. Thus, the first period-

doubling occurs when = -1. For algebraic brevity, the input voltage is

expressed in terms of the phase angle , i.e. )sin()( mg Vv . The critical

angle c at which the first period-doubling occurs is then found from = -1.

m

asc V

AILf 2arcsin . (4.20)

68

4.4 SLOW-SCALE INSTABILITY BY COMPUTER

SIMULATION AND EXPERIMENTAL INVESTIGATION

PFC uk converter in NLC control mode is simulated with

MATLAB/Simulink package. A prototype is constructed in the laboratory for

experimental investigation and controlled with the proposed control strategy

using dSPACE 1104 signal processor for the same design values as used in

simulation. The output voltage and the switch current are sensed and given to

the ADC channels of dSPACE. LEM HX 20-P current transducer with

features of low insertion loss and galvanic isolation is used for sensing the

switch current. The block diagram of the hardware implementation and the

photograph of the experimental setup are shown in Figures 4.2(a) and 4.2(b).

(a) (b)

Figure 4.2 (a) Schematic diagram depicts the hardware implementation of a NLC controlled PFC uk AC-DC pre-regulator; (b) snapshot of the experimental setup

69

The uk converter is designed with the specifications, input voltage

Vac,rms = 12V, line frequency = 50 Hz, Vo= 20 V, Io= (0-2) A, Ts = 400 s,

Ig = 4.8 % of the source current, IL2 = 9.6 % of the source current,

VC1 = 4.2 % of the output voltage, V0 = 0.00125% of the output voltage and

the component values are calculated as L1 = 2mH, L2 = 1mH, C1 = 10 F,

C2 = 2000 F.

The slow-scale instability at double the line frequency is studied by

varying the load from full load to very low values. The normal and the

acceptable operating regime in PFC converters is the fundamental regime

which demonstrates the period-1 operation. At first, the operation is examined

at full load. The input current is periodic at line voltage frequency and the

output voltage ripple is periodic at double the line frequency resulting in a

desired stable period-1 operation as shown in Figures 4.3(a(i)) and 4.3(b(i)).

The source power factor is found to be 0.94. Second, as the load is reduced to

90%, a slow-scale instability occurs which manifests itself as a period-

doubling bifurcation as shown in Figures 4.3(a(ii)) and 4.3(b(ii)). The

periodicity of the output voltage ripple is doubled when compared to period-1

operation and results with a lower input power factor of 0.86. Further

decrease in the load, emanates in a chaotic regime as in Figures 4.3(a(iii)) and

4.3(b(iii)). The output voltage has random behaviour with no periodicity and

the power factor decreases to 0.63, a very low value which is not accepted in

industrial sectors. Also, the output voltage starts decreasing.

70

Time, s(a(iii))

Time, s(b(iii))

Time, s(a(ii))

Time, s(b(ii))

Time, s(a(i))

Time, s(b(i))

-22.5

-22

-21.5

-21

-20.5

0.705

-20.5

-22.50.72 0.735 0.75

-22

-21.5

-21

-22.5

-21.5

-20.5

0.608

-20.5

-22.50.633 0.658 0.683

-21.5

0.708

-19

-18

-17

-16

0.72

-17

-190.74 0.76 0.78

-18

0.8 0.82

-16

Figure 4.3 (a) Simulated waveforms of a NLC controlled PFC uk AC-DC pre-regulator showing (i) period-1 operation; (ii) period-2 limit cycle operation; (iii) chaotic operation. (b) Experimental waveforms of a NLC controlled PFC uk AC-DC pre-regulator showing (i) period-1 operation; (ii) period-2 limit cycle operation; (iii) chaotic operation

71

The phase portraits which are very useful in uncovering the subtle

periodicity are also plotted between the output capacitor voltage and the input

inductor current to compare the dynamic phenomenon in each case.

Figure 4.4(a) shows the phase plane curve for the stable case with the

presence of a single loop. Figure 4.4(b) depicts the phase plane curve for the

period-doubling case with the presence of two loops. Chaotic behaviour can

be easily identified with irregular, aperiodic, multiple loops still bounded on

the phase plane trajectory as shown in Figure 4.4(c).

Output Capacitor Voltage Vo, V(b)

Output Capacitor Voltage Vo, V(a)

Output Capacitor Voltage Vo, V(c)

-22.4

1

-1-21.9 -21.4 -20.9

0

2

-21.8

1.5

-0.5-21.4 -21 -20.6

0.5

-0.75

0.25

1.25

2

-18

1.25

-0.75-17.6 -17.2 -16.8

0.25

-16.4

2

Figure 4.4 Phase portraits of a NLC controlled PFC uk AC-DC pre-regulator showing (a) period-1 operation; (b) period-2 limit cycle operation; (c) chaotic operation

72

4.5 FAST-SCALE INSTABILITY BY COMPUTER

SIMULATION AND EXPERIMENTAL INVESTIGATION

In this section, the effects of two different parameter variations on

the total system stability in the switching timescale are analysed. The variable

parameters are the load resistance and the feedback DC gain. The input

voltage and current waveforms are in phase resulting in a power factor of 0.94

as shown in Figure 4.5. Experimental inductor current is measured using

LEM HX 20P current transducer with gain 1V = 4A. It is observed that the

fast-scale instabilities are less detrimental compared to slow-scale instabilities

from the view point of power factor.

-16

-8

0

8

16

Time, s(a)

Time, s(b)

0.09

0

-160.14

-8

0.19

8

16

vac

iac *4

Figure 4.5 Input voltage and current waveforms of a NLC controlled PFC uk AC-DC pre-regulator showing in-phase operation. (a) Simulated; (b) experimental

4.5.1 Route to Chaos in Inductor Current by Varying Load

The various stages leading to chaos are studied by varying the load

resistor. Both the simulation and real time results are compared.

73

4.5.1.1 Fundamental operation

The NLC controlled PFC uk converter, in CCM operation is

modeled and simulated using MATLAB/Simulink package. The simulated

fundamental operation for rated load is shown in Figure 4.6(a(i)).

The fundamental, stable waveform observed in hardware is also depicted in

Figure 4.6(b(i)). Experimental inductor current is measured using LEM HX

20P current transducer with gain 1V = 4A. The simulated and experimental

waveforms of inductor current shown over a half line cycle are comparable.

4.5.1.2 Period-2 operation

When the load is decreased further, the system undergoes period-

doubling bifurcation, a behaviour which repeats every two cycles as shown in

Figure 4.6(a(ii)). As this period-doubling phenomenon multiplies its

periodicity following the universal property of Fiegenbaum constant and

culminates in an aperiodic behaviour, the value of load at which this

behaviour gets started is of interest. Figure 4.6(a(ii)) shows the waveform of

inductor current over a half line cycle, with the beginning of period-doubling

near the peak of the inductor current. The period-doubling waveform is also

ascertained in hardware and is shown in Figure 4.6(b(ii)).

4.5.1.3 Chaotic operation

When the load is decreased further, the system exhibits a chaotic

behaviour. As this chaotic nature, tends to induce noise and results in

reduction of power factor, it is not preferred to operate the circuit in this

parameter space. Figure 4.6(a(iii)) shows the inductor current over a half line

cycle, with the aperiodic, chaotic nature and the chaotic waveform envisioned

in hardware is also shown in Figure 4.6(b(iii)).

74

Time, s(a(iii))

Time, s(b(iii))

Time, s(a(ii))

Time, s(b(ii))

Time, s(a(i))

Time, s(b(i))

-8

-4

0

4

8

0.7

8

-80.7025 0.705 0.7075

-4

0

4

0.71

-8

-4

0

4

8

0.7

8

-80.7025 0.705 0.7075

-4

0

4

0.71

-8

-4

0

4

8

0.7

8

-80.7025 0.705 0.7075

-4

0

4

0.71

ig *2

ig *2

ig *2

ig / 2

ig / 2

ig / 2

Figure 4.6 (a) Simulated waveforms of a NLC controlled PFC ukAC-DC pre-regulator showing (i) period-1 operation; (ii) period-2 operation; (iii) chaotic operation. (b) Experimental waveforms of a NLC controlled PFC uk AC-DC pre-regulator showing (i) period-1 operation; (ii) period-2 operation; (iii) chaotic operation

75

4.5.2 Route to Chaos in Inductor Current by Varying Feedback DC

Gain

The reduction in DC gain results in an increase in the emulated

resistance as specified in Equation (4.9). The behaviour of the converter from

period-1 to chaos as the feedback gain is reduced from 1 to 0.1 has also been

observed and the inductor current waveform traversing through the same

route as in the load variation is shown in Figures 4.7(a(i)) – 4.7(b(iii)).

Experimental inductor current is measured using LEM HX 20P current

transducer with gain 250mV = 1A. The power factor reduces from 0.94 in

period-1 operation to 0.91 in the fast-scale instability case. This reduction in

power factor is less when compared to the slow-scale instability case.

4.6 ANALYSIS OF STABILITY DOMAIN

In this section, the effect of various parameter changes in the

system stability through stability maps is studied and also the three

dimensional margin of stability curve is plotted. It is clear from the

mathematical, simulation and experimental results that the load resistance and

the feedback DC gain have a major effect on the stability of the NLC PFC

uk converter. It is inferred from the results that lighter loads are detrimental

and the system stability is lost at light loads. The system enters into fast and

slow scale instable operations if the load reduces more than 10% of the

designed value. While the stability at fast-scale is lost for all loads lesser than

10%, the slow-scale stability shows an intermittent behaviour as shown in

Figure 4.8(a). The margin of stability curve for various loads is plotted in

Figure 4.8(b).

76

Time, s(a(iii))

Time, s(b(iii))

Time, s(a(ii))

Time, s(b(ii))

Time, s(a(i))

Time, s(b(i))

0.7 0.7025 0.705 0.7075 0.71-8

-4

4

8

0.7

8

-80.7025 0.705 0.7075

-4

0

4

0.71

-8

-4

0

4

8

0.7

8

-80.7025 0.705 0.7075

-4

0

4

0.71

-8

-4

0

4

8

0.7

8

-80.7025 0.705 0.7075

-4

0

4

0.71

ig *2

ig *2

ig *2

ig / 2

ig / 2

ig / 2

Figure 4.7 (a) Simulated waveforms of a NLC controlled PFC ukAC-DC pre-regulator showing (i) period-1 operation; (ii) period-2 operation; (iii) chaotic operation. (b) Experimental waveforms of a NLC controlled PFC uk AC-DC pre-regulator showing (i) period-1 operation; (ii) period-2 operation; (iii) chaotic operation

77

(a)

Stable Regime Slow & Fast ScaleChaotic Regime

Fast-Scale Chaotic & Slow-Scale Stable

Reg ime

Load Resistance R,5

22

620 35 50

10

14

18

65 80 95 110

9.7511.5

13.25

0.55

0.65

0.75

62

0.55 8

0.8547

54.5

150.750.65

9.7511.5

13.25

(b)

Figure 4.8 NLC controlled PFC uk AC-DC pre-regulator. (a) Fast and slow scale stability regime for various loads; (b) margin of stability curve

The critical phase angle calculated using Equation (4.20) for the

nominal value of circuit parameters given in Section 4.4 and = 0.1175 is

31.3o. The sampled waveform of the input inductor current shown in

Figure 4.9 also confirms the same.

Sampled Instants

-0.5

1.5

3.5

5

0

5

25 50 75-0.5

1.5

3.5

100

Figure 4.9 Sampled input inductor current waveform of a NLC controlled PFC uk AC-DC pre-regulator with fs = 10 kHz showing period-2 operation at c = 31.3o

78

4.7 CONCLUSION

In this chapter, analytical, numerical and experimental

investigations have been carried out to show the coexistence of fast and slow

scale instabilities in a PFC uk regulator under nonlinear carrier control, as

different parameters are varied. The fast-scale instability has been identified

for variations in load and feedback gain. The critical angle at which the first

period-doubling occurs has also been found analytically. From the results, it

has been inferred that lighter loads are detrimental and the reliability of

system stability is lost at very light loads. The margin of stability curve for

various loads has also been plotted. Numerical simulation results are

presented using suitable phase portraits and time-domain waveforms. The

dynamics also has been verified using a suitable experimental setup based on

DSP. Experimental observations are found to be in good agreement with the

analytical and simulation results.