chapter 5 thermal processes
TRANSCRIPT
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Chapter 5
Thermal Processes
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Objective
• List four thermal processes
• Describe thermal process in IC fabrication
• Describe thermal oxidation process
• Explain the advantage of RTP over furnace
• Relate your job or products to the processes
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Topics
• Introduction
• Hardware
• Oxidation
• Diffusion
• Annealing
– Post-Implantation
– Alloying
– Reflow
• High Temp CVD
– Epi
– Poly
– Silicon Nitride
• RTP
– RTA
– RTP
• Future Trends
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Oxidation Mechanism
• Si + O2 SiO2
• Oxygen comes from gas
• Silicon comes from substrate
• Oxygen diffuse cross existing silicon
dioxide layer and react with silicon
• The thicker of the film, the lower of the
growth rate
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Oxide Growth Rate RegimeO
xid
e T
hic
knes
s
Oxidation Time
Linear Growth Regime
B
AX = t
Diffusion-limited Regime
X = B t
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<100> Silicon Dry Oxidation
2 4 6 8 10 12 14 16 18 20
0.2
0
0.4
0.6
0.8
1.0
1.2
Oxidation Time (hours)
Oxid
e T
hic
knes
s (m
icro
n)
1200
°C
1150
°C1100
°C1050
°C1000
°C950 °C
900 °C
<100> Silicon Dry Oxidation
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Wet (Steam) Oxidation
• Si + 2H2O SiO2 + 2H2
• At high temperature H2O is dissociated to H
and H-O
• H-O diffuses faster in SiO2 than O2
• Wet oxidation has higher growth rate than
dry oxidation.
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<100> Silicon Wet Oxidation Rate
2 4 6 8 10 12 14 16 18 20
0.5
0
1.0
1.5
2.0
2.5
3.0
Oxidation Time (hours)
Oxid
e T
hic
knes
s (m
icro
n)
1150
°C1100
°C1050
°C1000
°C950 °C
900 °C
<100> Silicon Wet Oxidation
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Oxidation Rate
• Temperature
• Chemistry, wet or dry oxidation
• Thickness
• Pressure
• Wafer orientation (<100> vs. <111>)
• Silicon dopant
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• Oxidation rate is very sensitive (exponentially related) to temperature.
• Higher temperature will have much higher oxidation rate.
• The higher of temperature is, the higher of the chemical reaction rate between oxygen and silicon is and the higher diffusion rate of oxygen in silicon dioxide is.
Oxidation Rate & Temperature
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Oxidation Rate & Wafer Orientation
• <111> surface has higher oxidation rate
than <100> surface.
• More silicon atoms on the surface.
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Wet Oxidation Rate
1 2 3 40
Oxidation Time (hours)
0.4
0.8
1.2
1.6
0.2
0.6
1.0
1.4
1.8O
xid
e T
hic
knes
s (m
icro
n)
<111> Orientation
95 °C Water
1200
°C1100
°C
1000
°C
920
°C
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• Dopant elements and concentration.
• Highly phosphorus doped silicon has higher
growth rate, less dense film and etch faster.
• Generally highly doped region has higher
grow rate than lightly doped region.
• More pronounced in the linear stage (thin
oxides) of oxidation.
Oxidation Rate & Dopant Concentration
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Oxidation: Dopants
Pile-up and Depletion Effects
•N-type dopants (P, As, Sb) have higher
solubility in Si than in SiO2, when SiO2
grow they move into silicon, it is call
pile-up or snowplow effect.
•P-type dopant (Boron) tends to go to
SiO2, it is called depletion effect.
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Depletion and Pile-up Effects
Si-SiO2 interface
SiO2
Dopan
t C
once
ntr
atio
n
Si
Si-SiO2 interface
SiO2D
opan
t C
once
ntr
atio
nSi
P-type Dopant Depletion N-type dopant Pile-up
Original Si Surface Original Si Surface
Original Distribution
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Oxidation Rate
Doped oxidation (HCl)
• HCl is used to reduce mobile ion contamination.
• Widely used for gate oxidation process.
• Growth rate can increase from 1 to 5 percent.
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Oxidation Rate
Differential Oxidation
• The thicker of the oxide film is, the slower of
the oxidation rate is.
• Oxygen need more time to diffuse cross the
existing oxide layer to react with substrate
silicon.
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Pre-oxidation Clean
• Thermally grown SiO2 is amorphous.
• Tends to cross-link to form a crystal.
• In nature, SiO2 exists as quartz and sand.
• Defects and particles can be the nucleation sites.
• Crystallized SiO2 with poor barrier capability.
• Need clean silicon surface before oxidation.
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Oxidation Process
• Dry Oxidation, thin oxide
– Gate oxide
– Pad oxide, screen oxide, sacrificial oxide, etc.
• Wet Oxidation, thick oxide
– Field oxide
– Diffusion masking oxide
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Dry Oxidation System
To
Process
Tube
MFC
MFC
MFC
Control Valves
Regulator
Pro
cess
N2
Purg
e N
2
O2
HC
l
MFC
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Dry Oxidation
• Dry O2 as the main process gas
• HCl is used to remove mobile ions for
gate oxidation
• High purity N2 as process purge gas
• Lower grade N2 as idle purge gas
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Gate Oxidation Steps
• Idle with purge N2 flow
• Idle with process N2 flow
• Wafer boats push-in with process N2 flow
• Temperature ramp-up with process N2 flow
• Temperature stabilization with process N2 flow
• Oxidation with O2, HCl, stop N2 flow
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Dangling Bonds and Interface Charge
SiO2
Si
+ + + + +
Dangling
Bond
Si-SiO2
Interface
Interface State Charge (Positive)
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Gate Oxidation Steps, Continue
• Oxide annealing, stop O2, start process flow N2
• Temperature cool-down with process N2 flow
• Wafer boats pull-out with process N2 flow
• Idle with process N2 flow
• Next boats and repeat process
• Idle with purge N2 flow
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Wet Oxidation Process
• Faster, higher throughput
• Thick oxide, such as LOCOS
• Dry oxide has better quality
Process Temperature Film Thickness Oxidation Time
Dry oxidation 1000 °C 1000 Å ~ 2 hours
Wet oxidation 1000 °C 1000 Å ~ 12 minutes
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Water Vapor Sources
• Boiler
• Bubbler
• Flush
• Pyrogenic
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MFCProcess
Tube
Water
Heater
Heated Gas line Heated Fore line
Exhaust
Vapor Bubbles
Boiler System
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Bubbler System
Heater
MFCProcess
Tube
Exhaust
N2
N2 Bubbles
Heated Gas Line
N2 + H2O
Water
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Flush System
MFCProcess
Tube
Water
N2
Hot Plate
Heater
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Pyrogenic Steam System
H2
O2
Thermal Couple
To
Exhaust
Hydrogen Flame, 2 H2 + O2 → 2 H2O
Process Tube Wafer Boat
Paddle
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Pyrogenic System
• Advantage
– All gas system
– Precisely control of flow rate
• Disadvantage
– Introducing of flammable, explosive hydrogen
• Typical H2:O2 ratio is between 1.8:1 to 1.9:1.
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Pyrogenic Wet Oxidation System
MFC
MFC
MFC
Control Valves
Regulator
Pro
cess
N2
Purg
e N
2
O2
H2
MFC
Scrubbier
Exhaust
Process Tube
Wafers Burn Box
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Wet Oxidation Process Steps
• Idle with purge N2 flow
• Idle with process N2 flow
• Ramp O2 with process N2 flow
• Wafer boat push-in with process N2 and O2 flows
• Temperature ramp-up with process N2 and O2 flows
• Temperature stabilization with process N2 and O2 flows
• Ramp O2, turn-off N2 flow
• Stabilize the O2 flow
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Wet Oxidation Process Steps
• Turn-on H2 flow, ignition and H2 flow stabilization
• Steam oxidation with O2 and H2 flow
• Hydrogen termination, turn-off H2 while keeping O2 flow
• Oxygen termination, turn-off O2 start process N2 flow
• Temperature ramp-down with process N2 flow
• Wafer boat pull-out with process N2 flow
• Idle with process N2 flow
• Next boats and repeat process
• Idle with purge N2 flow
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Rapid Thermal Oxidation
• For gate oxidation of deep sub-micron device
• Very thin oxide film, < 30 Å
• Need very good control of temperature
uniformity, WIW and WTW.
• RTO will be used to achieve the device
requirement.
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RTP Process Diagram
Time
Ramp
up 1& 2
Cool
down
RTALoad
wafer
Unload
wafer
RTO
O2 flow
N2 flow
HCl flow
Temperature
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High Pressure Oxidation
• Faster growth rate
• Reducing oxidation temperature:
– 1 amt. = –30 °C
• Higher dielectric strength
• Thicker film
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High Pressure Oxidation
High Pressure
Inert Gas
High Pressure
Oxidant Gas
Stainless Steel Jacket
Quartz Process Chamber
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High Pressure Oxidation
Temperature Pressure Time
1 atmosphere 5 hours
1000 C 5 atmosphere 1 hour
25 atmosphere 12 minutes
Oxidation time to grow 10,000 Å wet oxide
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High Pressure Oxidation
Time Pressure Temperature
1 atmosphere 1000 C
5 hours 10 atmosphere 700 C
Oxidation temperature to grow 10,000 Å wet oxide in 5 hours
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High Pressure Oxidation
• Complex system
• Safety issues
• Not widely used in IC production
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Oxide Measurement
• Thickness
• Uniformity
• Color chart
• Ellipsometry
• Reflectometry
• Gate oxide
• Break down
voltage
• C-V
characteristics
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Linearly Polarized Incident Light
Elliptically Polarized
Reflected Light
n1, k1, t1
n2, k2
sp
Ellipsometry
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t
21
Substrate
Dielectric film, n(l)
Incident light
Human eye or
photodetector
Reflectometry
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C-V Test Configuration
Capacitor
Meter
Aluminum
Metal Platform
Silicon
Oxide
Large Resistor
HeaterHeater
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Summary of Oxidation
• Oxidation of silicon
• High stability and relatively easy to get.
• Application
– Isolation, masking, pad, barrier, gate, and etc.
• Wet and Dry
• More dry processes for advanced IC chips
• Rapid thermal oxidation and annealing for
ultra-thin gate oxide
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Diffusion
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Diffusion
• Most common physics phenomena
• Materials disperse from higher concentration
to lower concentration region
• Silicon dioxide as diffusion mask
• Was widely used for semiconductor doping
• “Diffusion Furnace” and “Diffusion Bay”
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Illustration of Diffusion Doping
Dopant
Silicon
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Illustration of Diffusion Doping
Dopant
Silicon
Junction Depth
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Definition of Junction depth
Background dopant concentration
Junction Depth, xj
Distance from the wafer surface
Dopant Concentration
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Diffusion
N-Silicon
Masking Oxide
N-Siliconp+ p+
Masking Oxide
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Diffusion
• Replaced by ion implantation due to the less
process control
• Still being used in drive-in for well formation
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Thermal Budget
• Dopant atoms diffuse fast at high temperature
D = D0 exp (–EA/kT)
• Smaller device geometry, less room for dopant
thermal diffusion, less thermal budget
• Thermal budget determines the time and
temperature of the post-implantation thermal
processes
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Illustration of Thermal Budget
As S/D Implantation Over Thermal Budget
Gate
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1 mm
Thermal Budget
1
10
100
1000
104/T (K)7 8 9 10
10001100 900 800
2 mm
0.5 mm
0.25 mm
Ther
mal
Budget
(se
c)
T (C)
Source: Chang
and Sze, ULSI
Technology
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Diffusion Doping Process
• Both dopant concentration and junction depth
are related to temperature.
• No way to independently to control both factor
• Isotropic dopant profile
• Replaced by ion implantation after the mid-
1970s.
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Diffusion Doping Process
• Silicon dioxide as hard mask
• Deposit dopant oxide
• Cap oxidation
– prevent dopant diffusion into gas phase
• Drive-in
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Diffusion Doping Process
• Oxidation, photolithography and oxide etch
• Pre-deposition:
B2H6 + 2 O2 → B2O3 + 3 H2O
• Cap oxidation:
2 B2O3 + 3 Si → 3 SiO2 + 4 B
2 H2O + Si → SiO2 + 2 H2
• Drive-in
– Boron diffuses into silicon substrate
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Diffusion Doping Process
• Oxidation, photolithography and oxide etch
• Deposit dopant oxide:
4POCl3 + 3O2 → 2P2O5 + 3Cl2
• Cap oxidation
2P2O5 + 5Si → 5SiO2 + 4P
– Phosphorus concentrates on silicon surface
• Drive-in
– Phosphorus diffuses into silicon substrate
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Phosphorus Diffusion System
MFC
MFC
MFC
Control Valves
Regulator
Pro
cess
N2
Pu
rge
N2
O2
PO
Cl 3
MFC
Scrubbier
Exhaust
Process Tube
Wafers Burn Box
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Si Substrate
Wafer Clean
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Si Substrate
Oxidation
SiO2
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Si Substrate
Doped Area Patterning
SiO2
PR
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Si Substrate
Etch Silicon Dioxide
SiO2
PR
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Si Substrate
Strip Photoresist
SiO2
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Si Substrate
Wafer Clean
SiO2
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Si Substrate
Dopant Oxide Deposition
SiO2
Deposited Dopant Oxide
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Si Substrate
Cap Oxidation
SiO2
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Phosphoric Oxide Deposition and
Cap Oxidation
N2 Flow
POCl3 Flow
O2 Flow
Push PullTemp
Ramp
Temp.
Stab.Dopant Deposition Cap
Oxide
Ramp
Down
Wafer
Position
Temperature
N2
Vent
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Drive-in
Si Substrate
SiO2
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Si Substrate
Strip Oxide, Ready for Next Step
SiO2
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Phosphorus Drive-in
Temperature
N2 Flow
O2 Flow
Push Temp
Ramp
Temp.
Stab.Drive-in
Wafer
Position
PullRamp
Down
Stab.
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Limitations and Applications
• Diffusion is isotropic process and always
dope underneath masking oxide
• Can’t independently control junction depth
and dopant concentration
• Used for well implantation drive-in
• R&D for ultra shallow junction (USJ)
formation
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Application of Diffusion: Drive-in
• Wells have the deepest junction depth
• Need very high ion implantation energy
• Cost of MeV ion implanters is very high
• Diffusion can help to drive dopant to the
desired junction depth while annealing
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Well Implantation and Drive-in
P-Epi
Photoresist
N-Well
P+
P-EpiN-Well
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Diffusion for Boron USJ Formation
• Small devices needs ultra shallow junction
• Boron is small and light, implanter energy
could be too high for it goes too deep
• Controlled thermal diffusion is used in
R&D for shallow junction formation
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Surface Clean
Si Substrate
STI STI
Silicide
Sidewall Spacer Sidewall Spacer
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BSG CVD
Si Substrate
STI STI
Boro-Silicate Glass
Silicide
Sidewall Spacer Sidewall Spacer
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RTP Dopant Drive-in
Si Substrate
STI
Boro-Silicate Glass
STI
SilicidePolysilicon
Gate Oxide
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Strip BSG
Si Substrate
STISTI
SilicidePolysilicon
Gate Oxide
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Doping Measurement
• Four-point probe
Rs = r/t
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Four-Point Probe Measurement
S1 S2 S3
P1 P2 P3 P4
V
I
Substrate
Doped Region
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Summary of Diffusion
• Physics of diffusion is well understood
• Diffusion was widely used in doping
processes in early IC manufacturing
• Replaced by ion implantation since the mid-
1970s
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Annealing and RTP Processes
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Post-implantation Annealing
• Energetic ions damage crystal structure
• Amorphous silicon has high resistivity
• Need external energy such as heat for atoms
to recover single crystal structure
• Only in single crystal structure dopants can
be activated
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Post-implantation Annealing
• Single crystal structure has lowest potential
energy
• Atoms tend to stop on lattice grid
• Heat can provide energy to atoms for fast
thermal motion
• Atoms will find and settle at the lattice grid
where has the lowest potential energy position
• Higher temperature, faster annealing
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Before Ion Implantation
Lattice Atoms
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After Ion Implantation
Dopant AtomLattice Atoms
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Thermal Annealing
Dopant AtomLattice Atoms
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Thermal Annealing
Dopant AtomsLattice Atoms
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Alloy Annealing
• A thermal process in which different atoms
chemically bond with each other to form a
metal alloy.
• Widely used in silicide formation
• Self aligned silicide (salicide)
– Titanium silicide, TiSi2
– Cobalt silicide, CoSi2
• Furnace and RTP
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Silicide
• Much lower resistivity than polysilicon
• Used as gate and local interconnection
• Used as capacitor electrodes
• Improving device speed and reduce heat
generation
• TiSi2, WSi2 are the most commonly used
silicide
• CoSi2, MoSi2, and etc are also used
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Titanium Silicide Process
• Argon sputtering clean
• Titanium PVD
• RTP Anneal, ~700 °C
• Strip titanium, H2O2:H2SO4
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Titanium Silicide ProcessTitanium
n+n+STI p+ p+
USG
Polysilicon
n+n+ USGUSGSTI
Titanium Silicide
n+n+ USG p+ p+USGSTI
Titanium SilicideSidewall Spacer
Ti Deposition
Annealing
Ti Strip
p+ p+
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Aluminum-silicon Alloy
• Form on silicon surface
• Prevent junction spiking due to silicon
dissolving in aluminum
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p+p+
Junction Spike
n-type Silicon
AlAl AlSiO2
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Rapid Thermal Process
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Rapid Thermal Processing (RTP)
• Mainly used for post-implantation rapid
thermal anneal (RTA) process.
• Fast temperature ramp-up, 100 to 150 °C/sec
compare with 15 °C/min in horizontal
furnace.
• Reduce thermal budget and easier process
control.
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Rapid Thermal Processing (RTP)
• Single wafer rapid thermal CVD (RTCVD)
chamber can be used to deposit polysilicon and
silicon nitride.
• RTCVD chamber can be integrated with other
process chamber in a cluster tool for in-line
process.
• Thin oxide layer (< 40 Å) is likely to be grown
with RTO for WTW uniformity control.
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Schematic of RTP Chamber
External Chamber
IR
Quartz
Chamber
Wafer
Process
Gases
Tungsten-Halogen Lamp
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Lamp Array
Bottom
Lamps
Wafer
Top
Lamps
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RTP Chamber
Photo courtesy of
Applied Materials, Inc
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Annealing and Dopant Diffusion
• At higher temperature >1100 °C anneal is
faster than diffusion
• Post implantation prefer high temperature
and high temperature ramp rate.
• Single wafer rapid thermal process tool has
been developed initially for this application
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Annealing and Dopant Diffusion
• Dopant atoms diffuse at high temperature
• Furnace has low temperature ramp rate
(~10 °C/min) due to large thermal capacity
• Furnace annealing is a long process which
causes more dopant diffusion
• Wafer at one end gets more anneal than
wafer at another end
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Anneal Rate and Diffusion Rate
Temperature
Anneal Rate
Diffusion Rate
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Dopant Diffusion After Anneal
Furnace annealRTA
Gate
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Advantage of RTP over Furnace
• Much faster ramp rate (75 to 150 °C/sec)
• Higher temperature (up to 1200 °C)
• Faster process
• Minimize the dopant diffusion
• Better control of thermal budget
• Better wafer to wafer uniformity control
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RTP Temperature Change
Time
Tem
per
ature
Ramp
up
Cool downAnnealLoad
wafer
Unload
wafer
N2 Flow
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Thermal Nitridization
• Titanium PVD
• Thermal nitridization with NH3
NH3 + Ti → TiN + 3/2 H2
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Titanium Nitridization
SiO2
SiO2
Ti
Ti TiN
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RTO Process
• Ultra thin silicon dioxide layer < 30Å
• Better WTW uniformity
• Better thermal budget control
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RTP Process Diagram
Time
Ramp
up 1& 2
Cool
down
RTALoad
wafer
Unload
wafer
RTO
O2 flow
N2 flow
HCl flow
Temperature
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Future Tends
• Rapid thermal process (RTP)
• In-situ process monitoring
• Cluster tools
• Furnace will still be used
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Cluster Tool
Transfer
Chamber
RTCVD
a-Si
Loading Station
HF Vapor
Clean
RTO/RTP
Cool
down
Unloading Station
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Summary of Anneal and RTP
• The most commonly used anneal processes are
post-implantation annealing, alloy annealing and
reflow
• Thermal anneal is required after ion implantation
for recover crystal structure and activation
dopant atoms
• Thermal anneal helps metal to react with silicon
to form silicides
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• Metal anneal helps to form larger grain size and
reduces the resistivity
• RTP becomes more commonly used in annealing
processes
Summary of Anneal and RTP
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• Advantages of RTP
– Much faster ramp rate (75 to 150 °C/sec)
– Higher temperature (up to 1200 °C)
– Faster process
– Minimize the dopant diffusion
– Better control of thermal budget
– Better wafer to wafer uniformity control
Summary of Anneal and RTP
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Summary of Thermal Process
• Oxidation, diffusion, annealing, and deposition
• Wet oxidation is faster, dry oxidation has better
film quality. Advanced fab: mainly dry oxidation.
• Diffusion doping with oxide mask, used in lab
• LPCVD polysilicon and front-end silicon nitride
• Annealing recovers crystal and activates dopants
• RTP: better control, faster and less diffusion
• Furnaces: high throughput and low cost, will
continue to be used in the future fabs