chapter 5c: a multi-cycle cpu
DESCRIPTION
Chapter 5c: A Multi-Cycle CPU. Observations on the Single Cycle Design. The single-cycle datapath is straightforward, but... It has to use 3 separate ALU’s It has separate Instruction and Data memories Cycle time is determined by worst-case path. A multi-cycle datapath might be better - PowerPoint PPT PresentationTRANSCRIPT
Ch5c- 2EE/CS/CPE 3760 - Computer OrganizationSeattle Pacific University
Observations on the Single Cycle Design
• The single-cycle datapath is straightforward, but...
• It has to use 3 separate ALU’s
• It has separate Instruction and Data memories
• Cycle time is determined by worst-case path
5.3
• A multi-cycle datapath might be better
• We can reuse some of the hardware
• We can combine the memories
• Cycle time is still constant, but instructions may take differing numbers of cycles
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The Multi-cycle idea...
5.4
RegistersMemory
Read reg. 1
Read reg. 2
Write reg
Write data
Read data 1
Read data 2
Read address
Write address
Write data
Read dataResult
PC
We can use any logic block once each cycleWe can use any logic block once each cycle
ALU: Computes R-type value Computes Address Computes next PC Computes Branch
ALU: Computes R-type value Computes Address Computes next PC Computes Branch
Memory: Holds Instructions Holds Data
Memory: Holds Instructions Holds Data
Registers: Hold data values
Registers: Hold data values
Ch5c- 4EE/CS/CPE 3760 - Computer OrganizationSeattle Pacific University
Multi-cycle Datapath
5.4
MemoryRead address
Write address
Write data
Read dataResult
Zero
Sh.Left2
0
1
signextend
PC
[25-21]
[20-16]
[15-11]
16 32
0
1
1
0
0
1
2
3
4
0
1
[15-0]
PC
Start: PCStart: PC
RegistersRead reg num B
Write reg num
Write reg data
Read reg data A
Read reg data B
Read reg num A
Read Instructionfrom memory
Read Instructionfrom memory
Decode,Readregisters (R-type)
Decode,Readregisters (R-type) Do ALU OpDo ALU Op
WriteResult reg.
WriteResult reg.
Update PC=PC+4Update PC=PC+4 Load Instruction:Need addressLoad Instruction:Need address
Read from MemoryRead from Memory Write resultWrite result Store Instr.Store Instr.
BranchBranch
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Breaking instructions into cycles
5.4
Instruction Fetch, Increment PC
Decode Instruction, Access Registers
Compute Memory Address Execute Instruction If condition holds
update PC to Target
Read/Write Memory Write Register
Write Register
R-typeBranch
LW,SW
LW
Update PC
Jump
Note: Some of theseare unneeded, butthey don’t hurt!
Note: Some of theseare unneeded, butthey don’t hurt!
Compute Branch Target
ALUMem
Mem
ALU
ALU
ALU
ALU
Reg
Reg
Reg
Can use each major block (ALU,reg,mem)once each cycle
Can use each major block (ALU,reg,mem)once each cycle
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Multi-cycle Control
5.4
MemoryRead address
Write address
Write data
Read dataResult
Zero
Sh.Left2
0
1
signextend
PC
[25-21]
[20-16]
[15-11]
16 32
0
1
1
0
0
1
2
3
4
0
1
[15-0]
PC
RegistersRead reg num B
Write reg num
Write reg data
Read reg data A
Read reg data B
Read reg num A
IorDMemRead
MemWrite MemToReg
ALUSelB
ALUSelARegWriteRegDest
ALUcontrol
[5-0]
Control
Inst[31-26]
Note: The control signals will be constant during each cycle, but may change during the multi-cycle instruction
Note: The control signals will be constant during each cycle, but may change during the multi-cycle instruction
ALUOp
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Issues
5.4
MemoryRead address
Write address
Write data
Read dataResult
Zero
Sh.Left2
0
1
signextend
PC
[25-21]
[20-16]
[15-11]
16 32
0
1
1
0
0
1
2
3
4
0
1
[15-0]
PC
RegistersRead reg num B
Write reg num
Write reg data
Read reg data A
Read reg data B
Read reg num A
IorDMemRead
MemWrite MemToReg
ALUSelB
ALUSelARegWriteRegDest
ALUcontrol
[5-0]
Control
Inst[31-26]
1. Memory reads overwrite the instruction
Instr. Reg
Instr. [31-0]
2. ALU overwrites PC every cyclePCWrite
PCWriteCond
Zero
3. Branches?
- Add Instr. Reg.- Add PCWrite Signal
Add PCWriteCond Signal
IRWrite
ALUOp
Ch5c- 8EE/CS/CPE 3760 - Computer OrganizationSeattle Pacific University
Issues
5.4
MemoryRead address
Write address
Write data
Read data
Sh.Left2
0
1
signextend
PC
[25-21]
[20-16]
[15-11]
16 32
0
1
1
0
0
1
2
3
0
1
[15-0]
PCorPC+4
RegistersRead reg num B
Write reg num
Write reg data
Read reg data A
Read reg data B
Read reg num A
IorDMemRead
MemWrite MemToReg
ALUSelB
ALUSelARegWriteRegDest
ALUcontrol
[5-0]
Control
On branches, the PC is alwayswritten with Zero!
PCWritePCWriteCond
Zero
Sh.Left2
26 28
Inst[25-0]
Concat.4
[31-28]
32
Inst[31-26]
IRWrite
ALUOp
Result
Zero
4
PCSource
2
0
1
ALUOut
A
B
MDR
Instr. Reg
Instr. [31-0]
Logic for Jumps
A, B: Save registers for use on next cycle
MDR: Save result of read for use on next cycle
ALU Out: Save result of ALU for use on next cycle
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Instruction Fetch
5.4
MemoryRead address
Write address
Write data
Read dataResult
Zero
Sh.Left2
0
1
signextend
PC
[25-21]
[20-16]
[15-11]
16 32
0
1
1
0
0
1
2
3
4
0
1
[15-0]
PCorPC+4
RegistersRead reg num B
Write reg num
Write reg data
Read reg data A
Read reg data B
Read reg num A
IorDMemRead
MemWrite MemToReg
ALUSelB
ALUSelARegWriteRegDest
ALUcontrol
[5-0]
Control
Inst[31-26]
PCWritePCWriteCond
Zero
PCSource
2
0
1
Sh.Left2
26 28
Inst[25-0]
Concat.4
[31-28]
32
IRWrite
01 0 1
0
1
01
0
ALUOp 0
IorD=0MemRead=1MemWrite=0IRWrite=1ALUSelA=0ALUSelB=1
ALUOp=0PCWrite=1PCSource=0RegWrite=0
x
x x
ALUOut
A
B
MDR
Instr. Reg
Instr. [31-0]
Cycle 1 All instructions
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Instr. Decode/Reg. Fetch
5.4
MemRead=0MemWrite=0IRWrite=0ALUSelA=0ALUSelB=3
ALUOp=0PCWrite=0PCWriteCond=0RegWrite=0
MemoryRead address
Write address
Write data
Read dataResult
Zero
Sh.Left2
0
1
signextend
PC
[25-21]
[20-16]
[15-11]
16 32
0
1
1
0
0
1
2
3
4
0
1
[15-0]
PCorPC+4
RegistersRead reg num B
Write reg num
Write reg data
Read reg data A
Read reg data B
Read reg num A
IorDMemRead
MemWrite MemToReg
ALUSelB
ALUSelARegWriteRegDest
ALUcontrol
[5-0]
Control
PCWritePCWriteCond
Zero
PCSource
2
0
1
Sh.Left2
26 28
Inst[25-0]
Concat.4
[31-28]
32
IRWrite
ALUOp
ALUOut
A
B
0
00
0
3
0
0
0
0
xx x
x
MDR
Instr. Reg
Instr. [31-0]
Cycle 2 All instructions
Inst[31-26]
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R-type Execution
5.4
MemRead=0MemWrite=0IRWrite=0ALUSelA=1ALUSelB=0
ALUOp=2PCWrite=0PCWriteCond=0RegWrite=0
MemoryRead address
Write address
Write data
Read dataResult
Zero
Sh.Left2
0
1
signextend
PC
[25-21]
[20-16]
[15-11]
16 32
0
1
1
0
0
1
2
3
4
0
1
[15-0]
PCorPC+4
RegistersRead reg num B
Write reg num
Write reg data
Read reg data A
Read reg data B
Read reg num A
IorDMemRead
MemWrite MemToReg
ALUSelB
ALUSelARegWriteRegDest
ALUcontrol
[5-0]
Control
PCWritePCWriteCond
Zero
PCSource
2
0
1
Sh.Left2
26 28
Inst[25-0]
Concat.4
[31-28]
32
IRWrite
ALUOp
ALUOut
A
B
0 0 0
1
0
0
0
2
0
xx x
x
MDR
Instr. Reg
Instr. [31-0]
Cycle 3 R-Type
Inst[31-26]
Ch5c- 12EE/CS/CPE 3760 - Computer OrganizationSeattle Pacific University
R-type Completion
5.4
MemRead=0MemWrite=0RegDest=1 PCWrite=0
PCWriteCond=0RegWrite=1MemToReg=0
MemoryRead address
Write address
Write data
Read dataResult
Zero
Sh.Left2
0
1
signextend
PC
[25-21]
[20-16]
[15-11]
16 32
0
1
1
0
0
1
2
3
4
0
1
[15-0]
PCorPC+4
RegistersRead reg num B
Write reg num
Write reg data
Read reg data A
Read reg data B
Read reg num A
IorDMemRead
MemWrite MemToReg
ALUSelB
ALUSelARegWriteRegDest
ALUcontrol
[5-0]
Control
PCWritePCWriteCond
Zero
PCSource
2
0
1
Sh.Left2
26 28
Inst[25-0]
Concat.4
[31-28]
32
IRWrite
ALUOp
ALUOut
A
B
0 0x
x
0
1
x
0
x
x
0 1x
MDR
Instr. Reg
Instr. [31-0]
Cycle 4 R-Type
Inst[31-26]
Ch5c- 13EE/CS/CPE 3760 - Computer OrganizationSeattle Pacific University
Branch if Equal
5.4
MemRead=0MemWrite=0ALUSelA=1ALUSelB=0PCSource=1
ALUOp=1PCWrite=0PCWriteCond=1RegWrite=0
MemoryRead address
Write address
Write data
Read dataResult
Zero
Sh.Left2
0
1
signextend
PC
[25-21]
[20-16]
[15-11]
16 32
0
1
1
0
0
1
2
3
4
0
1
[15-0]
PCorPC+4
RegistersRead reg num B
Write reg num
Write reg data
Read reg data A
Read reg data B
Read reg num A
IorDMemRead
MemWrite MemToReg
ALUSelB
ALUSelARegWriteRegDest
ALUcontrol
[5-0]
Control
PCWritePCWriteCond
Zero
PCSource
2
0
1
Sh.Left2
26 28
Inst[25-0]
Concat.4
[31-28]
32
IRWrite
ALUOp
ALUOut
A
B
0 01
0
0
1
xxx
1
x
0 1
MDR
Instr. Reg
Instr. [31-0]
Cycle 3 BEQ
Inst[31-26]
Ch5c- 14EE/CS/CPE 3760 - Computer OrganizationSeattle Pacific University
MemToReg RegWriteRegDestIRWrite
Jump
5.4
MemRead=0MemWrite=0
PCWrite=1RegWrite=0PCSource=2
MemoryRead address
Write address
Write data
Read dataResult
Zero
Sh.Left2
0
1
signextend
PC
[25-21]
[20-16]
[15-11]
16 32
0
1
1
0
0
1
2
3
4
0
1
[15-0]
PCorPC+4
RegistersRead reg num B
Write reg num
Write reg data
Read reg data A
Read reg data B
Read reg num A
IorDMemRead
MemWrite
ALUSelB
ALUSelA
ALUcontrol
[5-0]
Control
PCWritePCWriteCond
Zero
PCSource
2
0
1
Sh.Left2
26 28
Inst[25-0]
Concat.4
[31-28]
32
ALUOp
ALUOut
A
B
0 0
xxx
2
x
x
x
x
x
0
1
MDR
Instr. Reg
Instr. [31-0]
Cycle 3 Jump
Inst[31-26]
Ch5c- 15EE/CS/CPE 3760 - Computer OrganizationSeattle Pacific University
Memory Addr. Completion
5.4
MemRead=0MemWrite=0IRWrite=0ALUSelA=1ALUSelB=2
ALUOp=0PCWrite=0PCWriteCond=0RegWrite=0
MemoryRead address
Write address
Write data
Read dataResult
Zero
Sh.Left2
0
1
signextend
PC
[25-21]
[20-16]
[15-11]
16 32
0
1
1
0
0
1
2
3
4
0
1
[15-0]
PCorPC+4
RegistersRead reg num B
Write reg num
Write reg data
Read reg data A
Read reg data B
Read reg num A
IorDMemRead
MemWrite MemToReg
ALUSelB
ALUSelARegWriteRegDest
ALUcontrol
[5-0]
Control
PCWritePCWriteCond
Zero
PCSource
2
0
1
Sh.Left2
26 28
Inst[25-0]
Concat.4
[31-28]
32
IRWrite
ALUOp
ALUOut
A
B
0 0
0
0x
xx
1
2
0
x0
0
MDR
Instr. Reg
Instr. [31-0]
Cycle 3 LW,SW
Inst[31-26]
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Memory Read
5.4
MemRead=1MemWrite=0IRWrite=0
PCWrite=0PCWriteCond=0RegWrite=0IorD=1
MemoryRead address
Write address
Write data
Read dataResult
Zero
Sh.Left2
0
1
signextend
PC
[25-21]
[20-16]
[15-11]
16 32
0
1
1
0
0
1
2
3
4
0
1
[15-0]
PCorPC+4
RegistersRead reg num B
Write reg num
Write reg data
Read reg data A
Read reg data B
Read reg num A
IorDMemRead
MemWrite MemToReg
ALUSelB
ALUSelARegWriteRegDest
ALUcontrol
[5-0]
Control
PCWritePCWriteCond
Zero
PCSource
2
0
1
Sh.Left2
26 28
Inst[25-0]
Concat.4
[31-28]
32
IRWrite
ALUOp
ALUOut
A
B
1 0
0
0x
x
x
x0
01
x x
MDR
Instr. Reg
Instr. [31-0]
Cycle 4 LW
Inst[31-26]
Ch5c- 17EE/CS/CPE 3760 - Computer OrganizationSeattle Pacific University
Read WriteBack
5.4
MemRead=0MemWrite=0RegDest=0 PCWrite=0
PCWriteCond=0RegWrite=1MemToReg=1
MemoryRead address
Write address
Write data
Read dataResult
Zero
Sh.Left2
0
1
signextend
PC
[25-21]
[20-16]
[15-11]
16 32
0
1
1
0
0
1
2
3
4
0
1
[15-0]
PCorPC+4
RegistersRead reg num B
Write reg num
Write reg data
Read reg data A
Read reg data B
Read reg num A
IorDMemRead
MemWrite MemToReg
ALUSelB
ALUSelARegWriteRegDest
ALUcontrol
[5-0]
Control
PCWritePCWriteCond
Zero
PCSource
2
0
1
Sh.Left2
26 28
Inst[25-0]
Concat.4
[31-28]
32
IRWrite
ALUOp
ALUOut
A
B
0
0
1x
x
x
x0
01x
x
MDR
0
Instr. Reg
Instr. [31-0]
Cycle 5 LW
Inst[31-26]
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Memory Write
5.4
MemRead=0MemWrite=1
PCWrite=0PCWriteCond=0RegWrite=0
MemoryRead address
Write address
Write data
Read dataResult
Zero
Sh.Left2
0
1
signextend
PC
[25-21]
[20-16]
[15-11]
16 32
0
1
1
0
0
1
2
3
4
0
1
[15-0]
PCorPC+4
RegistersRead reg num B
Write reg num
Write reg data
Read reg data A
Read reg data B
Read reg num A
IorDMemRead
MemWrite MemToReg
ALUSelB
ALUSelARegWriteRegDest
ALUcontrol
[5-0]
Control
PCWritePCWriteCond
Zero
PCSource
2
0
1
Sh.Left2
26 28
Inst[25-0]
Concat.4
[31-28]
32
IRWrite
ALUOp
ALUOut
A
B
0 1
0
0x
x
x
x0
x x
x
x
MDR
Instr. Reg
Instr. [31-0]
Cycle 4 SW
Inst[31-26]
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Control Finite State MachineIorD=0
MemRead=1MemWrite=0IRWrite=1ALUSelA=0ALUSelB=1ALUOp=0PCWrite=1PCSource=0RegWrite=0
Instr. Fetch
5.4
MemRead=0MemWrite=0IRWrite=0ALUSelA=0ALUSelB=3ALUOp=0PCWrite=0
PCWriteCond=0RegWrite=0
Instr. Decode/Register Fetch
Write-backR-typeCompletion
JumpBranch
Execution
JumpBEQ
LW
SW
MemRead=0MemWrite=0IRWrite=0ALUSelA=1ALUSelB=0ALUOp=2PCWrite=0
PCWriteCond=0RegWrite=0
MemRead=0MemWrite=0RegDest=1PCWrite=0
PCWriteCond=0RegWrite=1MemToReg=0
MemRead=0MemWrite=0ALUSelA=1ALUSelB=0PCSource=1ALUOp=1PCWrite=0
PCWriteCond=1RegWrite=0
MemRead=0MemWrite=0 PCWrite=1RegWrite=0PCSource=2
MemRead=0MemWrite=0IRWrite=0ALUSelA=1ALUSelB=2ALUOp=0PCWrite=0
PCWriteCond=0RegWrite=0
MemRead=0MemWrite=1PCWrite=0
PCWriteCond=0RegWrite=0
MemRead=1MemWrite=0IRWrite=0PCWrite=0
PCWriteCond=0RegWrite=0
IorD=1
MemRead=0MemWrite=0RegDest=0PCWrite=0
PCWriteCond=0RegWrite=1MemToReg=1
R-type
LW or SW
Mem. Addr.Completion
Memory Access
Memory Access
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Implementing the Control
• Implementing a Finite State Machine is straightforward
• 10 states --> 4 flipflops
• Choose binary representations for each state
• Create state transition table
• Map to flipflop type
• Using K-maps, build a function for each control output
• 50-70 Gates
• Or..., Put the FSM into a computer program and trust it
5.4
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Evaluation
• Multi-cycle goals:
• Reuse common parts• Only one ALU in the design, but more complexity
• Merge the memories• Success!
• Get rid of worst-case cycle time constraint• R-type: 4 cycles, Branch: 3 cycles, Jump: 3 cycles,
LW: 5 cycles, SW: 4 cycles
• Which is faster? Single- or Multi-cycle?• It depends on how long the cycle time is…
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Single-Cycle Performance ReviewWhat major functional units are used by different instructions?
R-type: Instr. Fetch Register Read ALU Register Write
Assume the following times:
Memory Access: 2ns
ALU: 2ns
Registers: 1ns
6ns
8ns
7ns
5ns
2ns
Branch: Instr. Fetch Register Read ALU
LW: Instr. Fetch Register Read ALU Memory Read Register Write
SW: Instr. Fetch Register Read ALU Memory Write
Jump: Instr. Fetch
Since the longest time is 8ns (LW),the cycle time must be at least 8ns.
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Breaking instructions into cycles
5.4
Instruction Fetch, Increment PC
Decode Instruction, Access Registers
Compute Memory Address Execute Instruction If condition holds
update PC to Target
Read/Write Memory Write Register
Write Register
R-typeBranch
LW,SW
LW
Update PC
Jump
Compute Branch Target
ALUMem
Mem
ALU
ALU
ALU
ALU
Reg
Reg
Reg
Assume the following times:
Memory Access: 2ns
ALU: 2ns
Registers: 1ns
2ns
2ns
2ns 2ns2ns
2ns
1ns
1ns
1ns
Resulting times:Jump, Branch: 6nsR-type, SW: 8nsLW: 10ns
2ns
2ns
2ns