chapter 6 pc peripheral chips - pt 1 rtc, timers, keybd...

Rev. 1.0 Sys MFG T/ED 4/25/2003

PC Architecture For Technicians Level-1Technical Excellence Development Series

Ch 6 -

Chapter 6Chapter 6PC Peripheral Chips PC Peripheral Chips -- Pt 1Pt 1RTC, Timers, Keybd Ctlr RTC, Timers, Keybd Ctlr

PC Architecture for PC Architecture for Technicians: LevelTechnicians: Level--11

Systems Manufacturing Training Systems Manufacturing Training and Employee Developmentand Employee Development

Copyright © 1996 Intel Corp.Copyright © 1996 Intel Corp.

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Ch 6 -

OBJECTIVES: At the end of this section, the student will be able to do the following:

l Describe the Real-Time CMOS Clock Chip.

l Discuss the CMOS Address Map.

l Explain how to access the CMOS RAM.

l Describe the 8254 Programmable Interval Timer.

l Explain the function of the three Counter/Timers.

l Describe the 8742 Keyboard Controller.

l Discuss the functions of the Keyboard Controller.

l Name the I/O Ports associated with the 8742.

l Discuss the Misc. Keyboard Controller Signals.

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Ch 6 -

REALREAL--TIME TIME CMOS CMOS CLOCK CLOCK

DescriptionDescription

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Ch 6 -

REAL-TIME CMOS CLOCKlCMOS RAM - Complimentary Metal Oxide

Semiconductor Random Access Memory

lCMOS RAM is a small amount of low power battery -backed memory used to store time & configuration information used during the boot-up process.nThe configuration information includes the number & type

of floppy drives, graphics adapter, base memory, etc.

nThe RTC is independent of the CPU & all other chips & keeps updating time in the background.

lAlso know as:nRTC - Real Time Clock

nNVRAM- Non-Volatile RAM

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Ch 6 -

REAL-TIME CMOS CLOCK

BATTERY BACKUP

CLOCK INT (To IRQ8)

RAM013t14t

63t

} USED BY CLOCK

USED TO STORECONFIGURATIONINFORMATION

}

CMOS CLOCK CHIP Motorola MC146818 or DALLAS 12887

or equivalent

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Ch 6 -

REAL-TIME CMOS CLOCKlREAL-TIME CMOS CLOCK CHIP WITH BATTERY

BACKUP

lThe clock chip contains battery backup and 64 (40H) bytes of CMOS RAM, accessed through ports 70H and 71H. (Newer versions contain 128 (80H) bytes.)

l14 bytes (0-0DH) of the CMOS RAM are used by the internal clock circuitry to keep track of time in BCD format and as Status Registers.

lThe remaining bytes are used to store Configuration Status information used by BIOS.

lThe clock chip can be used to generate an interrupt on IRQ8, interrupt type 70H (no defined PC function) .

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Ch 6 -

BATTERY BACKED UP CMOS / RTC"PC/AT" CONFIGURATION STORAGE

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F

10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F

20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F

30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F


40H bytes of CMOS RAM

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Ch 6 -

RTC Address RTC Address MapMap

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Ch 6 -

RTC Address Map

SECONDSSECONDS ALARM

MINUTESMINUTES ALARM

HOURSHOURS ALARM

DAY OF THE WEEKDAY OF THE MONTH

MONTHYEAR

REGISTER AREGISTER BREGISTER CREGISTER D

012345678910111213

00H

0DH

3FH

1314

63

14 BYTES

50 BYTES

CONFIGURATIONREGISTERS

BINARYOR

BCDINPUTS

00

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Ch 6 -

RTC Address Map - Bytes 0-13tFUNCTION

Time, Calendar, and Alarm Bytes

Seconds register 00HSeconds alarm register 01HMinutes register 02HMinutes alarm register 03HHours register 04HHours alarm register 05HDay of week register 06HDate of month register 07HMonth register 08HYear register 09H

Status Registers

Status register A 0AHStatus register B 0BHStatus register C 0CHStatus register D 0DH

FUNCTION

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Ch 6 -

RTC Address Map - Bytes 14t-63tFUNCTIONGeneral Configuration Bytes

Diagnostic status byte 0EHShutdown status byte OFHFloppy drive type byte 10HReserved 11HFixed disk type byte 12HReserved 13HEquipment byte 14HLow base mem byte 15HHigh base mem byte 16HLow exp mem byte 17HHigh exp mem byte 18HDrive C ext type byte 19HDrive D ext type byte 1AH

General Configuration Bytes

Reserved 1BH--1EHFeatures installed byte 1FHMisc Reserved 20H-27HProduct Dependent 28H-2DHCMOS CHECKSUM byte 2EH-2FHLSB of extended mem 30HMSB of extended mem 31HDate century byte 32HSetup information byte 33HSystem speed byte 34HMisc Reserved 35H-3CHMisc Reserved 3DH-3FH

NOTE: Use of some locationsvaries with BIOS Vendor & BIOSVersion.

FUNCTION

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Ch 6 -

Sample of “CMOS.DOC” from SPEED

DEFAULTSBYTE DESCRIPTION [BIOS] {MFG} CUST10 Floppy Information [40] {44}

Bit 7-4 Floppy Drive A Type 0100y 0100y YESBit 3-0 Floppy Drive B Type 0000y 0100y YES

0000 = Not Installed0001 = 360KB 5.25"0010 = 1.2MB 5.25"0011 = 720KB 3.5"0100 = 1.44MB 3.5"0101 = Reserved for Future Use0110 = 2.88MB 3.5"0111-1111 Reserved for Future Use

INTEL PHASE III BIOS CMOS USAGE GUIDEPRODUCT: MORRISON MC (CH0_)VERSION: 1.00.01.CH0

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Ch 6 -


DEFAULTSBYTE DESCRIPTION [BIOS] {MFG} CUST14 Equipment Byte [POST] [POST]

Bit 7-6 Number of Floppy Drives POST POST NOBit 5-4 Display Type POST POST NOBit 3 Display Installed POST POST NOBit 2 Keyboard Installed POST POST NOBit 1 Co-Processor Installed POST POST NOBit 0 Floppy Installed POST POST NO

15 Base Memory Low Byte/KB [POST] {POST} NO

16 Base Memory High Byte/KB [POST] {POST} NO

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Ch 6 -


DEFAULTSBYTE DESCRIPTION [BIOS] {MFG} CUST2E Standard CMOS Checksum High Byte [POST] {POST} NO2F Standard CMOS Checksum Low Byte [POST] {POST} NO

7E Extended CMOS Checksum High Byte [POST] {POST} NO7F Extended CMOS Checksum Low Byte [POST] {POST} NO

NOTE:1. Extended CMOS (128Bytes) must be available for use.2. The standard cmos checksum is on cmos registers from 10h to 2Dh.

Standard cmos checksum: 10+11+..+2C+2D => 2E(H), 2F(L)3. The extended cmos checksum is on cmos registers from 48h to 7Dh.

Extended cmos checksum: 48+49+...+7D => 7E(H), 7F(L)

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Ch 6 -

ACCESSING ACCESSING CMOS RAMCMOS RAM

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Ch 6 -

REAL-TIME CMOS CLOCKlThe CMOS RAM is accessed in the following ways:

n1. Writing the address of the desired byte to port 70H.

3The address range is 0-3FH (0-63t).

n2. Reading from or writing to the byte using port 71H.

lExample: To access location 10H in CMOS RAMnWrite the RAM Address (10H) to I/O Port 70.

nRead/Write the RAM by performing an I/O Read/Write to Port 71.

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Ch 6 -

BATTERY BACKED-UP CMOS / RTC"AT" CONFIGURATION STORAGE

01234567

PORT 71: DATA "SHOOTER"

01234567

PORT 70: ADDRESS "POINTER"


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Ch 6 -

Real Time Clock , CMOS Memory and Battery

Battery IRQ8

ADDR

DATA

CMOSMemory

X-Bus 8 bits

OUT 70 (RTCALE#)

OUT 71 (RTCWR#)

IN 71 (RTCRD#)

Port 70 AddressPort 71 Data

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Ch 6 -

ACCESSING CMOS RAMl ITP COMMAND EXAMPLE (OFFSET 10H).

lPORTS TO ADDRESS CMOS RAMn70H = ADDRESS PORT

n71H = DATA PORT

lREAD ;READ OFFSET 10H nPort (70H) = 10H

nPort (71H) ;READ IT

lWRITE ;WRITE OFFSET 10H nPort (70H) = 10H

nPort (71H) = 44H ;WRITE IT

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Ch 6 -

ACCESSING CMOS RAMlASSEMBLY LANGUAGE EXAMPLE (OFFSET 10H).

lPORTS TO ADDRESS CMOS RAMn70H = ADDRESS PORT

n71H = DATA PORT

lREAD ;READ OFFSET 10HnMOV AL, RAM_ADDRESS ;e.g. MOV AL, 10H

nOUT 70H,AL

nIN AL,71H ;READ IT

lWRITE ;WRITE OFFSET 10HnMOV AL, RAM_ADDRESS ;e.g. MOV AL, 10H

nOUT 70H,AL

nMOV AL, RAM_DATA ;e.g. MOV AL, 44H

nOUT 71H, AL ;WRITE IT

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Ch 6 -

ACCESSING CMOS RAMlNOTES: Bit 7 of port 70H controls the enable and

disable of the NMI interrupts. nTake care to leave bit 7 unchanged when addressing the

clock chip.

nYou may notice that some BIOS accesses to the Shutdown Byte at offset 0FH, use address 8FH.38F in HEX => 1000 1111 in Binary

nThe MSB (Bit 7) is set to 1 to keep NMI Disabled.3(NMI is covered in detail in the Interrupt Section)

01234567

PORT 70: ADDRESS "POINTER"

1 0 0 0 1 1 1 1

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Ch 6 -

8254 8254 PPROGRAMMABLE ROGRAMMABLE IINTERVAL NTERVAL TTIMER IMER

(PIT)(PIT)

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Ch 6 -

Clock Period

t

PC Compatible TimerslThe PC/AT incorporates an 8254 PIT (Programmable

Interval Timer) which generates timing signals for use on the System Board.

lFrequency = 1/ time (1/period)

lOne clock period is usually measured on "like" clock edges;ni.e.: Rising-Edge to Rising-Edge, or

nFalling-Edge to Falling Edge.

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Ch 6 -

8254 COUNTER / TIMER

OUT 61

Counter 0

Counter 1

Counter 2

1.19MHz

÷12

0

1

Speaker Data

÷24

5

Refresh

IRQ0

OUT/IN 40

OUT/IN 41

OUT/IN 42

IN 61

14.318 MHz

"1"

"1"

CLK

ENA

CLK

ENA

CLK

ENA

TimerControlOUT/IN 43

(Time of Day Counter - 18.2 Hz)

ISA BUS84OSC=14.318 MHz

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Ch 6 -

THE 8254 PROGRAMMABLE INTERVAL TIMER (PIT)

lThe 8254 contains three functionally independent counter/timers.

lEach CT (Counter/Timer) consists of the following:na 16-bit down-counter

n a CLK input pin to trigger the down-counter

na GATE control input to gate the counting on/off

nan OUT pin producing a square-wave or periodic pulse (in PC/AT)

l In the PC/AT, all three CLK inputs are tied to a 1.19 MHz input frequency.

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Ch 6 -

COUNTER/TIMER FUNCTIONSlThe three Counter/Timers (CT0, CT1, CT2) are

initialized by BIOS to perform the following functions: nCT0--(TOD) interrupt.

3 Output is a square-wave with a 55 ms period.

nCT1--A high output initiates a DRAM refresh cycle.3Output is a pulse with a 15.6 usec period.

n CT2--Speaker Frequency3Generates Tone for Speaker (BEEP, BELL, etc)

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Ch 6 -

D7 D6 D5 D4 D3 D2 D1 D0

BCD

Mode

Read / Write

Select Counter

SC1 SC0 RW1 RW0 M2 M1 M0 BCD

01

0 0 00 0 1

1 0X 1 11 0 01 0 1

X

0 00

01

11 1

0 00

01

11 1

16 Bit BinaryBCD 4-Decades

Latch Counter ValueRead/Write LSB ONLYRead/Write MSB ONLY

Read/Write LSB then MSB

Counter 1 "Refresh Timer" 15.6usCounter 2 "Speaker Tone"

Counter 0 "Time-Of-Day" 55ms

Read Back Specific Counter Value

Mode 0 INT on TC

Mode 1 R-One ShotMode 2 Rate Gen.

Mode 3 Square WaveMode 4 S/W StrobeMode 5 H/W Strobe

CONTROL WORD FORMAT: A1.A0=11; CS*=0; RD*=1; WR*=0

CONTROL WORD FORMAT (Port 43H)

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Ch 6 -

8254 COUNTER #0 Time Of Day

Write 36H to Port 43HS/C=00=> Counter #0Mode= 011y => Mode 3 (Square Wave- Symmetric)

Write FFFFH to Port 40HFFFFH = 65,535t(1/1.19Mhz) * 65,535 = 55ms

Command Address Data /8

TO IRQ0 TOD Interrupt

MSB LSB

S/C R/W Mode BCD00 0 1 1 0

1.19 MHz

1 1 1 1 1 1 11 1 1 1 1 1 1 1 1

+VCC

Counter #0 (p/o 8254)

55ms1 1

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Ch 6 -

COUNTER/TIMER FUNCTIONSlCT0--Time Of Day Interrupt.

3GATE tied high, always counting.

3Output is a square-wave with a 55 ms period (18.2 Hz).

3Tied to 8259 PIC IRQ0. A rising-edge on the output causes an INTERRUPT TYPE 8, the Time Of Day Interrupt.

3Interrupt Service Routine for IRQ0 increments a dword counter in BIOS Data Area at 40:6c.

»Maintains count of how many timer ticks have elapsed since midnight.

»Can be set or read by BIOS INT 1AH in the PC/AT.

3Interrupt Service Routine for IRQ0 also decrements byte at 40:40H in BIOS Data Area.

»If the count reaches zero, the Interrupt Service Routine issues a command to shut off the disk drive motor if it is on.

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Ch 6 -

8254 COUNTER #1 REFRESH

Write 54H to Port 43HS/C=01=> Counter #1Mode= 010y => Mode 2 (Period Pulse - Asymmetric)

Write 12H to Port 41H12H = 18t(1.19Mhz /18) => 15.6 usec



1.19 MHz

+VCC


0 12H = 18t

0 1

MSB LSB

100000 100000000

15.6us

TO REFRESHCONTROLLER

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Ch 6 -

COUNTER/TIMER FUNCTIONSlCT1--A high output initiates a DRAM refresh cycle.

nGATE tied high, always counting.

nOutput is a period pulse (asymmetric) with a 15.6 usec period to the Refresh Controller.

nThis Refresh Request signal triggers the DRAM Refresh Logic to refresh (dummy read) another Row in DRAM memory every 15.6 microseconds.

nThe output also toggles bit 4 in Port 61 (Port B)3A program can check this bit to see if Refresh is active.

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Ch 6 -

8254 COUNTER #2 SPEAKER

Write 0B6H to Port 43HS/C=02=> Counter #2Mode= 011y => Mode 3 (Square Wave- Symmetric)

Write 0533H to Port 42H0533H = 1331t(1/1.19Mhz) * 1331 =>~897 Hz


TOSPEAKER

MSB LSB


1.19 MHz

0 0 0 0 0 1 10 0 0 1 1 0 0 1 1


1 1

PORT 61HR R R R

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Ch 6 -

COUNTER/TIMER FUNCTIONSlCT2--Speaker Frequency

nThe output from CT2 passes through a Speaker Gate to the speaker where the square-wave produces a tone.

nSpeaker Gate controlled by BIT0, PORT B (PORT 61H).3BIT1 = 0 , CT2 output disabled

3BIT1 = 1 , CT2 output enabled, square-wave output.

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Ch 6 -

BIT/VALUE FUNCTION ACCESS

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

1 = ONBOARD PARITY ERROR

1 = ISA PARITY ERROR

1 = SPEAKER SIGNAL ON

TOGGLES WITH EACH REFRESH.

1 = ISA PARITY ERROR DISABLED

1 = ONBOARD MEMORY PARITY ERROR DISABLED

1 = SPEAKER DATA ON

1=SPEAKER ENABLED

READ ONLY

READ ONLY

READ ONLY

READ ONLY

READ / WRITE

READ / WRITE

READ / WRITE

READ / WRITE

I/O Addr 61H Bit Assignments (Port B)

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Ch 6 -

COUNTER/TIMER FUNCTIONS

n Optional Watchdog Timer (Fail-safe Timer)3Some systems also implement an additional Timer located

at I/O Port 44H.

3An additional 8254 with only Counter #0 used.

3This is Timer 3 in PS/2 & EISA systems.

3The timer watches IRQ0, and if interrupt recognition has been disabled for an extended period of time (NO IRQ0), an NMI is generated.

3The NMI Interrupt Service Routine checks to see if this was caused by a Parity Error or Watchdog Timer and the Operating System can take appropriate action.

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Ch 6 -

8254 COUNTER / TIMER REVIEW

OUT 61

Counter 0

Counter 1

Counter 2

1.19MHz

÷12

0

1

Speaker Data

÷24

5

Refresh (15.6 us)

IRQ0

OUT/IN 40

OUT/IN 41

OUT/IN 42

IN 61

14.318 MHz

"1"

"1"

CLK

ENA

CLK

ENA

CLK

ENA

TimerControlOUT/IN 43

(Time of Day Counter - 18.2 Hz)

ISA BUS84OSC=14.318 MHz

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Ch 6 -

8742 Keyboard 8742 Keyboard ControllerController

DescriptionDescription

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Ch 6 -

8742 KEYBOARD CONTROLLER

Data Bus

8742system

keyboardu controller

COLOR*MGTESTKEYLOCK

IOWC*IORC*8742CS*A2RESET*

KBIRQDETURBOKB-RESETKB-A20GATE

KEYCLK

KEYDAT

Buffer

Buffer

8

ROMBIOS

Translate ScanCode to give

ASCII Character

(IRQ1 I.S.R).

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Ch 6 -

8742 KEYBOARD CONTROLLERlThe INTEL 8042 OR 8742 MICROCONTROLLER is a

functional microcomputer on a single chip that requires only a 12 MHz clock input.

lThe Microcontroller contains:nA CPU Core with an instruction set of more than 90

instructions.

n2K of ROM

n256 byte of RAM

nTwo I/O Ports

nAn 8 bit bi-directional Data Bus to interface to a CPU.

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Ch 6 -

8742 KEYBOARD CONTROLLERlThe 8742 Keyboard Controller interfaces the Keyboard

to the PC System Board.nIt converts the Serial Data SCAN CODES received from

the Keyboard & Mouse to 8-Bit parallel data and sends them to the PC System Board.3Keyboard & Mouse use 2 independent Serial Interfaces.

nIt is the Interface for sending commands and receiving status from the Keyboard.

nIt provides additional I/O Ports for miscellaneous functions such as generating the Keyboard Interrupt & and reading the KeyLock Status.

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Ch 6 -

8742 KEYBOARD CONTROLLERlThe Keyboard Controller communicates with the

Keyboard using a Serial Interface:n1 line for Key Clock

n1 line for Key Data

lThe Keyboard Data is in a properly formatted 11 BIT serial stream to/from another microcontroller in the Keyboard.nStart (Logic 0), 8 Data, Parity (Odd), Stop (Logic 1).

lNOTE: A detailed discussion of the communication with the 8042 is beyond the scope of this course.

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Ch 6 -

8742 8742 CONTROLLER CONTROLLER

PORTSPORTS

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Ch 6 -

8742 CONTROLLER PORTS

ControllerStatus

ControllerCommand

Keyboard Scan Codes& Kybd Cmd Results

8742 Cmd Data& Keyboard Data

OUT 64

OUT 60

IN 64

IN 60

KEYBOARDCONTROLLER

Rev. 1.0 Sys MFG T/ED 4/25/2003


Ch 6 -

8742 CONTROLLER PORTS

01234567PORT 64 Read: Status Register

Par

ity e

rror

Rec

eive

tim

e-ou

t

Tra

nsm

it tim

e-ou

t

Key

boar

d un

lock

ed

Last

inpu

t: C

md/

Dat

a

Sel

f tes

t fla

g

Inpu

t buf

fer

full

Out

put b

uffe

r fu

ll

01234567PORT 64 Write: Command Register

20h:3Fh Read Cmd byte60h:7Fh Write Cmd byte

AAh Self testABh Test interfaceACh NO-OPADh Disable keyboardC0h Read input portD0h Read output portD1h Write output portE0h Read test input port

E1h:EFh ReservedF0h:FFh Output pulse

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Ch 6 -

8742 CONTROLLER PORTSlThe 8742 uses two ports in the PC/AT I/O space:

PORT 64H and PORT 60H. nPORT 64H is used as both a COMMAND Port (Writes)

and STATUS Port (Reads) for the 8742.3Reads from Port 64H provide the current state of the

keyboard controller.

3Writes to Port 64H are interpreted as Commands by the microcontroller and go to a write only Register in the 8042.

»Writes to Port 64H set the CMD/DATA Bit (Port 64 BIT 3) to 1.

3Examples of common commands:»AAH - Self Test: 55 is placed in the Output Buffer (Port 60) if

PASS.»D1H - Writes the next byte sent to Port 60 to the Local Output

Port.

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Ch 6 -

8742 CONTROLLER PORTS (cont.)lPORT 60H is the data port and is used for:

nReading the Keyboard Scan Code information 3Should only be read from after status port bit 0 (OBF) = 1

3Normally read by the IRQ1 Interrupt Service Routine.

nSending Data & Commands to the Keyboard.3Writes to Port 60H set the CMD/DATA Bit (Port 64H BIT 3)

to 0 & pass the Data through the keyboard controller to the Keyboard

»Unless the 8742 is expecting a Data Byte following a command to Port 64H.

nCont. next page

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Ch 6 -

8742 CONTROLLER PORTS (cont.)lPORT 60H is the data port and is used for:(Cont.)

nReading & Writing the the Local Ports.

3Write: After sending the appropriate command to Port 64 (e.g. D1H), the 8742 transfers the next byte written to Port 60 to the Local Port.

»Should only be written to if status port bit 1(IBF) = 0

3Read: After sending the appropriate command to Port 64 (e.g. COH, DOH), the 8742 transfers the contents of the Local Port to the Input Buffer which can be read at Port 60.

»Should only be read from after status port bit 0 (OBF) = 1

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Ch 6 -

8742 KEYBOARD CONTROLLER

Mse Clock In

KEYBOARD CONTROLLER

Status REGPort 64 READ

Input Data BFRPort 60/64 Write

Output Data BFRPort 60 READ

8

Lo

cal P

ort

1L

oca

l Po

rt 2

Hot ResetA20 Gate

Kybd IRQ

Kybd Clock OutKybd Data Out

Kybd Data In

Color/MonoKybd Lock

Test Port

Kybd Clock In

Mse Data In

Passwd En

MFG Test

XTAL12 MHZ

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Ch 6 -

8742 KEYBOARD CONTROLLERlThe 8042 microcontroller contains two extra I/O Ports.

nOne Input Port (Local Port 1):3Gets Kybd Data From Kybd, Reads KeyLock Status, etc.

3Read at Port 60 by first sending the “Read Input Port” (C0H) Command to Port 64.

nOne Output Port (Local Port 2).3Sends Keyboard Data From 8742 to Keyboard

3Generates IRQ1, A20 Gate, Hot Reset, etc

3Data written at Port 60 after first sending the “Write Output Port” (D1H) Command to Port 64.

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Ch 6 -

MISC. KYBD MISC. KYBD CONTROLLER CONTROLLER

SIGNALSSIGNALS

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Ch 6 -

MISC. KYBD CONTROLLER SIGNALS

KBD IRQ:

lGenerated when the Keyboard sends a scan code to the 8742 Keyboard Controller.

lWhen the 8742 receives a data byte from the keyboard, the 8742 ROM code:nPlaces the data byte in it’s Output Buffer (Port 60).

nSets the Output Buffer Full flag 3A Read of Port 64 Bit 0 will see a 1.

3The OBF Flag is Reset when Data is read from Port 60.

Cont. next page

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Ch 6 -


lKBD IRQ: When the 8742 receives a data byte from the keyboard, the 8742 ROM code: (Cont.):nAutomatically generates an Interrupt to the PC System

Board (tied to PIC IRQ1).3Generates IRQ by setting Bit 4 of Local Port 2 (KBD IRQ)

3The IRQ1 Interrupt Service Routine reads keyboard controller data port to get key pressed.

»The data read is stored in the 16 word Keyboard Circular Buffer in BIOS DATA Area.

»Both a Scan Code & ASCII Code are stored at one of the 16 locations starting at 40:1E.

»BIOS INT 16 can access the “Key Pressed” from the BIOS DATA Area.

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Ch 6 -


lA20 Gate: nInhibits Generation of the A20 Address Line in Real

Mode making the 80286 and higher processors compatible with the 8088.

nThe 8088 only had A19:0 and could not assert A20. 38088 code that generated an address above 1 MB wrapped

around to low memory.

nAlso know as A20MASK, PASSA20, FORCEA20, etc

nCan be controlled by Software:3HIMEM.SYS, WINA20.386, etc.

nA “FAST A20” is often implemented in chipsets.3PS/2 Port “A” (Port 92) or Port 78 (Not PC/AT Compatible)

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Ch 6 -

lHot Reset: Causes a CPU only reset (System Board not reset).nOriginally used to change the 80286 from Protected

Mode to Real Mode.

nGenerated when “CTL-ALT-DEL” keys are depressed.3Also know as Warm Boot, Soft Reset

nCan be generated by writing “FEH” to Port 64.

lTurbo/Deturbo:nDeturbo slows down the System and emulates the 8

MHz PC/AT.

lMFG TEST: Used to enable special test functions in the manufacturing process (Optional Use).


Rev. 1.0 Sys MFG T/ED 4/25/2003


Ch 6 -

Keyboard Controller Review

8042

Keyboard

Controller

EWQ R T

1 2 3 4 5 Etc.

1

2

Etc.

Keyboard Switch Matrixproduces SCAN CODE

NumLock

CapsLock

Kbd Clock

Kbd Data

12Mhz Clock

RESET#

CE#

WR#

RD#

X-Bus8 Bit

ROMBIOS

Translate ScanCode to give

ASCII Character

KEYLOCK#

COLOR#

IRQ1

A20GATE#

KBDRST# (To CPU INIT Pin)

Misc.Inputs-Outputs

(IRQ1 I.S.R).

NOTE: Port A is PS/2 Port 92Fast A20 - Port A BIT 1Fast Hot Reset - Port A BIT 0

Rev. 1.0 Sys MFG T/ED 4/25/2003


Ch 6 -

SUMMARYWE HAVE DISCUSSED THE FOLLOWING:

l The Real-Time CMOS Clock Chip description.

l The CMOS Address Map.

l Accessing the CMOS RAM.

l The 8254 Programmable Interval Timer description.

l The functions of the three Counter/Timers.

l The 8742 Keyboard Controller description.

l The functions of the Keyboard Controller.

l The I/O Ports associated with the 8742.

l The Misc. Keyboard Controller Signals.

chapter 6 pc peripheral chips - pt 1 rtc, timers, keybd...

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