pcarch-full course-description.ppt...
TRANSCRIPT
Rev. 1.0 Sys MFG T/ED 4/25/2003
PC Architecture For Technicians Level-1Technical Excellence Development Series
Ch 0 - Page 1
Course DescriptionCourse DescriptionPC Architecture for PC Architecture for
Technicians: LevelTechnicians: Level--11Systems Manufacturing Training and Systems Manufacturing Training and
Employee DevelopmentEmployee Development
Copyright © 1996 Intel Corp.Copyright © 1996 Intel Corp.
Rev. 1.0 Sys MFG T/ED 4/25/2003
PC Architecture For Technicians Level-1Technical Excellence Development Series
Ch 0 - Page 2
VIDEO
Host DataHost Addr
TAG
PCI A/D
PCI Ctrl
DRAM
DRAM
MD
MD
TDP CTRL
Plink Bus
ISA BUS SA 19:0SD 15:0
ISA Ctrl
PCI Conn
ISAConn
P54CCPU Host Ctrl
TSC
PIIX
TDP
TDP
UIO
32K X 8 SRAM
BIOS
PC Architecture for Technicians : LevelPC Architecture for Technicians : Level--1 Introduction1 Introduction
Typical System Board w/ T-FX ChipSet
Rev. 1.0 Sys MFG T/ED 4/25/2003
PC Architecture For Technicians Level-1Technical Excellence Development Series
Ch 0 - Page 3
Course DescriptionCourse DescriptionCourse DescriptionlSession-1: 4 hrs (Day 1)
nPretest (0.5 hr) [Optional]
nCourse Description (0.5 hr)
nIntroduction (PC System Overview): Ch-1 (3 hrs)
3iComp (TM) Index; System Bus Standards; Microprocessor Systems; Bus Basics; Bus Cycles; Fetching the initial instructions
Rev. 1.0 Sys MFG T/ED 4/25/2003
PC Architecture For Technicians Level-1Technical Excellence Development Series
Ch 0 - Page 4
Course DescriptionCourse DescriptionCourse DescriptionlSession-2: 4 hrs (Day 1)
nMemory & I/O Maps: Ch-2 (1 hr)3System Memory Organization: 0-1 MB; Base Memory: 0-
640K; Reserved Memory: 640K-1MB; High Memory Area and A20 gate; I/O Address Map; Generic decode logic
PC Memory: (DRAM, ROM, CACHE)
nDynamic Random Access Memory: Ch-3 (3 hrs)3Organization: 0-1 MB; DRAM basics; Rows & Columns;
DRAM timing; EDO DRAM; SIMM/DIMM; Interleaving; DRAM Refresh
Rev. 1.0 Sys MFG T/ED 4/25/2003
PC Architecture For Technicians Level-1Technical Excellence Development Series
Ch 0 - Page 5
Course DescriptionCourse DescriptionCourse DescriptionlSession-3: 4 hrs (Day 2)
nQuiz/ Review (0.5 hr)
PC Memory: (DRAM, ROM, CACHE)(Cont.)
nSystem Board ROM: Ch-4 (1 hr)3System Memory organization: 0-1 MB; ROM contents:
POST/BIOS overview; FLASH Memory chip organization; Recovery BIOS procedures; FLASH Memory pin description; Using an O’scope to check Flash data.
nCache Systems: Ch-5 (2.5 hrs)3Cache terms; Basic Cache operations; Cache architectures:
Direct Mapped; Set Associative; Read policies: Look-Aside; Look-Through; Write policies: Write-Through; Write-Back; Inquire Cycles; Cache terms matching exercise.
Rev. 1.0 Sys MFG T/ED 4/25/2003
PC Architecture For Technicians Level-1Technical Excellence Development Series
Ch 0 - Page 6
Course DescriptionCourse DescriptionCourse DescriptionlSession-4: 4 hrs (Day 2)
PC Peripheral Chips - Pt 1:
nRTC (CMOS RAM): Ch-6 (<1 hr)3RTC description; RTC address map; Accessing the RTC
nTimers- (PIT): Ch-6 ( <1 hr)38254 description; TOD; Refresh; Speaker
nKeyboard Controller: Ch-6 (1.0-1.5 hr)38742 description; 8742 I/O Ports; Misc. Controller signals.
PC Peripheral Chips - Pt 2:
nDMA (Direct Memory Access): Ch-7 (1 hr)3Hardware description; DMA operation overview; DMA
transfer sequence; DMA Page addressing
Rev. 1.0 Sys MFG T/ED 4/25/2003
PC Architecture For Technicians Level-1Technical Excellence Development Series
Ch 0 - Page 7
Course DescriptionCourse DescriptionCourse DescriptionlSession-5: 4 hrs (Day 3)
nQuiz/ Review (0.5 hr)
PC Peripheral Chips - Pt 3:
nProgrammable Interrupt Controller: Ch-8 (3.5 hrs)
3Sources of Interrupts; Basic Interrupt operations; The Interrupt Vector Table; CPU & PIC operation during an Interrupt; Example Interrupt Service Routine; Hardware Interrupts associated with the PICs; NMI hardware interrupt logic; Software Interrupts & Exceptions
Rev. 1.0 Sys MFG T/ED 4/25/2003
PC Architecture For Technicians Level-1Technical Excellence Development Series
Ch 0 - Page 8
Course DescriptionCourse DescriptionCourse DescriptionlSession-6: 4 hrs (Day 3)
nIntroduction to Assembly Language: Ch-9 (4 hrs)
3Vocabulary; Little-Endian Addressing; Pentium Real Mode register description; Real Mode address generation: Segments; Offsets; Basic instruction set: [Data Transfer, Arithmetic, Logic, Shift & Rotate, Control & Transfer, Repeating]; Procedure example; Assembly Language exercise; Program example
Rev. 1.0 Sys MFG T/ED 4/25/2003
PC Architecture For Technicians Level-1Technical Excellence Development Series
Ch 0 - Page 9
Course DescriptionCourse DescriptionCourse DescriptionlSession-7: 4 hrs (Day 4)
nQuiz/ Review (0.5 hr)
nPentium (TM) CPU: Ch-10 (3.5 hrs)
3Pentium block diagram; Pentium register description; Microprocessor bus description; Pentium Byte Enables; Pentium CPU addressing examples; Ready logic; Bus Cycle definitions; Generic decode logic; Microprocessor Bus Cycle timing: Single & Burst cycles; Pentium pin description; Pentium address/data bus exercise.
Rev. 1.0 Sys MFG T/ED 4/25/2003
PC Architecture For Technicians Level-1Technical Excellence Development Series
Ch 0 - Page 10
Course DescriptionCourse DescriptionCourse DescriptionlSession-8: 4 hrs (Day 4)
nBIOS and DOS: Ch-11 (1.5 hrs)3Functional Hierarchy; ROM BIOS description; POST &
BOOT sequence: POST Codes, BEEP codes; BIOS Interrupts; BIOS Services examples; Introduction to DOS Functions; DOS BOOT sequence overview
nISA BUS Overview: Ch-12 (1.5 hrs)3ISA Bus background; Typical system bus cycles; 8/16 bit
I/O Channel signal description; 8/16 Bit ISA bus cycle description; conversion cycles
nTest Methods Overview: Ch-13 (1 hr)3MTA Diagnostics overview; Schematic use & signal tracing
Rev. 1.0 Sys MFG T/ED 4/25/2003
PC Architecture For Technicians Level-1Technical Excellence Development Series
Ch 0 - Page 11
Course DescriptionCourse DescriptionCourse DescriptionlSession-9: 4 hrs (Day 5)
nQuiz/ Review (0.5 hr)
nPCI BUS Overview: Ch-14 (2.5 hrs)3Bus standards: ISA, EISA, VL BUS, PCI; PCI Bus arch.
overview; Basic PCI bus cycles; Required PCI Bus signals; PCI commands, Parity, Subtractive Decode, and PCI Arbitration; PCI Cfg Access:[ PCI Cfg registers, PCI Cfg mechanism Type -1, PCI ID Select line usage]
nCurrent PCI ChipSet Overview: Ch-15 (1.0 hr)3Overview of example PCI ChipSet Implementation;
82430FX PCIset: [TSC] - 82437FX System Controller, [TDP] - 82438FX T Data Path, [PIIX] - 82371FB PCI-ISA-IDE Xcellerator, Overview of the PC87306 “Ultra I/O”
Rev. 1.0 Sys MFG T/ED 4/25/2003
PC Architecture For Technicians Level-1Technical Excellence Development Series
Ch 0 - Page 12
Course DescriptionCourse DescriptionCourse DescriptionlSession-10: 4 hrs (Day 5)
nIntroduction to DOS: Appendix A (1.5 hrs)3PC Operating Systems; Components of MS-DOS; Using
DOS Internal & External commands.
nWindows 3.1 Overview: Appendix B (1.5 hrs)3Windows Screen; Notepad; the Clipboard; Shortcut keys
nFinal Test (1 hr)