chapter 7 digital switching

8/2/2019 Chapter 7 Digital Switching

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CHAPTER 7DIGITAL SWITCHING SYSTEMSA switching system s called digital when tlrc input to and output fiom the swiiching systen can directly supporlthe digital signal. Many basic element's f the digital switching systemand its operation are vell sinilar 1o thesloredprogramcontrol (SPC)switchingsystem.The function of the digital-switchingnetwork rs to comect pails of chafirels. So that rnforrnatron nivirg al thesultching center n a particularchannelon one PCM multiplex systen can be passed o some other channelon anoutgoingPCM mr hplex systems.To achieve he switching two types of switchingcan be used.These are called

dn1e wrtcling and spaceswitching.In digiial datacommunication analogor digital signal) a lundanental requireNent s that the recei|cr should kno\rthe starting ime and duration of eachbit that t receives.To meet this requirementasynchronous nd synchfonolrsllansn11sslonre used, t^ nodefn dig'tal swiiohing system Electronicswitcling systen l) empioys a number of processors.t rs pufelyclectronicri1operationand the switching process s by time divisjon/ digrtal transnission. Ihe i)pe of control lsstoledprogramcommon contol and he net\,vork sesPCM. Figure 7.I shows he digital slvitchingsystem.

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Figxre 7.1. Digital s*,itching system7.1 Spacedivision s\YitchingIn spacedivision switching, he paths n the circuit are separatedrom emh other spalially. A crosspoints',{itch srefened to us as a spacedivision switch, because t moves bit stream tom one cfcuiirbus to another. or largegroup of outlets, considemblesavings n total crosspoints an be achieved f each nlct can accessonly a limilcdnunber ofoutlets. Such situation s called inited availabiliq'.Bt overlapping he available ontlet groups lor vadous inlet gloups, a technique called "gradlng" is established.

Rectangular rosspointarray s an exampleofgrading.11 s inefiicient to build conplete exchanges n single stages.Single stagecan only be usecl o interconnectoneparticular nlet outlet pair. Also the number of crosspointsgro\,r' s the squareof the inputs for gradng. N (N-1)/2Iorat angulal araJ' and N (N-1) for a squarearray.Also the large nunbel of crosspoints n each nlei and outleiline rnply a large anrountofcapacitive loadingon the message aths.Therefore, i is usu.rl1{) uild cxchangcs n 2or 3 stages o reduce he number of crosspointsand to provide altemativepaths.The shadng ol closspornts brpotentialpaths hrough he switch is accomplrshed y multiplestageswitching.I'igrLrc7.2 shows he 3 stageswitching skucture o accommodate 28 nputs and 128outputs$'rth 16 first and astsrage.


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Figule 7.2 Tlnee stages\:r.rtchrngtluctureThe structufeprovidespath for N inlets and N olrtlets.The N input lines are drvrded nto N/ n groupsofn lincs eechLach group oln mputs s accommodated y an n- input, k-output nlatrix. I'he outpul matdces are identical o $elnput rnatlices except hey are reversed.The intermediate tagesare k in number and N,rn nputs and N,rnoutputs.Thc inlcBlagc connectio1$ re oftm called unctors.Each of the k pathsutilizes a scparatcccnter slageanay. Anarbilrar)' npu! can find k altemateoutput.Thus nultjsiage shuctureprovidesaltematepaih.Also ihlj sr'itc|jng linkis connectedo a limited number ofcrosspoints.This enables hc minimized capacitjve oading.l \ e t o . a l . r m b e r o r o - . p o r l . N , l o _ " t d g eN.=2NK+K(N /n ) l 17 .1 l$,hereN = number ol ulets-outputsn = sirc olcach inlet-outletgroupk = numbefoiseoond stage2NK : nunber of cmsspojnts r1 "' anal2'd stage(Nm)r.- number olfioss points n eacharray olsecond stagek(Nin)'= nunbcr ofcross points n second tageIn space division s\.rtching crosspoirltsare used to establisha specific connection bctween 2 subcribc^. lhrcrosspomts f multistagespaceswitchesassigned o a particularconnection s dedicated o thai conncclion or ilsdufation.Thus the crosspoints an not be shared.7.2 Time division switchingTime division s$itching involves the sharing of crosspoints or shorterpeiods of timc. Timc division s*,ilchrDgLrscs in1e division nultiplexing to achieve switchng. Two popular methods that afe used in trme divisionLnulliple\ingare: ime slot interchange lsl) and'lDM bus. In ordinary ime dinsion multipLexjng. he data eacheslhe ou4rutrn the sameorder- s they sent.But TSI changes he ordering of slotsbasedon the desiredconnections.The demultiplexerseparates he slots and passes hem to the proper outputs.The TDM uses a control Lrnit.Thecontrol unit opensand closes he gatesaocording o the switchingneed.Figure 7.3 showssimple analog ime division swjtching structue. The speech scarriedas PAM analogsamples fPCN4 igi lalsanples. ccuring at 125ps Dtervals. heDPAM samples res\\ , i1chedn a i lnedivisionmanner.|eswiichrng is called analog trme division switching. If PCM binary sanples afe switched, hen the s$'ilching isc.rllcd digital time division switching. A srngle snitching bus suppons a multiple number of connectrons yrntefleavingPAM samples ionl recerve ine jnterlacesto fianslnjt ljne interl-aces. here two cyclic control slores'1hcfirst conijol slorc controlsgaiingolinputs onto the bus one samplcat a limc. The secondconlrol slore opcratcsin slrchronism widl the first and selects he approp ale output 1me for each input sample. lhe selection ofin1et,'outlets controlledby variousways.


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oI'igue 7.3. Analog time djvision switchingstructureThe L\cliL co trol rs organized by using Modulo-N counter and k to 2' decoder as shown in Figure 7.4.

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No restricdonson subscribernumber and full availability of ile switching systemcan be achreved y designlngaswitchrngconfigurationwifi conhol memory for controllingboth inieis and outlets.This configuration etened toas nelnory confiolled time division spaceswitch s shown n Figure 7.5.As eachword ofthe control memory has nlet address nd an outlet ad&ess, he conftol memory width is 2 logrN .'Ihe confol memory words are readoutone after another.The modulo counter s updatedat the clock rate. For thepath scllLpof i- th niet andj th outlet, the addresses re entel-edn control memory and path is nlade. Then thelocation s markedbusy. When conveffation s terminated, he addrcsses re replacedby null valuesand ocaliorl sHence

C l - ( 1 2 5 / t , ) p s e clvheres= ti+ tn+ td+ t,

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Decoder I Deccder

ManoryDaiaReg ler MDR)

>lvl^R Memory ddrcssReqsler

Figure7.5. Memory control for both inlet and outletTbe switching natrix above is referred to as time multiplexed swiiching as d1e swltch ln this conliguratior isreplcated once or each ime slot.The digital time divririor?multiplexed signals usually require switching between ime slots as well as betrveenphysrcal lines. The switching between time slots are called time switching. The time division switch can beconuolled n 3 ways.The basic requirement of time division switching is that ihe transler oI inlomation ariving at in a time slot ol oneinput link to other time slot of any one of output 1ink.A completl3 el ofpulses. a1T1l1ngt eachactjve inpui |ne isknown as a fiame. The ftame rate is equal to the sample mte of each ine.A lime switch opemtesby writing data nto and reading data out of a single rnemory. Tn the process heulonnalion in selected rme slots s interchansed s shown n Fisure 7.6.

I g- fe - . r r . I r r re 'nt rrterchangeperatrorLn I SI operation, nputs are sequentrally ontolled and outputsare selectirly controllednemory locations,eachsize is the sameas ofsingie time slot, The RAM have several


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Figure 7.7 shows he genenl arrangement fthe time division switching.

Flgur-e .7. lmctional diagramofthe time divisionswitchingThe serial o parallelandpalallel to serialconvertera1e sed o wnte the data l1to he mcmory and read he dataoulof the memory. For convenience, MDR are sho$n, but MDR is a single register.Gating mechanisn rs used oconnect he inlet/outlet o MDR.The input and output lines are connecled o a high-speedbus through nput and output gates.Each inputgate s closedduing one ofthe four time s1ots.During the same ime s1ot, nly one nput gate s closed.This parf olgatesallows a bulst of data to be transferred rom one inpui line to a specific output line through the bus. Thecontrol tulit opensandcloses he gatesaccording o switchltg need.Tbe time division time switch may be controlled by sequential \\.ritelrandonr rcad or fandonlwrrte/sequentlalead. Figure 7.8 depictsboth modes of operationand ndicateshow the memories arc accesscdotfanslatenfomation ftom time slot 2 to time slol 16. Both methodsuse a cyclic control.Ligure 7-8(a) mplies that specific memory locationsare dedicated o respectivechannelsof the incomingTDM l1nL.

-NT Illl l va-l t NI-- l

Figure 7.E a) Sequentialwrite/random ead,(t ) random*rite/sequentjal l ead


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Data are stored n sequentialocations n memory by incrementingmodulo N counler with every ilne slot.Thus ncoming data during time slot 2 is stored n the second ocationwithin the memory. On output,information etrieved iom the control storespecifieswhich addresss to be accessedor thatparticulartime slot.Thus 16-thword ofcontrol storecoDtainshe number 2, implying tlat the contentsofdata sloreaddress is transfer ed to the output ink during outgoingslot 16.Randomwite/sequential read modeofoperation s opposite o that ofsequontjalwrite/raldon r.ead.Incoming dataare written into the memory ocationsas specifiedby the control storebLltoutgoingdata ueretrievedsequentially nder control ofan outgoing ime slot counter.The dala receivedduring time slot 2is written directly nto data storeaddress16 and t is retrieveddlLringoutgoingTDM channelnumber 16.7.3Two dimensional igital switchingCoinbination f the ime andspacoswitcheseads o a configurationhatachieved oth ine slot nterchangendsamplc $'itching crossmlnl$. Theseslructures lsopermita largenumberoI simultaneousonnectionso bcsupportedbr a given echnology. argedigital switchescquireswitching perationsn both a spacc nd a tinrdi]nension.The ncoming ndoutgoingPCM ighways arespatially eparate.he s\\'iiching etworkmusrbe able10r'eceilePCM samplesiom one time slot and retransmithem n a dlfferent ime slot. This is knownas lirncswitchjng. hus heswitching et\:r,ork ustpedo1m othspace nd imeswitching.Thespace witching nd 'me switchingmaybe accomplishedn rnanyways.A two stage ornbinationwitchmaybe organizedwith time switch as first stageand spaceswilch as second tage01 vice versa. The fesultingconligurationsre called ime space TS.)or space ime (ST) switchesespecti\,ely. hreestage ime and spececonbinations fTST and STSconfigurationsremorepopularand lexible.Very largcdivisionswitchesncludcmanycombjnationsl time andspace witches. ).'tricalonfiguratronsreTSST,TSSSST ndTSTSTSTS. heseswrtchesuppofi 0000 inesor moreeconomically.Thegeneral lockdiagrams shown n Figure7.9Thc marn askof the switching afi is to jnterconnectan ncoming rmeslot andan outgoing ime siot.The unitresponsiblcbr this unctrons thegroupswitch-In Figure7.9, he subscrjber akes 1ocal all o B. The controlunrthasassignedlot 3 to thecallon its rvay nlothegfoupswitch, nd imeslot on ts way outofthe groupswitch toB). This s maintainedulingcntirecalt.

Figure 7.9 Cencralblock diagramofcombined switching52a.e rt'i|.fr (Figure7.10, usesa spacearay to provide switchrng.Generally hc spaceswitch consjstsof a matrixM x N swilchingpoints where M rs numberofinlets and N is numbel ofoutlets. A connectionbet\\,een n inlet andan outlct is madeby simple ogic gates AND gates).As logic gatesarc unidirectional, $o paths hroughswiichlngnutfix n,ust be established o accommodate a two-way conversation.The logic gate array can serl'e fbrconcentration, xpansionor distr:ibution ependingon M is larger,smaller or equal o N. Fi$re 7.10 sho$'sonly l\,'ojce irection.Flowever, he corresponding omponentsare avajlable or the oppositedirection oo.A nrnnberof M, ofX slot muftiplexers,providethe nputs and he outletsare connected o N. X slot demultiplexers.The gateselectmemory has X locations.The word containing nlomation aboutwhich crosspoint is to be enablcdis decodedby the translator-During each ntemal time s1ot,one qoss lroint is activated. n the shili to the nexiinlerval lime slot- thc contol memory is incrementedby one step, and a new dosspoinl pattun is fbrned in the

t \ . / lI ' x - - l


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Figure 7.10. SpaceswitchTimes.,Nitch 'igure 7.11 shows he block diagramof time switch.Each ncomng time slot is stored n sequmce n a speechmemory(SM). The control m,jmot' (CM) detennines nwlich order he time slots arc to be read iom SM-

Fig 7.1i . Time switch.'Iine ,pdce (TS)Srritchirg consistolonly two stages Figure 7.12).The spaceanays have N inlcls and N oullets.lor each nlet line, a time slot interchanger\.rtbT slots s introduced.Each TSI is provided \'ith time slot mcmorics(not showr). Simjlarly a gateselectmemoryneeds o be povided for the spacearray(not shown).The uansmission of signals s calaied out from sender o receiver tltough multiplexer input and demultiplexefouFut. A hybrid anangement s needed o isolate he transmitted ignal iom ile receivedsignal.Tlrc basic unclronofthe time switch is to delay infomation in arriving time slots until the desired outpnt time slot occurs.Let the communication ake place between subscriberA and B. A is assigned ime slot 2 and line 7 and B rsassjgned ime slot 16 and ine 11.Then the signalmoved fion time slot 2 to time slot 16 by the time slot exchangefand is transfered from line 7 to line 11 in the space array. Similarly, the si$al originated by B is moved fiom slot16 o slot 2 through ine 11 to 8.

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Figure 7.12.Time Space TS) switchingThe cyclic control andgateselectmemory contains nformationneeded o specify he spacestageconiguratron lbreach ndividual ime slot ofa ilame. The time stagehas o prcvide decays anging ftom one time slot to a full lianre.Dulng eachoutgoing ime s1ot, ontrol nlomation is accessedhat speclfies nterstage ink numbel to output ink.Dunng other ime slots, he spaceswitch s completely econfigured o supportother conneltions-Let each ime slot interchangerhave T slots. Il the spacearray is a N x N, then thl3 simultaneous onnectjonspossible s NT. IIT=128 and N=16, 204E connections an be supported.This slructure s not free olblocking. Theconfol store s a parallelend aroundshift register. fspace array s at the inlet side and time switch is at the outputside, he smrchrre s referred o as space-timeST) switching.ST and 1S arangenents a1eeqLrally ffective.'fhe blockingprobabiliry ofTS switching s calculated s ollows:

Theprobabilityhata subscriber is active= p/ T [7.4]wherep = fiactionof time hata parlicularink is b symeasurodn Erlangs.I .ndmber - nme lors n a l idme.The n]ultiplestages vercomehe limitations f the ndividuals{.itches nd cost savings an alsobe achieved.TST,STS, TSST, TSSSSTand TSTSTSTSTSTSTSrc the switchingsysten configuraiions sed n digitalswitching ystem-In STS tNitching,he time stage s sandwichedetweenwo space rrays.Figure7.13 shows le STSswrtchingretworl


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l rgu - .11fhep | |nc ip leITST.u ' r c \ i ng .The functional lock diagramwhich explains he ransfer f signalsrom inlet o outlel s shown n Figure7.15.The infornation arriving at the incoming link of TDM channel is delayed in the inlet times stage until anappropriate aththrough he spacestage s available.Then the information s transferred hrough he spacestageotheappropdateutlet ime stage.Here he nforrnations helduntil thedesired utgoingime slol occurs. ny spacestage rme slot can be used o establish connection. he spacestageoperatesn a t1medividedfashion,independentlyf the extemalTDM links.Therearemanyaltemative aths etween prescibed nput andoutputunlike a two stagenetworkwhich hasonly one ixed path.

TONl

1 1 6 2 l 1 2 1 2 1

TDM

J+- r t

Figue 7.15 TST switching tmcture.

chapter 7 digital switching

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