chapter 7. storage components.pdf
TRANSCRIPT
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7. Storage Components 7-1
Chapter 7. Storage Components
Introduction
Storage components store data and perform simple data transformations, suchas counting and shifting.
Registers, counters, register les, memories, etc.
Register : a group of binary cells (FFs) suitable for holding binary informa-tion.
In addition to the FFs, a register may have combinational gates that con-trol when and how new information is transferred into the register.
Counter : a register that goes through a predetermined sequence of states uponthe application of input pulses.
The gates in a counter are connected in such a way as to produce a pre-scribed sequence of binary states in the register.
Memory unit : a collection of storage cells together with associated circuitsneeded to transfer information in and out of storage.
For example, SRAM & DRAM.
Registers
A register can be viewed as a bitwise extension of a FF.
The simplest of the storage components: inputs, outputs, and a clock signal.
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7. Storage Components 7-2
All the FFs are driven by the common clock signal.
Registers are readily available as MSI circuits, it becomes convenient at timesto employ a register as part of the sequential circuit. The combinational-
circuit part of the sequential circuit can be implemented by any of the meth-ods discussed in Chapters 4 & 5.
D-FFs are normally used for registers.
The register may be enhanced by asynchronous Preset and Clear (Reset) sig-nals, which are not controlled by the clock signal.
Q Q Q Q 0
Register 0 I I I I
123
3 2 1
(a) Graphic symbol
(b) Register schematic
I 3
Q3
Q3
3 D
I
Q
Q
I
Q
Q
I
Q
Q
D
Clk
2 1 0
00
01
D1 12 D2
2
Figure 1: A 4-bit register [Gajski].
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7. Storage Components 7-3
Q Q Q Q 0
Register 0 I I I I 123
3 2 1
(a) Graphic symbol
(b) Register schematic
I 3
Q3
Q3
3 D
I
Q
Q
I
Q
Q
D
I
Q
Q
Clk
2
D2 2
2 1
1 1
1 0
D0 0
0
preet
clear
preset
clear
Figure 2: A 4-bit register with asynchronous Preset and Clear [Gajski].
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7. Storage Components 7-4
To be able to control when the data will be entered into a register, and forhow long it will be stored there before being sent to the output, we add theLoad (Enable) input to form a parallel-load register .
Q3
3
3 D Q Q D Q D
Clk
I
Selector
1 0
I
Selector
1 0
I
Selector
1 0
I
Selector
1 0
Load
3 2 1 0
D 2 2 1 1 0 0
Y Y Y 01Y 2
(a) Graphic symbol
Q Q Q Q 0
Register 0 I I I I 123
3 2 1
Load
(b) Operation table
Present state Load
Next state
Q3 Q Q Q2 1 0
3 2 1 0 I I I I
No change0
1
(c) Register schematic
Figure 3: Register with parallel load [Gajski].
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7. Storage Components 7-5
Shift Registers
A shift register can shift the stored data right and/or left.
(c) Register schematic
(a) Graphic symbol (b) Operation table
Q Q Q Q 0
I
3 2 1Shift
Shift Register
Present state
Next state
Q3 Q Q Q2 1 0
I
No change0
1 3 2 1QQQ
Shift
L
L
Q3
3
3 D Q Q D Q D
Clk
I
Selector
1 0
Selector
1 0
Selector
1 0
Selector
1 0
D 2 1 1 0 0
Y Y Y 01Y 2
Shift
L
2
(c) Register schematic
Q3
3
3 D Q Q D Q D
Clk
I
Selector
I
Selector
I
Selector
I
Selector
3 2 1 0
D2 2 1 1 0 0
Y Y Y 01Y 2
S 0
S 1
3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
R L I I
(a) Graphic symbol (b) Operation table
0 0
0 1
1 0
1 1
Present state
S 0S 1
Next state
Q3 Q Q Q2 1 0
3 2 1 0 I I I I
Q QQ2 1 0
Q Q
Operation
No change
Shift right
Shift left
Load input
I S 0S 1
Shift Register
Q 0QQQ
I I 0 I I I L R
R
L
I
I
3 2 1
3 2 1
Q3 Q Q Q2 1 0
Q3 2 1
Figure 4: Shift registers [Gajski].
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7. Storage Components 7-6
Counters
A counter is a special type of register that counts upward, downward, or inany prespecied sequence.
Clk
Q
Q
D2 2
2
Q
Q
D
1
1 1 Q
Q
D0
0
0
Q3
Q 3
3 D
HAHA HA HA
Output carry
(a) Graphic symbol (b) Operation table
Q Q Q Q 03 2 1
Counter Operations
0
1
No change
Count
Q i C i C i+1 D i
0 00 11 01 1
0 00 10 11 0
(c) HA truth table
E
3C 2C 1C 0C C 4
E
(d) Coun ter schematic
E
Clear
Clear
(d) Logic schematic
(a) Graphic symbol (c) HAS truth table(b) Operation table
Q Q Q Q 03 2 1
Up/Down Counter
Operations
No change
Count up
Count down
0
1
1
X
0
1
D E
Q i C i C i+1 D i
0 00 11 01 1
0 00 11 01 1
0000
1111
0 00 10 11 0
0 01 10 10 0
D E
1111
1111
Clk
Q3
Q33 D
Q3
’
HAS
Q2
Q D 2 2
Q2
’
Q1
Q D 1 1
Q1
’
Q
Q
D0 0
0
Q0
’
HAS HAS HAS
D
E
Output carry
0C 1C 2C 3C C 4
Clear
D E
Clear
Figure 5: Binary up and up/down counters [Gajski].
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7. Storage Components 7-7
(a) Graphic symbol (b) Operation table
Q Q Q Q 03 2 1
Up/Down Counter 0 I I I I 123
D E
Load
Operations Load
No change
Count up
Count down
Load the input
X
0
1
X
0
1
1
X
0
0
0
1
E D
(c) Register schematic
3
I I I I
Load
3 2 1 0
Y Y Y 01Y 2
33 Q D
Clk
Q D Q Q D D 2 2 1 1 0 0
3 QQ Q Q2 1 0
Selector
1 0
HAS
Selector
1 0
HAS
Selector
1 0
HAS
Selector
1 0
HAS
’ ’ ’ ’
E
D
Output carry
Figure 6: Binary up/down counter with parallel load [Gajski].
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7. Storage Components 7-8
BCD Counter
A BCD counter counts in the sequence 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, ....
Q Q Q Q 03 2 1
Up/Down Counter 0 I I I I 123
D E
Load
"0"
"0" "0" "0" "0" Selector 1 0
"0 0 0 0" "1 0 0 1"
Q Q Q Q 03 2 1
Up/Down Counter 0 I I I I 123
D E
Load
"0"
(a) BCD up−counter (b) BCD up/down−counter
Figure 7: BCD counters [Gajski].
Asynchronous Counter
An asynchronous counter counts without an incrementer or decrementer—itsFFs are not clocked by the same signal.
Counting without an incrementer/decrementer is achieved by toggling eachFF at half the frequency of the preceding FF.
FF
changes state only half as often as FF
.
FF
changes state only when FF
goes from 1 to 0, but not from 0 to 1.
A T-FF is very convenient for such an asynchronous counter design.
The counting frequency (speed) will be limited by the number of FFs due tothe linear growth of the clock-to-output delay.
To speed up the counting process, we can use the mixed-mode counter .
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7. Storage Components 7-9
(a) Graphic symbol
Q Q Q Q 03 2 1
Asyn. Counter
(b) Logic schematic3 012
33 Q
Clk
Q Q Q2 2 1 1 0 0
3 QQ Q Q2 1 0
’ ’ ’ ’
1 1 1 1
FF 3 FF 2 FF 1 FF 0
Q Q Q Q
E
T T T T
0t t 1 t 3t 2 t 4 t 5 t 6 t 7
Q
Q
Q
Clk
Q
2
1
0
3
0 1 2 3 4 5 6 7 8
4
2
3
(c) Timing diagram
3
2
E
Clear
Clear
Figure 8: Asynchronous up-counter [Gajski].
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7. Storage Components 7-10
(a) Synchronous counter with 4−bit asynchronous slices
(b) Asynchronous counter with 4−bit synchronous slices
Q Q Q Q 03 2 1Q Q Q Q 03 2 1
Enable
Clk Reset
Syn. Counter Syn. Counter
Q Q Q Q 03 2 1
Asyn. Counter
Q Q Q Q 03 2 1
Asyn. Counter
Enable
Clk Reset
E
Clear
E
Clear
E
Clear
E
Clear
Figure 9: Mixed-mode up-counter [Gajski].
Register Files
A register le has
registers of FFs each.
The registers are arranged as a 2-dimensional array of register-le cells(RFCs).
In addition, it has read/write decoders and output driving logic.
Writing is controlled by the Write-Enable (WE) signal.
At any time, we can write into only one register (row), unless it hasmultiple write ports.
Reading is controlled by the Read-Enable (RE) signal. At any time, we can read from only one register, unless it has multi-ple read ports.
Reading from and writing into the same register at the same time nor-mally is not allowed.
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7. Storage Components 7-11
The primary advantage of a register le is regularity , which reduces routing(wiring) complexity.
(b) Graphic symbol
(c) Logic Schematic
RFC
RFC
RFC
RFC
3 I 2 I 1 I 0 I
3O 2O 1O 0O
0WA
WA1
WE
2−to−4 writedecoder
0
3
2
1
0
1 RA
RA
RE
0
3
2
1
2−to−4 read decoder RFC
RFC
RFC
RFC
RFC
RFC
RFC
RFC
RFC
RFC
RFC
RFC
WA
WE
RARF
n
O
RE
n n
m
m
I
Clk
X2 m
Q D
Clk
RFC
Input Output
Read select
Write select
(a) Register file cell
Figure 10: Register le with 1 write port and 1 read port [Gajski].
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7. Storage Components 7-12
(a) Register−file cell (b) Graphic symbol
(c) Logic Schematic
RFC
RFC
RFC
RFC
3 I 2 I 1 I 0 I
3 2 1 0
0WAWA1 WE
2−to−4 writedecoder
0
3
2
10
3
2
1
2−to−4 read decoder RFC
RFC
RFC
RFC
RFC
RFC
RFC
RFC
RFC
RFC
RFC
RFC
0
3
2
1
2−to−4 read decoder
1 RAB0
RAB
REB
10
RAA RAA
REA
3 2 1 0 A B A B A B A B
WA RF
n
nn
m
m
I
n
m
A B
RAA
REA
RAB
REB
WE
Clk
2 mx
Q D
Clk RFC
Input
Write select
OutA
OutB
Read select (port A)
Read select (port B)
Figure 11: Register le with 1 write port and 2 read port [Gajski].
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7. Storage Components 7-13
Random Access Memories (RAMs)
A RAM is organized as an array of
rows with bits stored in each row.
The size of the RAM is
bits—it has
address lines,
input datalines, and output data lines (see Fig. 12).
The input data lines can be the same with the output data lines, i.e., thedata lines can be bidirectional.
For a commodity RAM, , and = 1, 4, 8, 16, 0r 32.
A memory cell (MC) can be considered as a clocked D latch with an ANDgate and an output driver (see Fig. 13(a)).
For a static RAM (SRAM) , MC is constructed by 6 transistors, usingcross-coupled inverters to serve as a latch, and implementing the inputAND gate and the output driver with one transistor each.
For a dynamic RAM (DRAM) , MC is constructed by only 1 transistor.
The latch is implemented by a capacitor. It needs to be refreshed periodically. It has high density (therefore low cost).
The RAM also has a Chip-Select (
) input and a Read/Write Select (
)input (see Fig. 13(b)).
The input sometimes is denoted as
.
Both SRAM and DRAM are volatile memories , i.e., their content is lost if the power is shut down.
ROM, PROM, EPROM, EEPROM, and ash memories are nonvolatile .
The delay time from address input to data output (
in Fig. 14) is thememory access time .
The address/data setup time and hold time are shown in Fig. 14.
We can connect several memory chips to get one of longer words (Fig. 15),or connect several memory chips to get one with more words (Fig. 16).
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7. Storage Components 7-14
(a) Memory address and content
(b) Graphic symbols
2 −2
2 −1n
n
0 ... 0 0 0
0 ... 0 0 1
0 ... 0 1 0
0 ... 0 1 1
0 ... 1 0 0
0 ... 1 0 1
0 ... 1 1 0
0 ... 1 1 1
1 ... 1 1 0
1 ... 1 1 1
0
1
2
3
4
5
6
7
m bits
0 1 1 ... 0 1 0 0
0 1 1 ... 0 1 0 0
1 0 1 ... 1 1 0 0
1 0 1 ... 0 0 0 1
0 1 1 ... 0 1 0 1
0 1 0 ... 0 1 0 1
1 1 0 ... 0 0 1 1
1 0 1 ... 0 0 0 1
0 0 0 ... 0 0 1 0
1 1 1 ... 0 1 1 0
Memory content
Binary Decimal
Memory address
... ... ...
2 m RAM A 1
0
A
A
CS
1 0
n
. . . . . .
. . .
. . .
RWS
m−1
n−1
I/O I/O I/O
x
. . .
A
I I 1 I 0
1
0
A
A
CS
1 0O O O
n
. . .
. . . . . .
. . .
. . .
RWS
m−1
m−1
n−1
x2 m RAM
Figure 12: Random-access memory (RAM) [Gajski].
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7. Storage Components 7-15
(b) Memory schematic
Q D Input Output
MCC
Row select
Write enable
0
1 A
A
12 03
0
3
2
1
2−to−4addressdecoder
MC
MC
MC
MC MC
MC
MC
MC MC
MC
MC
MC MC
MC
MC
MC
RWS
CS
IO IO IO IO
Writeenable
(a) Memory cell
Figure 13: RAM organization [Gajski].
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7. Storage Components 7-16
RWS
(b) Write cycle timing
(a) Read cycle timing
0t t 1 t 3t 2 t 4 t 5
Access time
Valid data
Valid address
Output disable−time
Output enable−time
Output
hold−time
CS
Address
Data
0t t 1 t 3t 2 t 4 t 5
Valid data
Valid address
RWS
CS
Address
Data
Datahold−time
Addresshold−time
Write−pulse width
Addresssetup−time Data setup−time
Figure 14: RAM timing [Gajski].
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7. Storage Components 7-17
I
O
M 3
I
O
M
I
O
M
I
O
M 012
8 8 8 8
32
14
8 8 8 8
32
CS
RWS
A
Input bus
Output bus
A
CS
RWS
A
CS
RWS
A
CS
RWS
A
CS
RWS
Figure 15: A RAM design using RAMs [Gajski].
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7. Storage Components 7-18
I
O
M 3
I
O
M 0
I
O
M 1
I
O
M 2
14
RWS
2
Input bus
Output bus
A
A
CS
RWS
A
CS
RWS
A
CS
RWS
A
CS
RWS
2−to−4 Decoder
3 2 1 0
Figure 16: A RAM design using RAMs [Gajski].
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7. Storage Components 7-19
*Push-Down Stacks
A push-down stack (or simply stack ) is a memory component with limitedaccess—data can be accessed through only one location (i.e., the top of thestack).
When data is to be stored, it is pushed on the stack and stays on top of others.
When data is to be fetched, it has to be in the top position before it canbe popped out of the stack.
A stack can be implemented by shift registers, with an up-down counter todetect full/empty stack as shown in Fig. 18.
It can also be implemented by a RAM—less expensive for a large stack, butneed two pointers (implemented by counters) as shown in Fig. 19.
TopTop − 1
Top − 2
Top − 3
34 23
empty
empty
34 23
empty
empty
45 34
23
empty
(a) Stack content
before 45 ispushed down
45 45
(b) Stack content
after 45 ispushed down
(c) Stack content
after 45 ispopped up
Figure 17: Push-down stack operations [Gajski].
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7. Storage Components 7-20
Reset
S 0
S 1
Reset
S 0
S 1
Up−Down Counter Reset D E Set
Push/Pop
IN
IN
0
m−1
0
m−1OUT
OUT
Empty
Full
Enable
(d) Stack schematic
Reset
03 2 1
I
Q Q Q Q
SRwPL L I R
03 2 1
I
Q Q Q Q
SRwPL L I R
03 2 1Q Q Q Q
...
...
. . .
"0"
"0"
(a) Operation table (b) Control table
Push/Pop
X
0
1
0
1
1
E
X
0
1
0
1
1
Counter controls
D
Shift register controls
0
1
1
0
1
0
S 1 S 0 EnableOperationsPush/Pop
X
0
1
0
1
1
No change
Push
Pop
Enable 1 0
Counter outputs
Q QQ 2
00001
00110
01010
Empty Full
10000
00001
(c) Output table
Control logic
Output logic
Figure 18: A 4-word stack implemented by shift registers [Gajski].
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7. Storage Components 7-21
(c) Stack schematic
Reset
Push/Pop
Empty
Full
I/O bus
D E Reset
Top Top−1 D E Set
Selector S
1K RAM
A
CS RWS
OperationsPush/Pop
X
0
1
0
1
1
No change
Push
Pop
(a) Operation table (b) Control table
Push/Pop
X
0
1
0
1
1
X
0
1
0
1
1
D
0
1
1
0
1
0
S CS RWS
Memorycontrols
Selector control
Counter controls
Control logic
Output logic
Enable Enable E
X
1
0
Enable
1 0
Top−1
Topempty
datadata
emptyemptyempty
empty
0 1 2
102110221023
(a) Symbolic design
Figure 19: A 4-word stack implemented by RAM [Gajski].
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7. Storage Components 7-22
*First-in-First-out Queue
A rst-in-rst-out (FIFO) queue (or simply queue or FIFO ) is a memory com-ponent with limited access—data can be written through only the head (front)of the queue and read (and removed) through only the tail (back) of the queue.
A queue can be implemented by shift registers, with an up-down counter todetect full/empty queue as shown in Fig. 21.
It can also be implemented by a RAM—less expensive for a large queue, butneed two pointers (implemented by counters) as shown in Fig. 22.
Top
Top − 1
Top − 2
Top − 3
empty
empty
34
23
empty
45
34
23
empty
empty
45
34
23
45
(a) Queue content before 45 is stored
(b) Queue content after 45 is stored
(c) Queue content after 23 is read
Figure 20: FIFO queue operations [Gajski].
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7. Storage Components 7-23
. . .
(a) Operation table
Operations
X
0
1
0
1
1
Read/Write
No change
Read
Write
X
0
1
0
1
1
E
0
1
1
DS 1 S 0 Read/Write
0
0
1
0
0
0
X
1
0
(b) Control table
Up−Down Counter Reset D E Set
IN
IN
0
m−1
m−1OUT
0OUT
Empty
Full
S e
l e c
t o r
S e
l e c t o r
Reset
"0"
(c) Queue schematic
S 0
S 1
Reset
03 2 1
I
Q Q Q Q
SRwPL L I R
S 0
S 1
Reset
03 2 1
I
Q Q Q Q
SRwPL L I R
03 2 1Q Q Q Q
Control logic
Output logic
. . .
. . .
. . .
Enable Enable
Enable
S 1
S 0
S 1
S 0
3
2
1
0
3
2
1
0
Read/ Write
Figure 21: A 4-word queue implemented by shift registers [Gajski].
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7. Storage Components 7-24
Operations
X
0
1
0
1
1
Read/Write
No change
Read
Write
X
0
1
0
1
1
X
0
1
0
1
1
0
1
0
S CS RWS Read/Write
X
1
0
0
0
1
emptydatadata ...dataempty
Front
Back
0 1 2
102010211022
(a) Symbolic design (b) Operation table (c) Control table
Reset
Empty
Full
I/O bus
Selector 1 0
S
1K RAM
Clk
E Reset
Read/Write
E Reset
Back Front
1010
(d) Schematic
A
CS RWS
Comparator < = >
1 1
E (Front)
E (Back) Enable Enable
Enable
Figure 22: A 4-word queue implemented by RAM [Gajski].
c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2005
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7. Storage Components 7-25
Simple Datapaths
Datapaths are used in all standard CPU and ASIC implementations to per-form complex numerical computation or data manipulations; a datapath con-sists of temporary storage in addition to arithmetic, logic, and shift units.
Example 1Assume we want to perform the summation of 100 numbers:
Wecan use the datapath as shown in Fig. 23 to implement the following algorithm:
sum=0;for(i=1; i<=100; i++)
sum=sum+x[i];
(b) Control word
(a) Datapath schematic
Selector 1 0
S
ALU
A B M S
S 01
01S
S
Clk Accumulator
Input O
I R I L
8 7 6 5 4 3 2 1 0 Input select
Accumulator controls
ALU controls
Shift values
Out enable
8
76
5
43
21
0
Figure 23: Simple datapath with one accumulator [Gajski].
c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2005
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7. Storage Components 7-26
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ALU operation
Writeaddress
Read address A
Read address B IE OE Shifter
operation
(a) Datapath schematic
ALU
A B M S S 0
1
0
1
Clk
Bus B Bus A
Result Bus
Shifter S S
S
2
WAWE
3
3
3
Selector
1 0S
I L I R
RAA REA
RAB REB
"0" "0"
00001111
M S 1 S 0 ALU Operations
00110011
01010101
S 2
0000111
1
S 1 S 0
0011001
1
0101010
1
Shift Operations
(b) Table of ALU operations
(c) Table of shifter operations
complement AAND
EX−OR OR decrement A add subtract inrement A
pass pass not used not used shift left rotate left shift right
rotate right
(d) Control word
Inport
Outport
8 m Register File
x
7
654
32
1
0
19
8−1011
12−14
1516−18
Figure 24: Datapath with 3-port register le [Gajski].
c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2005
8/14/2019 Chapter 7. Storage Components.pdf
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7. Storage Components 7-27
(a) Basic algorithm for one’s count
R1: Data
R2: Mask
R3: Ocount
R4: Temp
(b) Register assignment
IE OE ControlWords
Read address B
Read address A
Writeaddress
ALU operation
Shifter operation
1
2
3
4
5
6
7
1
0
0
0
0
0
0
X
0
0
R1
R3
R1
R3
X
0
X
R2
R4
0
0
X
add
increment
AND
add
add
add
0
0
0
0
0
0
1
R1
R3
R2
R4
R3
R1
none
X
pass
pass
pass
pass
shift right
pass
(c) Control words for one’s counter
} Repeated while
Data = 0
while repeat
end while
1. Data := Inport2. Ocount := 03. Mask := 1 Data := 0
4. Temp := Data AND Mask 5. Ocount := Ocount + Temp 6. Data := Data >> 1
7. Outport := Ocount
Figure 25: One’s-count algorithm [Gajski].