chapter 9. multiplexers, decoders and programmable logic...

Chapter 9. Multiplexers, Decoders and Programmable Logic Devices

9 - 2

Introduction

◈ Multiplexer, Decoder, encoder. Three-state Buffer

◈ROMs

◈PLD

◈PLA

◈CPLD

◈FPGA

9.1 Introduction

9 - 3

Multiplexers

◈A multiplexer (or data selector) has a group of data inputs and a group of control inputs

◈The control inputs are used to select one of the data inputs and connect it to the output terminal

10' AIIAZ +=

Logic equation for the 2-to-1 MUX

9.2 Multiplexers

9 - 4

4-to-1 MUX

3210 '''' ABIIABBIAIBAZ +++=


9.2 Multiplexers

9 - 5

8-to-1 MUX

7654

3210

'''' ''''''''

ABCIIABCCIABICABBCIAIBCACIBAICBAZ

+++++++=


9.2 Multiplexers

9 - 6

2n-to-1 MUX

∑−

=

=12

0

n

kkk ImZ

Logic equation for the 2n-to-1 MUX

9.2 Multiplexers

9 - 7

Logic Diagram for 8-to-1 MUX

◈Logic Diagram for 8-to-1 MUX

9.2 Multiplexers

9 - 8

Quad MUX

◈Quad Multiplexer Used to Select Data

◈Quad Multiplexer with Bus Inputs and Output

9.2 Multiplexers

9 - 9

Function Realization using MUX

◈ A 4-to-1 MUX can realize any 3-variable function with no added logic gates.

◈ Example: Realize F(A,B,C)= A’B’ + AC

◈ Soln.: Expanding F so that all terms include both control inputs, A and B, yields

F = A’B’ + AC(B’+B) = A’B’1 + AB’C + ABC◈ The general eqn. For 4-to-1 MUX is

F = A’B’I0 + A’BI1+ AB’I2+ ABI3◈ Comparing eqns. ◈ We see they will be identical if

I0 =1, I1 =0, I2 =C, I3 =C

9.2 Multiplexers

9 - 10

Function Realization using MUX

Example: Consider the function Z(A,B,C,D) = Sm(0,1,3,6,7,8,11,12,14) and implement it using an 8-to-1 MUXSoln.: Assume that A,B,C are applied to control inputs s2,s1,s0 resp.

Then all 16 possible minterms that can be generated by the MUX can be represented in a table.

000 001 010 011 100 101 110 111I0 I1 I2 I3 I4 I5 I6 I7

D’ 0 2 4 6 8 10 12 14D 1 3 5 7 9 11 13 15

1 D 0 1 D’ D D’ D’

Working out the bottom row tells us what to apply to I0, I1, 12, etc.How to work it out? e.g. I0 col D’+D=1, I1 col only minterm with D appears, (apply D), I2 col no minterms used (apply 0), I3 col D’+D=1,I4 col. only minterm with D’ appears(apply D’).

9.2 Multiplexers

9 - 11

Example: Continued

◈The function is then realized with an 8-to-1 MUX with ABC applied to the control inputs and the values found in the table to I0, I1, I2, etc.

S2S1 S0

9.2 Multiplexers

9 - 12

Example: Continued Alternate Solution

Represent all of the minterms of Z on a k-map. Then obtaingroupings corresponding to [I0 = 000 with both D’ and D][I1=001 with both D’ and D] etc. Each of the two-minterm groupingscan be thought of as a 1-variable k-map in D only and simplified.

One-variable k-maps

9.2 Multiplexers

9 - 13

Example: Continued Yet another Alternate Solution

◈This time assume that A,B,D are applied to control inputs S2,S1,S0 respectively

000 001 010 011 100 101 110 111I0 I1 I2 I3 I4 I5 I6 I7

C’ 0 1 4 5 8 9 12 13C 2 3 6 7 10 11 14 15

C’ 1 C C C’ C 1 0

D

C’

C’

1

0

C

C

1

C

S0S1S2

Mux Realization with Control Inputs A, B, and D

9.2 Multiplexers

9 - 14

Example (Cont.)

◈ Example: continued yet another alternate solution using externalgates

00 01 10 11 I0 I1 I2 I3

00 0 4 8 12 01 1 5 9 13 11 3 7 11 15

CD

10 2 6 10 14

Table method in this case isequivalent to four 2-variable K-maps

9.2 Multiplexers

9 - 15

Buffers

◈A simple buffer may be used to increase the driving capability of a gate output

◈Gate Circuit with Added Buffer

9.3 Three-State Buffers

9 - 16

Three-State Buffers

◈Use of three-state logic permits the outputs of two or more gates or other logic devices to be connected together

◈Three-state buffers


9 - 17

Three-State Buffers

◈Four Kinds of Three-State Buffers

Z

Z

0

1

0 0

0 1

1 0

1 1

CB A

(a)

Z

Z

1

0

0 0

0 1

1 0

1 1

CB A

(b)

0

1

Z

Z

0 0

0 1

1 0

1 1

CB A

(c)

1

0

Z

Z

0 0

0 1

1 0

1 1

CB A

(d)


9 - 18

Data Selection Using Three-State Buffers

D = B’A + BCD = B’A + BC


9 - 19

Circuit with Two Three-State Buffers

◈Circuit with Two Three-State Buffers

◈When a bus is driven by three-state buffers, we call it a three-state bus.

◈The signal on this bus can have values of 0, 1, Z and perhaps X.

X

X

1

1

1

X

0

X

0

S2

0

X

X

X

X

X

X

0

1

Z

X

0

1

Z

ZS1

X = Unknown


9 - 20

Three-State BUS

◈Example : 4-Bit Adder with Four Sources for One Operand


9 - 21

Bi-Directional Pins

◈Integrated Circuit with Bi-Directional Input/Output Pin

◈Bi-directional means that the same pin can be used as an input pin and output pin, but not both at the same time

◈To accomplish this, the circuit output is connected to the pin through a three-state buffer


9 - 22

3-to-8 Line Decoder

9.4 Decoders and Encoders

0

0

0

0

0

0

10

y6

0

0

0

0

0

0

0

1

y7

1

0

0

0

0

0

0

0

y0

0

1

0

0

0

0

0

0

y1

0

0

1

0

0

0

0

0

y2

0

0

0

1

0

0

0

0

y3

0

0

0

0

10

0

0

y4

0

0

0

0

0

10

0

y5

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

a b c

This decoder generates all minterms of of the three input variables

Exactly one of the output lines will be 1 for each combination of the input variables.

9 - 23

A 4-to-10 Line Decoder (1)


9 - 24

A 4-to-10 Line Decoder (2)

1

1

1

1

1

1

1

0

1

1

1

1

1

1

1

1

7

1

1

1

1

1

1

1

1

0

1

1

1

1

1

1

1

8

Decimal OutputBCD Input

1

1

1

1

1

1

0

1

1

1

1

1

1

1

1

1

6

1

1

1

1

1

1

1

1

1

0

1

1

1

1

11

9

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

1

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

1

1

1

1

1

1

1

1

1

1

1

1

1

2

1

1

1

0

1

1

1

1

1

1

1

1

1

1

1

1

3

1

1

1

1

0

1

1

1

1

1

1

1

1

1

1

1

4

1

1

1

1

1

0

1

1

1

1

1

1

1

1

1

1

5

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

A B C D

(c) Truth Table


9 - 25

Realization of a Multiple-Output Circuit Using a Decoder

outputs) (inverted 12 to0 ,

outputs) ed(noninvert 12 to0 ,

−===

−==

niii

nii

iMmyor

imy

)''''(),,,(

421

4211

mmmmmmdcbaf

=++=

)''''(),,,(

974

9742

mmmmmmdcbaf

=++=

Can realize a function by ORing together selected minterm outputs.In this case outputs are active low, so NAND gates are used (effectively ORing together these outputs).


9 - 26

8-to-3 Priority Encoder

0

0

0

0

1

X

X

X

X

y3

0

0

0

0

01

X

X

X

y4

0

0

0

0

0

0

1

X

X

y5

0

0

0

0

0

0

0

1

X

y6

0

0

0

0

0

0

0

0

1

y7

0

0

0

0

0

1

1

1

1

a

0

0

0

1

1

0

0

1

1

b

0

0

1

0

1

0

1

0

1

c

0

0

1

X

X

X

X

X

X

y1

0

0

0

1

X

X

X

X

X

y2

0

1

X

X

X

X

X

X

X

y0

0

1

1

1

1

1

1

1

1

d


9 - 27

Read-Only Memories

◈ A read-only memory (ROM) consists of an array of semiconductor devices that are interconnected to store an array of binary data.

◈An 8-Word x 4-Bit ROM

9.5 Read-Only Memories

1

1

0

0

1

0

1

0

F0

0

1

0

1

0

1

0

1

C

0

0

1

1

1

0

1

1

F1

1

1

1

0

0

0

1

0

F2

0

0

1

1

0

1

1

1

F3

0

0

1

1

0

0

1

1

B

0

0

0

0

1

1

1

1

A

(a) Block diagram (b) Truth table for ROM

typical data stored in ROM

(23 words of

4bits each)

9 - 28

ROM with n Inputs and m Outputs

◈Read-Only Memory with n Inputs and m Outputs

100

010

101

110

001

110

011

111

· · · ·· · · ·· · · ·· · · ·

··

· · · ·· · · ·· · · ·· · · ·

m output

Variables

· · · ·· · · ·· · · ·· · · ·

··

· · · ·· · · ·· · · ·· · · ·

110

111

101

010

··

011

110

000

101

00

01

10

11

00

01

10

11

00

00

00

00

11

11

11

11

n input

Variables

typical data array stored

in ROM

(2n words of

m bits each)


9 - 29

Basic ROM Structure

◈ When a pattern of n 0’s and 1’s is applied to the decoder inputs, exactly one of the 2n decoder output is 1

◈ This decoder output line selects one of the words in the memory array, and the bit pattern stored in this word is transferred tothe memory output lines


9 - 30

ROM Implementation of Boolean Functions

Decoder generatesall minterms of input variables

Switching elementseffectively form an OR gate

Contents of ROMusually specifiedby a truth table

A 2n x m ROMcan realize m functions of n variables

∑∑∑∑

+==

+==

+==

+==

4)7,6,5,3,2(

''')6,2,1,0(

')7,6,4,3,2(

''')6,4,1,0(

3

2

1

0

BACmF

BCBAmF

ACBmF

ACBAmF


9 - 31

Equivalent OR Gate for F0

◈For above example

∑ +== ''')6,4,1,0(0 ACBAmF


9 - 32

Example : Code Converter

◈Hexadecimal to ASCII Code Converter

ASCII Code for Hex DigitInput

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

A6

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

A5

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

A4

0

0

0

0

0

0

0

0

1

1

0

0

0

0

0

0

A3

0

0

0

0

1

1

1

1

0

0

0

0

0

1

1

1

A2

0

0

1

1

0

0

1

1

0

0

0

1

1

0

0

1

A1

Hex

Digit

0

1

0

1

0

1

0

1

0

1

1

0

1

0

1

0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

A0ZYXW


9 - 33

ROM Realization of Code Converter


9 - 34

Example: Implement 2 functions of 3 variables

F (A,B,C) = A ⊕ B ⊕ C G = AB + AC + BC

A B C F G0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 0 1 0 1 0 11 1 0 0 11 1 1 1 1

Recall that Exclusive OR (⊕)

A B Y0 0 00 1 11 0 11 1 0

A0A1A2

8 x 2 Memory

ABC O0

G

LookUp Table (LUT)

O1F

A[2:0] is 3 bit address bus, O[1:0] is 2 bit output bus.Location 0 has “00”, Location 1 has “10”,Location 2 has “10”, etc….


9 - 35

Memory Implementation can be INEFFICIENT

◈What if I wanted to implement:F(A,B,C, D) and G (W,X,Y, Z)

◈These are two INDEPENDENT functions - they use DIFFERENT inputs!

◈Note that the variables are different. I could use two different memory devices (need 32 locations total between the two devices):

ABCD

A3A2A1A0

O

16 x 1 Memory

WXYZ

A3A2A1A0

O

16 x 1 Memory

F G


9 - 36

Memory Implementation can be INEFFICIENT (Cont’d)

◈What if I wanted to use only a single memory device?

A

B

CD

A7A6A5A4

O1

O0

256 x 2 Memory

WXY

Z

A3A2A1A0

F

G

Most of the locations are wasted because I have to repeat the G function for every F input.

Went from 32 locations to 256 locations!


9 - 37

Another Inefficiency

◈Implement:

F(A,B,C,D,E,F,G,H) = ABCD + EFGH

◈Looks like a simple equation…would only take two 4 input NANDs, and one two input NAND (NAND-NAND form).

◈Yet it takes a 256 x 1 memory device because of the number of input variables!

ABCD

A7A6A5A4 O

256 x 1 Memory

EF

GH

A3A2A1A0

F


9 - 38

Memory Summary

◈To implement m functions of the same n variables,

need a memory with 2n locations and m bits per location (use one address line for each variable, use data out line for each function).

◈Memory is not efficient at implementing wide functions (functions with lots of input variables) or multiple functions with different inputs.


9 - 39

Programmable Logic Devices (PLDs)

◈PLDs were invented to address the inefficiencies of implementing logic using memories.

◈PLDs can implement wide functions efficiently (functions with many input variables).

◈PLDs can implement multiple functions of different variables efficiently.

◈The logic in PLDs is programmable -- it can be defined by the user and programmed on the desktop

Most PLDs can be erased and reprogrammed many times.

9.6 Programmable Logic Devices

9 - 40

PLD types

◈There are MANY different types of PLDs.

◈Densities ranges from from 10’s of gates to 100’s of thousands of gates.

◈We will look at a type called PALs (Programmable Array Logic).


9 - 41

Programmable Logic Array

ANDArray

ORArray

k wordlines

n inputlines

m outputlines

PLA

AND array--> product termsOR array OR’stogether product terms

Can realize m functions of n variables


9 - 42

PLA Internal Structure

◈PLA with Three Inputs, Five Product Terms, and Four Outputs


9 - 43

PLA AND-OR Array Equivalent

◈AND-OR Array Equivalent


9 - 44

PLA Table for Figure 9-25

◈PLA Table for Figure 9-25

OutputsInputs

-

0

-

0

1

C

1

1

0

0

0

F0

0

1

1

0

0

F1

1

0

0

1

0

F2

0

0

1

0

1

F3

0

-

1

1

-

0

1

-

-

1

A’B’AC’B

BC’AC

BA

Product

Term

ACBFBCBAF

BACFACBAF

+=+=+=+=

3

2

1

0

''''

'''


9 - 45

PLA Realization of Functions

1

1

1

1

0

0

f1

1

0

0

0

1

0

f2

0

1

1

0

0

1

f3

1

1

-

-

-

-

-

-

0

1

1

1

1

1

0

0

-

1

0

1

1

-

-

-

dcba

(a) PLA table

◈F1 = a’bd + abd+ab’c’ + b’c◈F2 = c + a’bd

◈F3 = bc + ab’c’ + abd


9 - 46

PALs (Programmable Array Logic)

◈ An early type of programmable logic - still in common use today.

◈ Logic is represented in SOP form (Sum of Products)

◈ The number of PRODUCTs in an SOP form will be limited to a fixed number (usually 4-10 Product terms).

◈ The number of VARIABLEs in each product term is limited by the number of input pins on the PLD (usually a lot, minimum of 10 inputs)

◈ The number of independent functions is limited by number of OUTPUT pins.


9 - 47

Programmable Array Logic

◈Programmable Array Logic

The symbol of Figure 9-28(a)

logically equal


9 - 48

Programmable Array Logic

◈When the PAL is programmed, some of the interconnection points are programmed to make the desired connections to the AND gate inputs

Connections to the AND gate inputs in a PAL


9 - 49

PAL Segment


9 - 50

Implementation of a Full Adder Using a PAL

◈Example : Full Adder

inininin XYCCXYYCXCYX +++= ''''''

XYYCXC inin ++=


9 - 51

Complex Programmable Logic Devices (CPLDs)

◈Instead of a single PAL or PLA on a chip, many PALs or PLAs can be placed on a single CPLD chip and interconnected

◈When storage elements such as flip-flops are also included on the same IC, a small digital system can be implemented with a single CPLD

9.7 Complex Programmable Logic Devices

9 - 52

Architecture of Xilinx XCR3064XL CPLD

◈Architecture of Xilinx XCR3064XL CPLD (Figure based on figures and text owned by Xilinx, Inc., Courtesy of Xilinx, Inc. © Xilinx, Inc.1999-2003. All rights reserved.)


9 - 53

CPLD Function Block and Macrocell

◈CPLD Function Block and Macrocell(A Simplified Version of XCR3064XL)


9 - 54

Field Programmable Gate Arrays (FPGAs)

◈An FPGA is an IC that contains an array of identical logic cells with programmable interconnections

◈The user can program the functions realized by each logic cell and the connections between cells

9.8 Field Programmable Gate Arrays

9 - 55

Typical FPGA

◈Layout of a Typical FPGA


9 - 56

Simplified Configurable Logic Block (CLB)

◈ Simplified Configurable Logic Block (CLB)

The function generators are implemented as lookup tables(LUTs)

A 4-input LUT is essentially a reprogrammable ROM with 16 1-bit words


9 - 57

Implementation of a Lookup Table (LUT)

◈Implementation of a Lookup Table (LUT)

0

1

··1

d

0

1

··1

0

0

··1

0

0

··1

0

0

··1

fcba

abcddabccdabdcabbcdadbcacdbadcbaF +++++++= ''''''''''''''''


9 - 58

Decomposition of Switching Functions

◈In order to implement a switching function of more than four variables using 4-variable function generators, the function must be decomposed into subfunctions where each subfunction requires only four variables

◈Shannon’s expansion theorem

10'),,,1(),,,0('),,,( affadcbafdcbfadcbaf +=+=


9 - 59

Shannon’s Expansion Theorem

◈Example

◈The general form

10')'()'''(')'''()'''('

'''''),,,(

affabdcacdcbdcacbcddcabcdcbdca

acbcdcbadcdcbaf

+=++++=+++++=

+++=

iii

niiiniii

nii

fxfxxxxxxfxxxxxxfx

xxxxxf

+=+= +−+−

+−

0

11211121

1121

'),...,,0,,...,,(),...,,0,,...,,('

),...,,0,,...,,(


9 - 60

Decomposition of switching Functions

◈5-variables

◈6-variables

10'),,,,1(),,,,0('),,,,( affaedcbafedcbfaedcbaf +=+=

11101

01000

10

'),,,,1,1(),,,,0,1(''),,,,1,0(),,,,0,0(''),,,,,1(),,,,,0('),,,,,(

bGGbfedcbGfedcGbGbGGbfedcbGfedcGbGaGGafedcbaGfedcbGafedcbaG

+=+=+=+=+=+=

11100100 ''''),,,,,( abGGabbGaGbafedcbaG +++=


9 - 61

Function Expansion Using a Karnaugh Map

◈Function Expansion Using a Karnaugh Map


9 - 62

Realization of 5- and 6-Variable Functions

◈Realization of Five- and Six-Variable Functions with Function Generators


chapter 9. multiplexers, decoders and programmable logic...

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