ChargeCharge--Recycling MTCMOS: Circuit Recycling MTCMOS: Circuit Techniques and Design Automation Techniques and Design Automation

AlgorithmsAlgorithms

Massoud Pedram

University of Southern CaliforniaEE Dept.

pedram@ceng.usc.edu

IEEE SSCS Austin ChapterNov 16, 2006

2

RealitiesRealities

• Power has emerged as the #1 limiter of design performance beyond the 65nm generation.

• Dynamic and static power dissipation limit achievable performance due to fixed caps on chip or system cooling capacity.

• Power related signal integrity issues (IR drop, L di/dt noise) have become major sources of design re-spins.

TransistorsTransistors (and silicon) are (and silicon) are free.free.PowerPower is the only real is the only real limiter.limiter.OptimizingOptimizing for for frequency and/or areafrequency and/or area may achieve may achieve neither.neither.

Pat Gelsinger, Senior Vice President & CTO, Intel

Motivation

3

Industry Views (Intel)Industry Views (Intel)Motivation

4

OutlineOutline

• Sources of Leakage in CMOS VLSI Circuits• Circuit and CAD Techniques for Leakage Minimization• MTCMOS• Charge Recycling MTCMOS• Conclusion

5

Leakage Components in Bulk CMOSLeakage Components in Bulk CMOS

• I1 Diode reverse bias current• I2 Subthreshold current • I3 Gate induced drain leakage • I4 Gate oxide tunneling

Long Channel (L > 1 μm) Very small leakage

Short Channel(L > 180nm, Tox > 30A0)Subthreshold leakage

Very Short Channel(L > 90nm, Tox > 20A0)Subthreshold +Gate leakage

Nano-scaled(L < 90nm, Tox < 20A0)Subthreshold +Gate + Junction leakage

Leakage Modeling

6

Subthreshold Leakage CurrentSubthreshold Leakage Current

I2: Transfer characteristics of MOSFET for VGS near Vth:

10lnq

nkTS =

• The inverse subthreshold slope, S, is equal to the voltage required to increase ID by 10X, i.e., • If n = 1, S = 60 mV/dec at 300 K• We want S to be small to shut off the MOSFET quickly• In well designed devices, S is 70 - 90 mV/dec at 300 K.

2 e 1 e 10GS th DS DS GS th DS GS th DS

T T T

V V V V V V V V V Vnv v n S

sub e T sth

WI v C e

L

η η ηνμ

− + − − + − +⎛ ⎞= − ∝ =⎜ ⎟⎜ ⎟

⎝ ⎠

Subthreshold Leakage

7

Modeling Subthreshold (Modeling Subthreshold (IIsubsub) and ) and off (off (IIoffoff) Currents ) Currents • Increases exponentially with reduction in Vth.

• Modulation of Vth in a short channel transistor.- L ↓ ⇒ Vth ↓: “Vth Rolloff”- VDS ↑ ⇒ Vth ↓:”Drain Induced Barrier Lowering”- VSB ↑ ⇒ Vth ↑: “Body Effect”.

• If VDS = 0 ⇒ Isub = 0

• If long-channel device w/ VDS > ⇒

• With

• Key dependencies of the subthreshold slope:- Tox ↓⇒ Cox ↑⇒ n ↓⇒ sharper subthreshold- NA ↑⇒ Csth ↑⇒ n ↑⇒ softer subthreshold- VSB ↑⇒ Csth ↓⇒ n ↓⇒ sharper subthreshold- T ↑⇒ softer subthreshold.

2GS th

T

V V

nvsub e T sth

WI v C e

Lμ

−

=

1 1 12 2

dep itsth

ox oxf

C CCn

C C

γ += + = + = +

Φ

3 Tnv

T

th

nv

V

sthTeGSsuboff eCvL

WVII

−=== 2)0( μ

Subthreshold Leakage

• Occurs when transistor is “off”

8

Gate Oxide TunnelingGate Oxide Tunneling

• I4: Gate oxide tunneling of electrons that can result in leakage when there is a high electric field across a thin gate oxide layer. Electrons may tunnel into the conduction band of the oxide layer; this is called Fowler-Nordheim tunneling.

• In oxide layers less than 3–4 nm thick, there can also be direct tunneling through the silicon oxide layer. Mechanisms for directtunneling include electron tunneling in the conduction band (ECB), electron tunneling in the valence band (EVB), and hole tunneling in the valence band (HVB).

• Direct tunneling of electrons through gate oxide is the dominantsource. This current depends exponentially on the oxide thickness and the VDD [BSIM 4].

1.5

1 1

2( )

gsg

ox

gs

oxgs

ox

VB

V

TDT g

V

TJ A e

⎛ ⎞⎛ ⎞⎜ ⎟− − −⎜ ⎟⎜ ⎟⎜ ⎟Φ⎝ ⎠⎝ ⎠

=

Gate Leakage

• Occurs when transistor is “on”

9

Gate ON/OFF currentsGate ON/OFF currents

• As oxide thickness decreases, gate current becomes more important; eventually it dominates the off current (ID at VG = 0).

10-16

10-14

10-12

10-10

10-8

10-6

10-4

0 50 100 150 200 250

Cur

rent

(A

/μm

)

Technology Generation (nm)

Ion

IG

Ioff

Source: Dieter K. Schroder, Arizona StateSource: D. Frank, IBM, 2002

Gate Leakage

10

Why highWhy high--K dielectricK dielectric

• SiO2 layers <1.6 nm have high leakage current due to direct tunnelling. Not insulating.

• Maintain C/area for S-D current:

• Replace SiO2 with thicker layer of new oxide with higher K.• Equivalent oxide thickness, ‘EOT’.

t

KC 0ε=

Gate Leakage

DRAM limit

Gate limit

0 1 2 3Gate voltage (V)

Gat

e cu

rren

t den

sity

(A

.cm

)

1

10

10

2

-2

10-4

10-6

10-8

104

-2

T (nm)ox

1.5

2.0

2.5

2.9

3.5

1.0Source: John Roberston, Cambridge Univ.

11

C1

C2

C3

2000 2005 2010 2015

1

10

100

year

Le

ng

th (

nm

)

N ode

G ate length

E O T

S i a tom diam eter

High-K dielectrics:hafnium-oxide-based materials

Gate leakage and highGate leakage and high--K dielectricK dielectric

Polysilicon gate electrodes are known to suffer from a polySidepletion effect (equivalent to a ~0.3–0.4-nm-thick parasitic capacitor), which cannot be ignored for sub-2-nm gate stacks.

Gate Leakage

12

Gate dielectric scaling and metal gatesGate dielectric scaling and metal gates

Source: R. Jammy, Sematech

Thermal/plasma nitrided SiO2 (SiON) continuesIn practice for > two technology generations

Implementation of high-K needs metal gatesAt least SiON-like mobilities in high-K dielectrics

Need to identify stable n and p type metals and integration options

Gate Leakage

13

HighHigh--K, metal gate stackK, metal gate stack

• Key Issues with metal gate/high-K: thermal stability, degraded carrier mobility in the transistor channel, and Vth control

• Band edge metal gates (fully sillicided gates) limiting factor in high-K deployment

- Key manufacturability issues: thickness, stoichiometry, uniformity, workfunction, contamination control, gate CD control and reliability

- Still a road block!

Gate Leakage

14

OutlineOutline

• Sources of Leakage in CMOS VLSI Circuits• Circuit and CAD Techniques for Leakage Minimization• MTCMOS• Charge Recycling MTCMOS• Conclusion

15

Leakage Reduction TechniquesLeakage Reduction Techniques

• Lowering and/or turning off Vdd (voltage islands and power domains)

• Non-minimum channel length transistors• Dual-Vth design • Transistor stacking• Body bias control (static and/or adaptive)• MTCMOS (sleep transistors, power gating)• SOI technology• Cooling and/or refrigeration

Leakage Reduction

16

Power dependence on VPower dependence on VTHTH and Vand VDD DD

Vdd vs. Vth

17

Delay dependence on VDelay dependence on VTHTH and Vand VDDDD

Vdd vs. Vth

18

Voltage Islands and Power DomainsVoltage Islands and Power Domains

• Voltage islands -Areas (logic and/or memory) on chip supplied through separate, dedicated power feed.

• Power domains -Areas within an Island fed by same Vddsource but independently controlled via on intra-island header switches.

Voltage Islands

Source: IBM Blue Logic® Cu-08 voltage islands Ldrawn = 70 nmUp to 72-million wireable gatesPower supply: 1.0 V with 1.2-V optionPower dissipation: 0.006 µW/MHz/ gateGate delays: 21 picoseconds (2-input NAND gate)Eight levels of copper for global routing.

19

Voltage Island Powering and Switching ControlVoltage Island Powering and Switching Control

• Any additional voltage levels must be available from off-chip sources or generated with on-chip regulators. Signal interfaces between regions running on different supplies must have appropriate level converters.

• If blocks are powered down, electrical "fencing" is required to prevent indeterminate state from corrupting still active blocks. In addition, powered down blocks probably need to save and restore state. Source EE-Times, August 06, 2004 Issue

Voltage Islands

20

Using NonUsing Non--minimum Channel Lengthsminimum Channel Lengths

• As Le increases, Vth goes up and leakage is reduced exponentially.

• Extent of leakages reduction is a function of the Vth roll off effect.

Voltage Islands

70nm Vth versus Le Plot

1.16

1.18

1.2

1.22

1.24

1.26

1.28

1.3

1.32

1.34

1.36

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

ΔVth

/Vth

ΔLe/Le

Vth roll off region

Source: Clark, SLPED 2004

Source: Taur, IDEM 1998

21

Dual Dual VVthth DesignDesign

• Use two- Use the lower threshold for gates on critical path- Use the higher threshold for gates off the critical path.

• Improves performance without an increase in power.

Dual Vth#

of

pat

hs

slack

150nm

100nm high-Vt 100nm

low-Vt

100nm dual-- VtNote: not drawn to scale

# o

f p

ath

s

slack

150nm

100nm high-Vt 100nm

low-Vt

100nm dual-- VtNote: not drawn to scale

0%

5%

10%

15%

20%

25%

30%

35%

40%

45%

50%

55%

60%

0% 5% 10% 15% 20% 25%

% timing scaling from all high-Vt design

very

low

- Vt

tran

sist

or

wid

th(a

s %

of t

otal

tran

sist

or w

idth

)

0%

5%

10%

15%

20%

25%

30%

35%

40%

45%

50%

55%

60%

0% 5% 10% 15% 20% 25%

% timing scaling from all high-Vt design

very

low

- Vt

tran

sist

or

wid

th(a

s %

of t

otal

tran

sist

or w

idth

)

Full low-Vt performance!low-Vt usage: 34%

0%

5%

10%

15%

20%

25%

30%

35%

40%

45%

50%

55%

60%

0% 5% 10% 15% 20% 25%

% timing scaling from all high-Vt design

very

low

- Vt

tran

sist

or

wid

th(a

s %

of t

otal

tran

sist

or w

idth

)

0%

5%

10%

15%

20%

25%

30%

35%

40%

45%

50%

55%

60%

0% 5% 10% 15% 20% 25%

% timing scaling from all high-Vt design

very

low

- Vt

tran

sist

or

wid

th(a

s %

of t

otal

tran

sist

or w

idth

)

Full low-Vt performance!low-Vt usage: 34%

Source: Vivek De, Intel

22

Dual Dual VVthth: Observations and Questions: Observations and Questions

• In the dual-Vth approach, leakage current is controlled by managing threshold voltages using manufacturing process techniques so that the threshold of a gate is fixed.

• The high Vth cells are identical to the low Vth cells except for processing changes.

• No change to the library characterization methodology is required, but the high Vth library does require a separate characterization. Modeling of the library can continue to be done with NLDM format look-up tables, and the cells can be stored in separate Liberty files.

• How can we assign threshold voltages to transistors?- Not all non-critical gates can be made high Vth.

• What are their optimal values?- Delay and leakage sensitivities to the Vth values.

Dual Vth

23

VariableVariable--Threshold CMOSThreshold CMOS

• Another approach to managing threshold voltage is the use of substrate biasing. - Normally, the substrate in a digital gate is tied to GND for NMOS

transistors and to Vdd for PMOS transistors. Substrate biasing is used in conjunction with process-based Vth management.

• As the bias voltage for any of these devices is reduced below 0V under reverse bulk bias (RBB), Vth increases and leakage current decreases. Under forward bulk bias (FBB), Vth decreases and performance increases at the expense of leakage current.

• The variable threshold or VTCMOS approach uses RBB in standby modes to manage leakage power without degrading performance.- This approach assumes a low Vdd with low Vth devices are used in

active mode to meet overall performance requirements, although it can be combined with dual- and multi- Vdd approaches. A standby mode using RBB raises the effective Vth to block leakage current.

VTCMOS

24

Reverse and Forward Body BiasingReverse and Forward Body Biasing

Body Biasing

Vdd Vbp

Vbn-Ve

+Ve

• Reverse Body Biasing (RBB)- No Bias = Low Vth

- Apply Reverse Bias = High Vth.

• Forward Body Biasing (FBB)- No bias = High Vth

- Apply Forward Bias = Low Vth.

1

10

100

0.01 0.1 1 10 100 1000Target Ioff (nA/μm)

110C0.5V RBB

Low VT

High VTIntrinsicLeakageReductionFactor (X)

Shorter L

RBB becomes less effective at shorter L and lower Vth

Source: A. Keshavarzi, 1999 & 2001 , SLPED

VTCMOS

25

Stack ForcingStack ForcingTransistor Stacking

• Another low-leakage power design solution is “stack forcing,” in which a single transistor is divided into two or more transistors to increase resistance for leakage currents.

26

OutlineOutline

• Sources of Leakage in CMOS VLSI Circuits• Circuit and CAD Techniques for Leakage Minimization• MTCMOS• Charge Recycling MTCMOS• Conclusion

27

MultiMulti--Threshold CMOS (MTCMOS)Threshold CMOS (MTCMOS)

• It is also called guarding, power gating, ground gating, using sleep transistor, etc.

• A high-Vth is used to disconnect low-Vth transistors from the ground (Vdd).

MTCMOS

N

outin

SLEEP

P

SLEEP

Virtual Supply

Virtual Ground

Low Threshold High Threshold

28

Sleep Mode ApproachSleep Mode Approach

• The high Vt sleep mode approach is a global leakage power reduction technique that requires fewer changes to the design. The design is implemented using low Vttransistors to meet high-speed performance goals. High Vt NMOS and PMOS sleep control transistors are added to form virtual supply rails (VDD,V, GNDV.)

• A sleep mode signal, SL, controls the operation of these high Vt transistors. In active mode, these sleep transistors function as real power and grounds with small on-resistances. In sleep mode, these transistors block the leakage currents otherwise present in the low Vt circuitry.

MTCMOS

29

SimplificationsSimplifications

• Instead of two sleep transistors, one can be used.

• Usually NMOS:- μn > μp smaller size.- However, PMOS usually has a lower

leakage.

• One sleep transistor can be shared between several gates- Reduction in the number of sleep

transistors, area overhead, dynamic and leakage power dissipations

- Increase in the complexity of design optimization process.

N

outin

P

SLEEPVirtual Ground

Vdd

MTCMOS

Gate1

SLEEPVirtual Ground

Gate2 Gate3

Vdd

30

Sleep Transistor SizingSleep Transistor Sizing

• Reduction in the high to low transition due to,- Reduction in the gate drive from Vdd to Vdd – Vx.- Increase in the threshold voltage of NMOS due to the body effect.

• Increase the sleep transistor width to solve the problem- Increase in the area overhead, dynamic power and leakage.

• Technology scale down have to enlarge the sleep transistor

MTCMOS

[Kao-DAC97]

SLEEP = Vdd

Vx

Vdd

dsVappVthVthV ηγ −+= '0

ddVgsV <

31

Important QuestionsImportant Questions

• How many sleep transistors?- Affects the area overhead, the dynamic power overhead, and the

leakage power saving.

• How to cluster gates?- Affects the routability and the size of the sleep transistors.

• What size to choose for the sleep transistors?- Affects the delay and area overhead, the dynamic power

overhead and the leakage power saving.

MTCMOS

32

SamsungSamsung’’s MTCMOS Design Methodologys MTCMOS Design Methodology

• Design new cells that have sleep transistors.• Use conventional P&R methodology.

Vdd

GND

Vdd

VGND

GND

Area Overhead~ 12%

MTCMOS

[Won-ISLPED03]

33

ProblemsProblems

• MTCMOS cannot be applied to Flip Flops- Data loss- Can copy the data to an external

memory• Delay and dynamic power overhead• Energy overhead of external memory

• In an SoC, not all IP blocks are guarded- Short circuit current if a guarded output

drives a regular input.

MTCMOS

Flip Flop

Vdd

Gate2

Vdd

Gate1

Vdd

0 < V’ < Vdd

V’

34

Complementary PassComplementary Pass--Transistor Flip Flop (CPFF)Transistor Flip Flop (CPFF)MTCMOS

O

SCB

Q

Q

dataD

data

CLK

SCB

A high threshold transistor is used to reducethe leakage in the sleep mode.

High threshold inverters are not guarded.

Low threshold transistors to decrease the delay.

High threshold transistors are used to cut the leakage path in sleep mode.

35

Preventing Short Circuit CurrentPreventing Short Circuit Current

SC

IP2

SCB

Floating Prevention Circuit (FPC)

MTCMOS

Active ActiveSleep

T1 T2

IP1

SC

SCB

SLEEP• Store the data in a latch

before disconnecting the module from the ground.

36

Design FlowDesign Flow

Add Power Management Block to the RTL Code

Synthesize the RTL Code

Insert FPCs at the Interface to Unguarded IP Blocks

Insert Sleep Transistors

Place & Route Check Placement Rules and Floating Nodes

Replace All Flip Flops with CPFFs

Floor Plan Size Sleep Transistors

MTCMOS

37

DSP CoreDSP Core

• The method was applied to a 16-bit DSP chip• 0.18μm, Vdd = 1.8V• Inserted 324 sleep transistors with the size of 5μm • Ground bounce: average=9mV, max=49mV• Performance degradation = 2%

MTCMOS

38

A 32A 32--bit RISC Processor used in a PDAbit RISC Processor used in a PDA

333MHz

Clock

1,914K

# Gates

0.18μm 5-metal

Process

270mW18mm5.7mm ×5.7mm

Power Dissipation

Total Sleep Transistors WidthChip Size

6000x2μW

ReductionLeakage Power

MTCMOS

39

Minimizing Ground BounceMinimizing Ground Bounce

• During the sleep period, internal nodes are charged up.

• When the sleep transistor is turned on hard, there is a current spike flowing to the ground (due to the large Vds of the sleep transistor).

• This sinks a lot of current into the GND terminal, potentially creating a large ground bounce noise.

Circuit

Vdd

Vdd

GND

MTCMOS

[Kim-ISLPED03]

40

IBMIBM’’s First Solutions First Solution

• Turn-on the sleep transistor in two steps:

1. Using a weak PMOS: Vgs< Vdd for the sleep transistor. Originally, Vdsis high. So, the peak current is controlled.

2. Using a strong PMOS: Vgs= Vdd for the sleep transistor. Vds is however low. Therefore, the peak current reduces.

MTCMOS

Circuit

Virtual Ground

Vdd

Weak

Sleep

Sleep Delayed Sleep

Strong

Sleep transistor

41

IBMIBM’’s Second Solutions Second Solution

• Use several sleep transistors.

• Turn them on with some delay.

• The resistance between the virtual ground and the ground is reduced as the Vds of the sleep transistor is lowered. This reduces the peak current.

MTCMOS

Circuit

Vdd

Sleep FFFFFF

W23

1W

23

2W

23

4W

23

16Virtual Ground

42

ResultsResults

• Applied to a 16-bit ALU (with a multiplier)• Designed at 0.13μm, 1.5V, operating at 500MHz.

50

55

60

65

70

75

80

85

90

Imax Imin Vmax-Vdd

Vmin-Vdd

Vmax-GND

Vmin-GND

Ts

Rat

io (%

)

Method1 Method2

MTCMOS

Vmax

Vmin

Ts is the time it takes for the voltage of both ground and Vdd to settle within ±5% of their final values.

TS

43

Virtual Power/Ground Rail Clamp (VRC)Virtual Power/Ground Rail Clamp (VRC)

• Reduce the virtual supply and ground voltages using two diodes- This allows state retention.- It reduces noise during

transition to active mode.- However, the leakage reduction

is small.

[Kumagai-SVLSIC98]

MTCMOS

Circuit

Vdd

VD

Vdd-VD

44

Park ModePark Mode

• Use a normally-on PMOS transistor to clamp the virtual ground (Park Mode)- Reduces leakage and bounce noise during wakeup.- Keeps the internal state.

• Turn off the PMOS transistor when in the Sleep Mode to achieve higher leakage saving. However, internal state will be lost.

• Empirical results for a 32-bit Carry Look Ahead adder designed in 0.13µm technology for various supply voltages.

[Kim-ISLPED04]

MTCMOS

Circuit

Vdd

22.8x43xSleep

2.68x2.3xPark

1.5V0.9V

7.42%

2.44%

1.1V

6.26%3.49%Sleep

2.83%1.07%Park

1.5V1.3V

Leakage reduction compared to active mode

Clock Frequency Reduction

45

ToshibaToshiba’’s Mixed MTCMOS and Dual Vs Mixed MTCMOS and Dual Vth th MethodMethod

• Used to reduce the leakage power in a DSP core for W-CDMA cell phones.

• Cell phones spend a significant amount of time in the standby mode.- High leakage power dissipation.

• Note however that the phones have to exchange some information with base stations every 100ms.

MTCMOS & Dual Vth

[Usami-ISLPED02]

46

Combining MTCMOS and Dual VCombining MTCMOS and Dual Vthth

• Using MTCMOS for the entire circuit means the flip-flop values have to be saved and restored every 100ms.- Significant delay and power overhead.

• Solution: use MTCMOS for selected gates only (i.e., those with low Vth transistors which are on the timing-critical paths of the circuit). All other gates in the circuit use high Vth or dual Vth transistors.- Use Dual Vth for the flip-flops.

• Assume one sleep transistor per cell.- Simplifies the analysis.

MTCMOS & Dual Vth

47

MTCMOS Cell GenerationMTCMOS Cell Generation

• Exclude Flip Flops and Latches• Exclude cells with small drive

- Unlikely to be on the critical path

• Exclude high fanin gates- Can be implemented by using 2-input gates.

• Develop complex library cells to speed up the timing-critical paths of the circuit, thereby, reducing the number of gates that must be implemented in MTCMOS.

• Overall 56 MTCMOS cells were developed using low-Vth transistors for logic.

MTCMOS & Dual Vth

48

OutlineOutline

• Sources of Leakage in CMOS VLSI Circuits• Circuit and CAD Techniques for Leakage Minimization• MTCMOS• Charge Recycling MTCMOS• Conclusion

49

Charge Recycling MTCMOSCharge Recycling MTCMOS

• Charge recycling technique uses both NMOS and PMOS sleep transistors.

• Circuit C is divided into 2 sub-circuits:- Sub-circuit C1 is connected to SN

- Sub-circuit C2 is connected to SP

C1 C2

Connections between C1 and C2

VDD VDD

G

PSP

SN

CR-MTCMOS

50

Mode Transitions in This ConfigurationMode Transitions in This Configuration

e-e-

C1

Vdd

C2

Vdd

1

0

0

Vdd

Active Sleep

0Vdd

01

Td, Ed

T’d, E’d

CR-MTCMOS

51

Our Solution: Charge Recycling (CR)Our Solution: Charge Recycling (CR)

e-e-

C1

Vdd

C2

Vdd

1

0

0

Vdd

Active Sleep’

0Vdd

01

CRON

CROFF

Sleep

01Vdd/2

Vdd/2

CR-MTCMOS

52

Energy Consumption in CREnergy Consumption in CR

• Replacing CR element with an ideal switch, M:

C1

C2

VDD VDD

G P

t=ta0<ta

t=ts0>tsSN

SP

CG CP

M

CR-MTCMOS

53

Energy Consumption in CR (cont.)Energy Consumption in CR (cont.)

• Energy consumption during mode transition:

where we have:

( ) 21 DDPactivesleep VCE α−=−

( ) 21 DDGsleepactive VCE β−=−

eCapacitancGroundVirtualTotal

eCapacitancPowerVirtualTotal

and

=

=

+=

+=

G

P

PG

P

PG

G

C

C

CC

C

CC

C βα

CR-MTCMOS

54

Energy Saving Ratio (ESR) in CREnergy Saving Ratio (ESR) in CR

• Energy consumption in one cycle for the conventional MTCMOS and CR-MTCMOS:

• The energy saving ratio is:

• ESR is maximum when X=1, i.e., when .

22DDPDDGCR VCVCE βα +=

22. DDPDDGconv VCVCE +=

( )_

2

2( )

1total cr total

total

E E XESR X

E X

−= =

+

G PC C=

CR-MTCMOS

55

Charge Recycling Operation Charge Recycling Operation

0 0.1 0.2 0.3 0.4 0.5 0.6-0.2

0

0.2

0.4

0.6

0.8

1

1.2

Time (ns)

Vo

ltag

e (V

olt

)

VG

VP

VCR

CR-MTCMOS

56

Effect of the Threshold VoltageEffect of the Threshold Voltage

• Condition for a complete CR (assuming CG=CP):

- If Vtn=|Vtp|, then a simple NMOS will be adequate.

• Solution: decrease Vt- Trade off: leakage current increases.

{ }2

, DDtptn

VVVMin ≤

CR-MTCMOS

57

Effect of Transistor SizingEffect of Transistor Sizing

• The larger the transmission gate (TG), the faster the charge recycling operation

• Trade off: larger TG switching power penalty- Ctg denotes the input cap of NMOS and PMOS in TG.

0

VDD

( ) PG

tg

DDPG

DDtg

total

totaltg

CC

C

VCC

VC

E

E

+=

+=− 44

2

2

CR-MTCMOS

58

Leakage AnalysisLeakage Analysis

C1

Vdd

C2

Vdd

0

1

0

• TG adds a new leakage path:

• Transistors in the TG must be high Vt transistors.

CR-MTCMOS

59

Leakage Paths in Conventional TechniqueLeakage Paths in Conventional Technique

• The equivalent leakage model for the sleep mode:

VDD VDD

r1

RN

RP

r2

• Leakage is calculated by writing KVL equations (RN=RP=R):

R

VP DD

convleakage

2

.

2=−

CR-MTCMOS

60

Leakage Paths in CR TechniqueLeakage Paths in CR Technique

where (RN=RP=R and RTG=nR):

• The equivalent leakage model in the sleep mode:

RN

VDD

r1

VDD

RP

r2

RTG

r1*

r2RN

r3*r2

*

VDD

∆ γ

Rn

n

RRr

RRr

rn

n

RRr

Rrr

rnRRr

Rrr

PTG

TGP

PTG

TG

PTG

P

1

1

1

1

1

*3

11

1*2

11

1*1

+=

++=

+=

++=

+=

++=

CR-MTCMOS

61

Leakage in CR TechniqueLeakage in CR Technique

R

V

nP DD

CRleakage

212 ⎟

⎠⎞

⎜⎝⎛ +=−

r1/(n+1)

r2R

nR/(n+1)nr1/(n+1)

VDD

• Leakage is calculated by writing KVL equations:

• Leakage has increased by a factor of 1/2n .

CR-MTCMOS

62

Leakage in CR Technique (cont.)Leakage in CR Technique (cont.)

• If n=2, there is 25% increase in the leakage:- For short and medium sleep periods, this increase is negligible

compared to the saving that we get from the CR technique- For long sleep periods, we must use larger n

by choosing transistors with smaller W/L ratiosin the TG

- This is also beneficial from the layout areapoint of view

- Potential disadvantage: CR takes longerto complete.

CR-MTCMOS

63

Ground Bounce (GB) AnalysisGround Bounce (GB) Analysis

• Simple wake-up circuit model for GB analysis:

L

R

CG

t=0

SN

+

-VG(t=0)=V0

• For conventional MTCMOS: V0=VDD

• For CR MTCMOS: V0=VDD/2

CR-MTCMOS

64

Ground Bounce Analysis (cont.)Ground Bounce Analysis (cont.)

• It is well known that:- The positive GB peak occurs when SN operates in saturation

region- When operating in the saturation region,

drain-source current of SN, and thus the GB value,dose not depend on the V0 value

- In CR-MTCMOS, the positive GB peak value remains unchanged- The negative GB peak occurs when SN operates in

linear region. This changes in CR-MTCMOS.

CR-MTCMOS

65

Ground Bounce Analysis (cont.)Ground Bounce Analysis (cont.)

• Equivalent circuit model when the negative GB peak happens (rDS is the ON resistance of SN):

L

R

CGrDSVG(t=0)=V0

+

-

• RLC circuit with initial voltage value V0 on CG.• In CR-MTCMOS:

- V0 is reduced by 50%- Negative GB peak value is reduced- Settling time is lowered.

CR-MTCMOS

66

Ground BounceGround Bounce

0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8

-0.25

-0.2

-0.15

-0.1

-0.05

0

0.05

0.1

0.15

Time (ns)

Gro

un

d L

ine

Vo

ltag

e (v

olt

)

Conventional

Charge Recycling

CR-MTCMOS

67

Experimental Results for the 90nm CMOS NodeExperimental Results for the 90nm CMOS Node

45%842.6153224022310C7552

40%628.2104720472100C6288

44%357.363813071320C5315

43%276.949015451500C3540

41%72.6123573578C2670

46%20.538275.63267C1908

40%7.212125.42132C1355

43%5.710232.73240C432

45%1629489.614949Sym

CRConv.CRConv.

Energy Saving

(%)

Mode Transition Energy Cons.

(pJ)

Wake up Time(ps)Circuit

-4%

2.5%

0.1%

-3%

0.9%

-3%

5%

3%

0.9%

Wake Up Time

Reduction(%)

CR-MTCMOS

68

SummarySummary

• Leakage currents are rising fast and must be controlled by circuit design and optimization tools

• Gate leakage is rising at the fastest rate, but is expected to be controlled by the introduction of high-K dielectric material; thus, subthreshold leakage remains the most worrisome component of standby power dissipation

• Most of the power reduction techniques described depend on trading off timing slack for power at the cell level. Even the block-level approaches are often combined with the cell level approaches.

• Dual-Vth designs and MTCMOS technique appear to be the most effective solutions for minimizing the subthreshold leakage current.

• CR-MTCMOS nearly cuts the power consumption for mode transition in half. The technique is most applicable in designs with frequent power mode transitions.

Conclusions