charge transfer ed pre sensing

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22-4Charge-Transferred Presensing and Efficiently Precharged Negative

Word-Line Schemes for Low-Voltage DRAMSJae-Yoon Sim, Young-Gu Gang, Kyu-Nam Lim, Joong-Yong Choi,Sang-Keun Kwak, Ki-Chul Chun , Jei-Hwan Yoo, Dong-I1 Seo, Soo-In C ho

Memory Product and Technology Division, Samsung Electronics, Korea

AbstractA 256Mb SDRAM is implemented with a 0.12pm tech-

nology to verify two circuit schemes suitable for mobileapplication. A charge transferred presensing is proposedto achieve fast low-voltage sensing and robust operation.With a precharge disabler for productivity, new negativeword-line scheme is also proposed to bypass t he majorityof discharging current to VSS without switching control.Keywords:D RAM, low-vol tage, sensing

In t roduc t ionLow power requirements in mobile system have driven

the low voltage trend of DRAM product which seeks forchallengeable circuit and process technologies to improveperformance as well as stability. Though DRAM has suc-cessfully managed to move down to 1.8V era[ l] , furthervoltage scaling has been limited by critical problems suchas sensing speed degradation, tightened power budget,and retention characteristics.

Fig. 1shows the bit-line(BL) flipping affected by VCC-precharged IO lines in the conventional VBL(=VCCA/Z)precharged BL scheme. VCC and VCCA represen t in-ternally generated voltage sources for periphery and ar-ray, respectively. Thi s BL flipping error occurs whenCSL is enabled too fast after the sensing star t under thecircumstances of process/design-induced skews, such asmismatch in threshold voltages of N3 and N4 and dif-ference in resistance between BL-to-IO and BLB-to-IOBpaths. Such performance degradation by th e BL flippinghrcnmes more serioiis in low voltage operation du e to thereduced da ta keeping capability of t he latcb(N1, N2, P1,

Chargetrans ferred presensing(CTPS) schemes[2][3]re-moved the BL flipping by precharging the sensingBLs(SBL, SBLB) with high level. Fig. 2shows th e circuitand timing diagrams of a typical CTPS scheme. ThoughCTPS schemes improved the low voltage sensing, they aredifficult to be implemented due to the complex constraintsin the additional bias levels(Vmid and VH) and ratios ofcapacitances(Ccm,L, C B L and CSBL) o guarantee N5an d N6 to be operated in the saturation region[2].

The small rnrrent driving capability of the cell accesst,ransist,nr i s st,ill another limit,nt,ion factor for low voltageoperation. Th e threshold voltage of th e cell access tran -sistor i s not, sralahle along with operati ng voltage d ue t o

/

Pa).

. .Fig. 1. BL flipping resulted from the early timed CSL andmismatch in each BL-to10 line paths in the conventionalhalf-VCCA precharging scheme.

PR E 0 SAN ,OB10

~ ~ - -CCA(a )PRE- - - - "CC---.SS- - ~ *CCA~~-SS---.PP

PSE, charge rannlsrred Pre~mnng

SAN man N~SeNiw

. . . ! ~ ~ ~ ' ~ ~ ~ ~ ~ . . . ~BL*Vlnrn- - - - "SS,so,S B V S B L B . ~ ~ ~ ~ ~ . . . . . . . . . . ...*"",'. ..-. ---- "CCA, -..- . . ~ ~ - -

- - - * ssFig. 2. Circuit(a) and timi!&) diagrams of theconventional CTPS scheme.

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-~-,C Umal" P-llnsmpsBusBLB ............. ~~ ...... ~ ~ . . ~...., ..~../ , -..~s sBUBLB (b)Fig. 3. Circuit(a) and timing(b) diagrams of the proposedCTPS scheme. (a )t,hn retention time requirements. Furthermore the gen.eration of higher VPP from low voltage requires multi-stage pumping with poor efficiency[l]. Addressing thoseissues, negative word-line(WL) schemes have been pro-posed[4][5][6].Negative bias generation by charge pump-ing, however, requires large current consumption, causingserious fliirt,uations during the fast-cycle operation.

Tightened current allowance of mobile application atpower-down or self-refresh mode is another critical prob-k m in the negative scheme. In terms of productiv-ity, significant portion of DRAM product is exposed toWT.-to-RT. hridge defects during the fabrication process.Though the bridges are repairable with redundant WLs orBLs, the amount of current flowing through the bridgesstill remains after the repair. So charge pumping is re-quired to compensate the leakage current flowing to the *negative bias, resulting in additional current consumptionwhich is not in the ground-precharged WL scheme. Theinrrease of current in the power-down modes causes sig- .nificant yield loss in productivity.

Charge Transferred Presensing

px.- - -"PP

- - -VCCA- - - v s 5- - - YRRl

(b)Fig, 4. Circuit(a) and timing(h) diagrams of the proposednegativeWL scheme used in a typical array with local SWDs.

m , , ~ B L ~ .

........~~ ...... ~~ .......Fig. 3 shows circuit(a) and timing(b) diagram of the i~~

sharing phase, enable switches(N7 and N8) for the pro ~sensing turn on. Then SBL and SBLB are developed !W Lfollowed by regenerating amplification with the positive i yBBifeedback configuration of N9 and NI0 and the pull-upsensing by P1 and P2. This regeneration guarantees ro-hitst. operation without additional bias voltages; eliminnt-ing the complex constraints in the conventional CTPS[2].

CTPS scheme proposed in this work. After the charge

by the presensirig with N9 and N10. The presensing is' ~ ~ - - - - - ~ ~ - - - - - - . ~ ~ - - - - - ~ ~ ~ ~ ~ - - - - '~ i ~ ,. proposed VBL.precharKe disabling circuit.

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0 ... ; ......p- .......... ....., ..........~...~ . . ~ .: SAN discharge 10 V002 -... . ~ .

0 20 40 timelns) 60 80 100-0.51 4g, ...~................~~.~~~~ ........~,

j.WL.5

0 1Fig. 6. Simulated waveforms of a sensing and precharge cyclefor the conventional(a)and the proposed(b) sensing schemesshown i n Fig. 1and Fig. 3, respectively.

After the main pull-down sensing enabled by high-to-low- transition of SAN, RSTi goes to VP P level to restorethe sensing result t o the storage cell.

Negatively Precharged Word-Line SchemeFig. 4 shows circuit(a) and timing(b) diagrams of th e

proposed negative WL scheme used in a typical array wi thlocal sub-word decoder(SWD). VBBZ represents the neg-ative bias for the precharged WLs. At the start of theprecharge phase, WL and heavily loaded PXD dischargeto both VSS and VBBP simultaneously. The majority ofthe discharging current flows to VSS through WZ: pull-down NMOS of I1 and W1, due to their large W /L atioand high gate bias. When PX D becomes lower than Vtn,W1 turns off. Then W3 and W4, with small W/L atios,slowly discharge th e rest of charge to VBBZ.

Subsequently the discharging pa th of WLE is switchedfrom VSS tu VBBP in response to the voltage of WLEitself. W3 and W4 should have high-Vtn to minimizeleakage current caused by positive Vcs during the phaseof WL activation. About 60-percent of current flowing toVBBZ is reduced by minimizing VBBZ transition of WLcontrol signals and bypassing the discharging current ofthe heavily loaded nodes to VSS.To use the negative WL scheme fur mobile product,th e leakage current caused by the WL-to-BL bridge defectshould be removed. Fig. 5 shows a disabling scheme ofVBL-precharge. If W / L ratio of NE4 is designed to be

100

50

0

-50

proposed-conventional

I0 2 4 6 8 10 12time alter sensing(ns)

Fig. 7. Simulated results of the differential sensing currentflowing through CSL gates, i(I0)-i(IOB), n theconventional(Fig. 1) and the proposed(Fig. 3) sensingschemes.

very small, the WL-to-BL bridge pulls down BL and BLBto almost VBBP. T ha t results in bit-failures along columndirection which can he repaired by column redundancy.At the repair stage, by cutting the fuse F1 to disableCSL, EQ E is also disabled to VBBZ, which eliminatesVBL-to-VBB2 current path through NE4, NEZ, and NS.

Resu l t sTo verify the proposed schemes, a 256-Mb SDRAM was

designed and fabricated with a 0.12prn technology. Fornormal operation, VCC, VCCA, VPP, and VBB2 weredesigned to be l.GV, 1.3V: 2.9V, and -0.4V, respectively.6 shows simulated waveforms of a sensing andprecharge cycle for the conventional(a) and the pro-posed(b) sensing schemes showxi in Fig. 1and Fig. 3 ,respectively. For the precharge scheme: the proposed neg-ative WL scheme shown in Fig. 4 was applied to bothcases. The CT PS scheme gives abou t 17-percent largervoltage difference a t the end of the charge sharing phase,because th e effective BL capacitance was reduced by theisolation of SBLs. .4s shown in Fig. 6, the proposedCTP S achieved fast development of SBL and SBLB fromthe start of the sensing. Th e slow high-to-low transitionof WL when WL is less than 0.7V does not degrade theprecharge performance, since th e cell access transistor al-most turns off when WL is less than l\.

Fig. 7shows simulated resul ts of the differential sens-ing current flowing through CSL gates, i (I0 )-i (IO B) , inthe conventional(Fig. 1) and the proposed(Fig. 3) sens-ing schemes. Wit h th e asymmetric BL-to-IO line modelas designed, 70mV-mismatch in threshold voltage of CSLgates was introduced in this simulation tu verify the im-munity against the BL flipping. While t h e conventionalscheme suffers from the BL flipping when the sensing-to-CSL time is up to 3ns, the proposed CTPS makes it

Fig.

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possible for CSL to be timed from the start point of thesensing. With this simulation, improvements in the min-imum allowable RAS-tc+CAS delay of 3ns is expected atVCCA=1.3V.

Fig. 8shows a photomicrograph of the test chip. Toverify the effect of the proposed sensing scheme, A andC banks were allocated for CTPS, and B and D banksfor the conventional scheme. Each bank has two casesof Cb/Cs ratios, 5 .3 and 7. The chip size overhead was3.2-percent for CTPS , and 0.9-percent for negative WLschemes, respectively.

Fig. 9 shows measured shmoo plots of RAS-to-CASdelay vs. voltage(=VCC=VCCA). In the proposed sens-ing scheme, the minimum RAS-to-CAS delay was 12nsat VCC of 1.3V showing less sensitivity t o voltage varia-tion. The improvements were more dramatic in th e case oflarger Cb/Cs ratio, because the readout performance de-pends on the voltage difference between SBL and SBLB,not being affected by the capacitance of BL and BLB.

Fig. 10 shows measured current vs. voltage(=VCC=VCCA), with act ive cycle time of 15011s. Tobreak down the pumping current for VBBP generation,power for the negative charge pumping was driven by aseparated pin. Comparing with simulated current for di-rect discharging case, the proposed WL scheme reducedabout 60-percent of pumping current.

ConclusionsA charge transferred presensiug and a negative word-

line schemes were proposed to achieve high performanceand stability for low voltage mobile application. The im-plemented schemes were verified using a 256Mb SDRAMwith a 0.12Wm technology. The proposed CTPS improvedR.AS-tc+CAS delay being free from th e design constraintsrequired in the conventional CTPS. Without loss in pro-ductivity, the negative WL scheme automatically switchesthe discharging path in response to the discharging nodesitself eliminating additional switching control.

References[l] J . Y. Sim, et al., "Double boosting pump, hybrid current

sense amplifier, and binary weighted temperature sensoradjustment schemes for 1.8V 1ZBMb mobile DRAMS,"Dig.Symp. VLSI Cir. , pp. 294-295, 2002.[ Z ] M. Tsukude, et al. , "A 1 .2V to 3 .3V wide voltage-

range/low-power DRAM with a charge-transfer presensingscheme," IEEE JSSC, pp. 1721-1727, Nov. 1997.

[3] L. Heller, et al. , "High sensitivity charge-transfer senseamplifier," IEEE JSSC, pp. 596-601, Oct. 1976.[4] H. Tanaka, et al., "A precise on-chip voltage generator

for a gigascale DRAM with a negative word-line scheme,"I E E E JSSC, pp. 1084-1090, Aug. 1999.

151 H. Yamauchi, et al., "A circuit technology for self-refresh16Mh DR.AM with less than 0.5 uA/MB data-rdentioncurrent,'' IEEE JSSC, pp. 1174-1182, Nov. 1995.

161 T. Yamagata, et al., "Low voltage circuit design techniquesfor hat.tery-operated and/or giga-scale DRAM'S," I E E E.ISSC, pp. 1183-1188, Nov. 1995.

Fig. 8. Photomicrographof the test chip.l 0 . m , 2 m 4 . m ii.m ,mm0 1o.m I Z W S W m s iwms I"!Tim! !E!

. . I. . . . . . . . . . . . I__.-_.

I, ......l....^. _I*I -.......!8. ..........~."............-.,,. . "" . ...,*."......-......__.I. . . . . .r----.

....._........... -....................................................................."...................-................ _. ........ -._~~~~ ~~~ ~~~~ ...-........... ."....*.*.. .._.."..-....-. .-..".",-............ .-. ...!. , ..............".-.....-........I".._-..tX."l~ ~~~ ~~.........- ...... -........... ".~........"...!X- ..l...."-.... . . . . . . . .-.......---__lo.- #*OR1 l 4 . m 1 s m l B m s l O . m S 1 2 m 14.- 16." l a m s

(c) new(Cb/Cs=5.3) (d) new(CWCs=7)Fig. 9. Measured shmoo plot of RAS-to-CAS delay vs.voltage, when the conventional(a,b) and the proposed(c,d)sensing schemes were used.

I I I I I

1 measured operating cur+

4imulated current for direct discharge to VEB5 I \current for negative charge pumpL I I I I

1,o 1.2 1.4 1.6 1.8 2.0 (VIFig. 10. Measured current YS. voltage with active cycle timeof 15011s. (total operating current and current for chargeP mP ng1

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charge transfer ed pre sensing

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