chen, jason 2020.04ย ยท 14 real device effects incorporated into the model self-heating effect core...
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CHEN, Jason 2020.04.21
Application Engineer
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โข Quick Start for IC-CAP
โข Introduction to ASM-HEMT Model
โข Introduction to CMC Modeling Kit (ASM-HEMT) in IC-CAP
โข Export Model to ADS for Load-pull Simulation
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โข Integrated Circuit Characterization and
Analysis Program
โข Integrate measurement and modeling on
the same platform
โข Support various simulators and python
script
โข Support customized GUI and extraction
flow
โข Suitable for highly customized modeling,
such as RF and Power devices
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5G
PIB
LA
N
IC-CAP
Platform
WaferPro
WProXP
Instruments
Switch Matrix
Prober
Instruments
Prober
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Different types of model, such
as HEMT, MOSFET, BJT
Different dimensions of same type of
model, such as A100x10, A100x8
Different measurements of the same
device, such as IdVg, IdVd, Sparam
Configurations and Extractions of
the same measurement
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Inputs: Define the Stimulus/Bias to be applied
Outputs: Define the Data to be Measured
Define Unit Names in Setup
to map to Unit Names
defined in the Instrument
Configuration settings in
the Hardware Window
Hardware Window
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A D VA N C E D S P I C E M O D E L F O R H E M T
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H O W D O E S A G A N D E V I C E W O R K ?
โข quantum well at the heterojunction interface โ
2 Dimensional Electron Gas (2-DEG)โข very high mobility
โข Low resistance
โข Difference between AlxGa1-xN and GaN
spontaneous polarization (PSP) creates
a sheet charge at the interface.
โข Difference in lattice constants leads to
mechanical strain and piezoelectric
effect (PPE)
AlxGa1-xN
GaN
PSP
PSP
AlxGa1-xN
GaN
PSP
PSP
PPENegative 2DEG
Sheet charge
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Analytical Solution of
Schrำงdigerโs & Poissonโs
SP-Based Current &
Charge Model
Noise, Trapping, Self-
Heating, Field Plate
2-DEG Charge, Ef,
Surface Potential
I-V, C-V, DIBL, Rd, Rs,
Vel. Sat., ...
DC, AC, Transient
Harmonic Sim.,
Noise, ...
Electrostatics
Transport
Higher-order Effects
Source: Prof. Yogesh Chauhan
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โข Better Model Scalability โ L, W, NF, Lsg, Ldg, Temperature etc.
โข Better Temperature Scalability
โข Device Insight
โข Better Statistical Behavior
โข Accurate Charges and Capacitances
โข Less number of parameters โ Easier parameter extraction
โข Uses a single expression for all regions โ Faster convergence, smooth
derivatives
โข Inherent Model Symmetry and Continuity
Source: Prof. Yogesh Chauhan
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Real Device Effects Incorporated into the Model
Self-Heating Effect
Core Model Parameters
Parameter Description Extracted Value
๐๐๐น๐น Cutoff Voltage โ2.86 ๐
๐๐น๐ด๐ถ๐๐๐ Subthreshold Slope Factor 0.202
๐ถ๐ท๐๐ถ๐ท SS Degradation Factor 0.325 ๐โ1
๐0 DIBL Parameter 0.117
๐0 Low Field Mobility 33.29 ๐๐2/๐๐
๐๐0๐ด๐ถ๐ถ๐ AR 2DEG Density 1.9๐ + 17 /๐2
๐๐๐ด๐๐ด๐ถ๐ถ๐ AR saturation velocity 157.6๐ + 3 ๐๐/๐
๐ ๐๐ป0 Thermal Resistance 22 ฮฉ
Core drain current expression
Source: Prof. Yogesh Chauhan
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Set L, W, NF, Tbar
Device Dimensions
Extract VOFF, NF, CDSCD,
ETA from log-IDVG, LINEAR
And Saturation
Extract U0, UA, UB and RDS
from IDVG-LIN
Extract VSAT, Improve ETA
From LINEAR IDVG
Extract LAMBDA, Improve
VSAT, ETA from IDVD
Temperature Parameters
Capacitance Modeling
Model Implemented in Verilog-A
Simulations performed in: ADS, Spectre, HSPICE
Parameter Extraction available in IC-CAP Software
Source: Prof. Yogesh Chauhan
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Start with ๐ผ๐ โ ๐๐ characteristics in the log scale
๐ฌ๐ป๐จ๐ โ DIBL Parameter
๐ต๐ญ๐จ๐ช๐ป๐ถ๐น โ Sub-threshold slope parameter
๐ช๐ซ๐บ๐ช๐ซ โ Captures the drain voltage dependence on
the sub-threshold slope.
๐ฝ๐ถ๐ญ๐ญ โ Cut-Off Voltage
๐ผ๐ โ ๐๐ characteristics in the linear scale
๐ผ๐ โ Low field mobility
๐ผ๐จ,๐ผ๐ฉ โ Mobility degradation parameters
Source: Prof. Yogesh Chauhan
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๐ผ๐ โ ๐๐ characteristics
โข ๐ฝ๐บ๐จ๐ป โ Velocity saturation parameter
โข ๐ผ๐จ, ๐ผ๐ฉ โ Mobility degradation parameters
Access Region Parameters extracted from ๐ผ๐ โ ๐๐characteristics:
โข ๐ต๐บ๐๐จ๐ช๐ช๐บ(๐ซ) โ 2DEG density in the access region.
โข ๐ฝ๐บ๐จ๐ป๐จ๐ช๐ช๐บ โ Saturation velocity in the access region.
โข ๐ผ๐๐จ๐ช๐ช๐บ(๐ซ) โ Low field mobility in the access region.
๐0๐ด๐ถ๐ถ๐(๐ท) independently tunes the access region resistance
around Vds = 0 and helps extract ๐๐๐ at that point.
Source: Prof. Yogesh Chauhan
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๐ผ๐ โ ๐๐ characteristics โ Self Heating Parameters
โข ๐น๐ป๐ฏ๐ โ Self heating resistance.
โ Decides the rate of temperature increase with
increasing current.
Temperature dependence parameters to observe the effects of the temperature increase on IV
characteristics:
โข ๐ผ๐ป๐ฌ โ Temperature dependence of mobility
โข ๐จ๐ป โ Temperature Dependence for saturation
velocity
Source: Prof. Yogesh Chauhan
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Nonlinear variation of source/ drain
access resistances with Ids.
Geometrically scalable
Source: Prof. Yogesh Chauhan
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Second slope in ๐๐โ self-heating in the device.
Reason: Self heating has
significant impact at high
gate and drain biases where
the current is high.
The first slope in ๐๐โ velocity saturation in the
access region.
Source: Prof. Yogesh Chauhan
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Rd/s increases significantly with increasing temperature
Temperature dependence of 2-DEG charge density
in the drain or source side access region:
Temperature dependence of Saturation Velocity:
Temperature dependence of electron Mobility:
Source: Prof. Yogesh Chauhan
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Affects capacitance and breakdown behavior.
Source: Prof. Yogesh Chauhan
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23Source: Prof. Yogesh Chauhan
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Stephen Sque - ESSDERC tutorial Sept. 2013
Source: Prof. Yogesh Chauhan
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๐๐บ๐๐
๐๐ท๐๐ Quiescent Bias Condition
Measurement during pulse
condition
Source: Prof. Yogesh Chauhan
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0, 0
-8, 0-8, 0
-8, 20
Vgq, VdqVgq, Vdq
Gate-lagโข Vdq = 0V
โข Vgq = Deep OFF condition:
A strong field through the AlGaN
layer. No field through buffer
(since Vds = 0). Only surface
traps activated.
Drain-lagโข Vdq = A significantly positive voltage
โข Vgq = Deep OFF condition:
A strong field through the AlGaN
layer as well as the buffer. Both
surface and buffer traps activated.
RON Collapse:
Trapping reduces the 2DEG
concentration and leads to an
increased on-state resistance.
Source: Prof. Yogesh Chauhan
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Pulsed-IV Scheme used to simulate the P-IV Characteristics in IC-CAP
TRAPMOD=2
Source: Prof. Yogesh Chauhan
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Vtrap is then used to tune:โข Cut-off voltageโข DIBLโข Source and drain access resistances
TRAPMOD=1
โข Vtrap is used to model the Vgd dependence on just
the drain-side access region resistance.
โข Recommended for modeling the GaN power
device dynamic ON-resistance.
โข An empirical temperature dependence is also
included.
TRAPMOD=3A single sub-circuit to capture the dependence on both Vg
and Vd by using Vgd instead of Vgs and Vds separately.
Source: Prof. Yogesh Chauhan
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Pulsed โ IV chacteristics for multiple quiescent conditions
Knee walkout โ linearity and efficiency
The trap model accurately captures
Dynamic-RON and knee walkout.
Pulse Width โ 200 ns, Duty-cycle 0.02 %
Source: Prof. Yogesh Chauhan
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๐ฟ๐ฅ๐๐
๐ฟ๐ฅ๐๐
๐ฟ๐ฅ๐
๐
GMF
SMF
DMF
Extrinsic
Manifolds
Overlap
๐ถ๐๐ ,๐๐ถ๐บ๐๐
๐ถ๐บ๐ท๐
๐ถ๐๐,๐
๐๐
๐ ๐ ๐ ๐
๐ ๐
๐๐๐
ASM-GaN-HEMT
๐๐๐ ๐
๐๐
๐ถ๐ท๐๐๐ถ๐๐ ,๐
๐๐
๐ ๐
๐๐
๐๐กPDK
โข Model
โข Core surface potential based PDK
โข Access region resistances included in core
โข Bus-inductances in extrinsics
Pad-level Small Signal Equivalent Circuit Model
Device Layout
CGSO, CGDO, CDSO
bias-independent
capacitances
intrinsic capacitances:
CGS,i, CGD,i and CDS,i
bias dependent
Source: Prof. Yogesh Chauhan
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โข Three step methodology
โข De-embed manifolds
โข Extract the intrinsic core model - Using low frequency Y-parameters
โข Extract Inductances - Using high frequency Y-parameters
Measure S-
parameters including
de-embedding
structures
Convert to Y-
parameters
Extract L, C, gm, gds,
Rg etc.
Source: Prof. Yogesh Chauhan
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Three step methodology1. De-embed manifolds
2. Extract the intrinsic core model - Using low
frequency Y-parameters
3. Extract Inductances - Using high frequency Y-
parameters
โข The effect of bus-inductances is ignored at low frequencies
(assumption)
โข Drain & Source access region resistances ignored from
hand analysis (not an assumption, it is an advantage)
โข Ignore some terms at low frequency (~ 10 GHz)
(assumption)
โข Very simple โ only need to adjust overlap capacitances &
gate finger resistances (advantage)
[1] I. Kwon et al., IEEE Trans. Microw. Theory Techn., 50 (6), [2002]
[1]
[1]
Source: Prof. Yogesh Chauhan
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Core GaN
Model
Khandelwal, et al, BCICTS, 2018
Nonlinear Circuit Simulation and Modeling,
Cambridge University press
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A S M - H E M T
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_DeviceA_5053_8x100~DC_MODELING~ig_vgs__Input
prefix Dut name Setup name
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Live Demo for GaN Modeling GUI
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<<ๆญฅ้ฉ>>1.้ปๆModel Parameters้ ้ข2.้ปๆSave As3.้ธmps & ่จญ็ฝฎ่ทฏๅพโๅๅพmps file
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GaN RF Workshop โ Design A Single Stage PA
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45GaN RF Workshop โ Design A Single Stage PA
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<<ๆญฅ้ฉ>>1.ๅตๅปบschematicๅพ,ไฝฟ็จtools้ฒ่กๅๆธๅฐๅ ฅ2.่ชๅๅธถๅบ ASM_HEMT_M model card3.็ฑไบๆๅค้จๅๆธ,ๅ ๆญคๆWarning(้่ช่กๅปบๆง)4.่ช่กๅปบๆงๅค้จๅๆธ่ASM_HEMT_5N้ฃๆฅ
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46GaN RF Workshop โ Design A Single Stage PA
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<<ๆญฅ้ฉ>>1.ๅปบ็ซ4T symbol2.ๆพๅ ฅschematic3.้ปๆsimulation
![Page 47: CHEN, Jason 2020.04ย ยท 14 Real Device Effects Incorporated into the Model Self-Heating Effect Core Model Parameters Parameter Description Extracted Value ๐ Cutoff Voltage โ2.86](https://reader033.vdocument.in/reader033/viewer/2022050120/5f50ebbb2ff4156d990570d5/html5/thumbnails/47.jpg)
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๐บ๐๐๐ =๐๐๐ข๐ก๐๐๐
๐๐ด๐ธ =๐๐๐ข๐ก โ ๐๐๐
๐๐๐
๐ท๐๐๐๐ ๐ธ๐๐๐๐๐๐๐๐๐ฆ =๐๐๐ข๐ก๐๐๐
๐๐๐
๐๐๐๐ ๐
Source: Prof. Yogesh Chauhan
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โข Determine Optimum load impedance for
maximum Pout and PAE performance
โข Specify matching networks
โข Understand tradeoffs!
[M. S. Hashmi et. al, IEEE Instrum. Meas. Mag., 16 (2), Feb., (2013)] Source: Prof. Yogesh Chauhan
![Page 49: CHEN, Jason 2020.04ย ยท 14 Real Device Effects Incorporated into the Model Self-Heating Effect Core Model Parameters Parameter Description Extracted Value ๐ Cutoff Voltage โ2.86](https://reader033.vdocument.in/reader033/viewer/2022050120/5f50ebbb2ff4156d990570d5/html5/thumbnails/49.jpg)
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ADS Schematic for simulation of load-pull contours 22 dBm signal @ 10 GHz
Pout & PAE load pull contours for 10 mA/mm Pout & PAE load pull contours for 100 mA/mm
[1] S. A. Ahsan et al., IEEE J. Electron Devices Society, Sep., [2017] Source: Prof. Yogesh Chauhan
![Page 50: CHEN, Jason 2020.04ย ยท 14 Real Device Effects Incorporated into the Model Self-Heating Effect Core Model Parameters Parameter Description Extracted Value ๐ Cutoff Voltage โ2.86](https://reader033.vdocument.in/reader033/viewer/2022050120/5f50ebbb2ff4156d990570d5/html5/thumbnails/50.jpg)
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Harmonic balance drive-up characteristics showing Pout, PAE & Gain
Time domain waveforms of drain voltage & current.
Load line contours spanning the IV plane
[1] S. A. Ahsan et al., IEEE J. Electron Devices Society, Sep., [2017]
Frequency 10 mA/mm 100 mA/mm
๐๐๐ฅ. ๐๐ด๐ธ
๐0 22.46 + ๐38.54 30.53 + ๐34.35
๐1 40.61 โ ๐93.39 37.32 โ ๐73.44
๐2 11.39 โ ๐0.07 14.77 + ๐10.83
๐๐๐ฅ. ๐๐๐๐
๐0 19.57 + ๐22.83 19.57 + ๐22.83
๐1 253.48 โ ๐65.72 253.48 โ ๐65.72
๐2 15.66 โ ๐31.21 15.66 โ ๐31.21
Source: Prof. Yogesh Chauhan
![Page 51: CHEN, Jason 2020.04ย ยท 14 Real Device Effects Incorporated into the Model Self-Heating Effect Core Model Parameters Parameter Description Extracted Value ๐ Cutoff Voltage โ2.86](https://reader033.vdocument.in/reader033/viewer/2022050120/5f50ebbb2ff4156d990570d5/html5/thumbnails/51.jpg)
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Live Demo for Load-Pull Simulation
![Page 52: CHEN, Jason 2020.04ย ยท 14 Real Device Effects Incorporated into the Model Self-Heating Effect Core Model Parameters Parameter Description Extracted Value ๐ Cutoff Voltage โ2.86](https://reader033.vdocument.in/reader033/viewer/2022050120/5f50ebbb2ff4156d990570d5/html5/thumbnails/52.jpg)
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โข RF GaN modeling is challenging but extremely important.
โข IC-CAP provides an easy-to-use kit for CMC GaN modeling.
โข The tuned parameters can be easily imported to ADS for design and verification.
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