1

2

Overview

Vertical – AMBA SVT VIP Reuse

Vertical – Sequence Reuse

Vertical – Connection Reuse

Horizontal – Configuration Reuse

Horizontal – Scoreboard Reuse

Horizontal – Coverage Reuse

Vertical and Horizontal – Debug Reuse

Acknowledge

Agenda

3

Over View

IP_MODULE_UVC

coverage svt_ahb_uvc[0..M](svt_ahb_master_agent)

predictor

scoreboard

ahb_master_if[0..M]

AMBA Fabric RTL

sequence

uvc_cfg

svt_apb_uvc[0..N](svt_apb_slave_agent)

svt_axi_uvc[0..K](svt_axi_slave_agent)

apb_slave_if[0..N] axi_slave_if[0..K]

amba_featurescfg

cfg

cfg

cfg

AMBA Fabric RTL connects a group of AMBA devices(AXI, AHB and APB).

Verification components reside at IP_MODULE_UVC, reuse happens here.

Vertical Reuse: IP -> SOC; Horizontal Reuse: Project_A -> Project_B.

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Vertical – AMBA SVT VIP Reuse (1)

AM

BA

Fab

ric

RTL

At IP level, AMBA SVT VIP works in active mode, it executes UVM sequence, generates master request or slave response stimulus to drive RTL signals.

At IP level, AMBA SVT VIP checks port protocol timing, collects functional coverage.

5

SOC _Level

AMBA Fabric RTL

AXI VIP AHB VIP

passive mode

IP_MODULE UVC

IP_Level

AMBA Fabric RTL

IP_MODULE UVC

AXI VIP AHB VIP

AHB RTL AXI RTL

Vertical Reuse – AMBA SVT VIP Reuse(2) At SOC level, AMBA SVT VIP works in passive mode, it monitors the transactions on AMBA

interface and send them to scoreboard for correctness check. At SOC level, AMBA SVT VIP checks port protocol timing, collects functional coverage.

6

Vertical – Sequence Reuse – RAL Sequence

class amba_uvmreg_sequence extends uvm_sequence;

ral_amba_register_model amba_reg_model;

amba_reg = amba_reg_model.get_reg_by_name(“RESET_REGISTER ");

amba_reg.write(status, wdata, .parent(this));

endclass

Register Abstraction Layer(RAL) Model should be reused from IP to SOC.

RAL Sequence , reuse from IP to SOC.

class reg2axi_adapter extends uvm_reg_adapter;

function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw);

function void bus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op rw);

endclass

Adapter is the key point, adapter changes when interface protocol changes

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Vertical – Sequence Reuse – Slave Response Sequence

class slv_rsp_seq#(type REQ = uvm_sequence_item)extends uvm_sequence;

mailbox #(REQ) req_fifo;

forever begin

req_fifo.get(m_req_item);

`uvm_send(m_req_item)

end

Typical Slave Response Sequence.

slv_rsp_seq virtual sequencer real agent sequencer

mailbox mailbox response_request_port

forever begin

p_sequencer.axi_slv_sqr.response_request_port.peek(resp_req);

p_sequencer.req_fifo.put(resp_req);

end

forever begin

p_sequencer.ahb_slv_sqr.response_request_port.peek(resp_req);

p_sequencer.req_fifo.put(resp_req);

end

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Connect static RTL world and dynamic UVM world by interface.

1) static RTL world: real interface. Dynamic UVM world: virtual interface.

2) uvm_resouce_db pass the real interface handle to virtual interface.

3) Bind the interface to RTL module, RTL module usually keeps same at IP and SOC level.

4) Both the bind and interface can be reused to SOC level.

Vertical – Connection Reuse(1)

UVM_TEST_BENCH

IP RTL

virtual interface

interface Interface path

uvm_resource_db

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Vertical – Connection Reuse(2)

bind `AMBA_MODULE svt_axi_slave_if axi_slave_if (

.araddr(AXI_SLV0_araddr),

...

module

initial begin

uvmpkg::uvm_resource_db#(virtual svt_axi_if)::set(“interface_registry

",`AMBA_MODULE.axi_slave_if, `AMBA_MODULE.axi_slve_if);

end

endmodule

uvm_pkg::uvm_resource_db#( virtual svt_axi_if) ::read_by_name("

interface_registry ",`AMBA_MODULE.axi_slve_if, axi_slave_if)

Bind connection keeps DV code separate from design code, better for reuse;

IP_MODULE_UVC retrieves the real interface handle, uses it at active or passive mode;

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Vertical – Connection Reuse(3)

amba_checker ();

property signal_apb0_timeout_cnt_cov;

$rose(start) |-> (($past(apb0_cnt, 1) >= (apb_timeout_clk_in -1))

endproperty

interface

bind AMBA_MODNAME amba_checker amba_checker(

.apb_timeout_clk_in (64)

...

Assertion is used to check signal timing, assertion usually connect to signals.

Put the assertion in interface and connect the interface to related signals by module bind.

Both the bind and assertion can be easily reused to SOC level.

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Horizontal – Configuration Reuse (1)

Design Parameters

IP_MODULE_UVC

predictor

scoreboard

coverage

sequence

AMBA VIP

feature_class

uvc_cfg

Project changes, design parameters changes, and UVC configuration need change.

A perl script helps convert design parameters to a system verilog class(feature_class) automatically.

The system verilog class (feature_class ) configures UVC configuration(uvc_cfg) .

The UVC configuration(uvc_cfg) can be reused to different projects.

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Configuration is configured by feature_class.

Project changes, feature_class changes automatically.

axi_env_cfg = new[feature_class.axi_slaves];

for(int i=0; i < feature_class.axi_slaves; i++) begin

$sformat(inst_name,"axi_env_cfg[%0d]", i);

axi_env_cfg[i] = svt_axi_env_cfg::type_id::create(inst_name);

end

Horizontal – Configuration Reuse (2)

for (int i=0; i<feature_class.axi_slaves; i++) begin

$sformat(if_name, ".amba_axi_slave_if%0d", i);

axi_env_cfg[i].vif_slv_path = {interface_instance_path,if_name};

axi_env_cfg[i].addr_width = feature_class.axi_addr_width[i];

. . .

end

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Horizontal – Scoreboard Reuse(1)

Here scoreboard is a comparator , check transaction correctness.

An out-of-order comparator makes no assumption that matching transactions will appear in the same order from the expected and actual sides. So, unmatched transactions need to be stored until a matching transaction appears on the opposite stream.

This structure is suited well for AXI protocol, each channel has ID, different ID may out of order, but same ID in order, so naturally AXI ID acts as index, transactions with same index do compare.

1) out of order scoreboard structure

typedef T q_of_T[$];

q_of_T received_data[IDX];

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index_id_ooo_scb #( type T = int, type PORT= uvm_sequence_item, type IDX = int, type index_id_type = get_index_id#(T, IDX))

uvm_scoreboard

index_id_ooo_scb#(axi_tran,uvm_sequence_item,char) axi_scb;

parameterize scoreboard arguments for different protocols - AXI, AHB, APB

Horizontal – Scoreboard Reuse(2)

class get_index_id #( type T = int , type IDX = int);

static function IDX index_id( input T a );

return a.id;

endfunction : index_id

endclass : get_index_id

get_index_id for different protocols – not adhere to AXI ID, user can create self ID according to project requirement.

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Horizontal – Coverage Reuse(1)

amba_coverage_callback_class extends uvm_callback

cover group properties

set_weight()

new()

sample()

Encapsulate cover group properties and related functions in a class.

Then UVM test bench can use central configuration to control cover group.

When do horizontal reuse, IP parameters are changed, so some cover groups and cover points aren’t on demand.

1)For unneeded cover group, configure this coverage group control bit to zero.

2)For unneeded cover point, configure its weight to zero.

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Dynamic Coverage.

Horizontal – Coverage Reuse(2)

class amba_ahb_msr_cov_cb extends uvm_callback;

function void set_weight(int page_boundary_wt);

cg_cov_ahb_msr_pkt.cp_addr_page_boundary.option.weight=p_wt;

endfunction : set_weight

function new(string _name = "amba_ahb_msr_cov_cb");

cg_cov_ahb_msr_pkt = new("cg_cov_ahb_msr_pkt");

endfunction : new

virtual function void write(svt_ahb_transaction _ref);

if (_ref.get_type_name() == "svt_ahb_master_transaction")

cg_cov_ahb_msr_pkt.sample();

endfunction : write

covergroup cg_cov_ahb_msr_pkt(string name)

cp_addr_page_boundary : coverpoint tr.addr[9:0]

{ bins addr_page_boundary_start = {[0:3]};}

endgroup : cg_cov_ahb_msr_pkt

endclass

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Debug Reuse – Debug Sequence

Debug effort usually takes the largest portion.

Run_opts '+uvm_set_type_override=debug_dummy, debug_full‘

1) factory is used to defer the object subtype decision to run-time

2) type could be changed at run time to support reuse.

Open question: What can a debug sequence do?

1) print TB, UVC, VIP configuration value;

2) print test bench topology;

3) change UVM_VERBOSITY at given time during simulation; eg. #0 UVM_LOW; #800ns UVM_HIGH; #200ns UVM_LOW;

4) check and report sequence status – FINISHED ? etc.

5) get the current list of objecting objects

(objects that raised an objection but have not dropped it)

. . .

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Debug – Protocol Analyzer

Protocol Analyzer allows user to visualize the bus activity at the transaction level instead of signal level. User can check full read and write packet content. About AMBA, it is especially useful for AXI protocol, like out of order, wrap, data before address, it groups all related channels in one packet.

19

Whiting Karl

Gao Teng-Fei

Wang Roman

Acknowledge

20

Trademark Attribution

AMD, the AMD Arrow logo and combinations thereof are trademarks of Advanced Micro Devices, Inc. in the United States and/or other jurisdictions. Other names used in this presentation are for identification purposes only and may be trademarks of their respective owners.

©2012 Advanced Micro Devices, Inc. All rights reserved.