chris basso apec seminar 2011

8/10/2019 Chris Basso APEC Seminar 2011

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1 Chris Basso APEC 2011

The Dark Side of FlybackConverters

Presented by Christophe Basso

Senior ScientistIEEE Senior Member


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Course Agenda

The Flyback Converter

The Parasitic ElementsHow These Parasitics Affect your Design?

Current-Mode is the Most Popular Scheme

Fixed or Variable Frequency?More Power than Needed

The Frequency Response

Compensating With the TL431


3/165


What is the Subject?

There has been numerous seminars on Flyback converters

Seminars are usually highly theoretical link to the market?

Industrial requirements usually not covered

This 3-hour seminar will shed lights on less covered topics:

Why the converter delivers more power than expected? Solutions?Books talk about compensation with op amps, I have a TL431!

The origin of the Right-Half Plane Zero, how do I deal with it?

Quasi-resonant converters presence increases, how do they work?

In a 3-hour course, we are just scratching the surface!


4/165


The Flyback, a Popular Structure

The flyback converter is widely used in consumer productsEase of design, low-cost, well-known structurePoor EMI signature, bulky transformer, practical up to 150 W

flyback 40 180 W Notebook

flyback 3 5 WCharger

flyback 10 35 W DVD player

Set-top box

Netbook


5/165


1

2

4

drv

7

5

drv

8

9 12

11

drvVout

VoutVout

gnd gnd

buck-boostground referenced

buck-boostinput referenced

flybackisolated ground referenced

a b c

VinD

C

SW1

L

1 N

Vin

D

C

SW1

L

Vin

SW1

D

C

An Isolated Buck-Boost

The flyback converter is derived from the buck-boost cell

The addition of a transformer brings:

V in -k.V in

+

Up or down scale V in

Isolation Polarity change

More than 1 output


6/165


..

in

on p

V

S L=

The current increases in the inductor in relationship to V in and L pThe output capacitor supplies the load on its own

in peak valley on

p

V I I t

L= +

CCM

in peak on

p

V I t

L=

DCM

PIV in out V N V = +Reverse voltage on the diode

Simplified, no leakage

The Turn-on EventThe power switch turns on: current ramps up in L p, D is blocked

inV

SW

p I

sec 0 I =

in NV out V

p L

s p N N N =0 V

ont

ont

peak I

peak I

valley I C I

inV

( ) p I t


7/165


..

,out

DS off in in r

V V V V V

N = + = +

Reflectedvoltage

( )1 1out on sw

in off sw

V Nt NDT NDV t D T D

= = =

V Lp(t)

t on = DT sw t off = (1-D )T sw

V in

V out /N

Apply volt-second balance

dc transfer function in CCM

Applying Volt-Second Balance, CCMThe power switch turns off: D conducts, V out "flies" back

inV

p L

out V

out V N

p I N C I


8/165


..

V Lp(t)

t on = DT sw t off = (1-D)T sw

V out /N

V in

DT

2out load

in p sw

V R D

V L F =

N no longer plays a role Rload , L p and F sw do

, DS off inV V =

Applying Volt-Second Balance, DCM

Apply volt-second balance

In DCM, when L p is fully depleted D opens: V out reflection is lost

dc transfer function in DCM

inV

p L0V

sec 0 I = C I


9/165


24 X1PSW1RON = 10mROFF = 1Meg

3 Cout470uIC = 10

V2 4 0 PULSE 0 5 0 10n 10n 3u 10u

Rload2

5

Vin100

V2

Vout6 1

X2XFMRRATIO = -0.1

Ls

VdsIIn

.

.Lp2.2m

D1

D

S

Flyback, Typical WaveformsBelow is a simple flyback converter, without parasitics

It will run open loop for simplicity, V out 8 VNo parasitics


10/165


Flyback, Typical Waveforms, CCM

0

400m

800m

1.20

1.60

i i n i n a m p e r e s

p l o t

1

1

750m

850m

950m

1.05

1.15

i ( l p )

i n a m p e r e s

p l o t

2

2

10.070.0

130

190

250

v d s i n v o

l t s

p l o t

33

8.81

8.83

8.85

8.87

8.89

v o u t

i n v o

l t s

p l o t

44

3.002m 3.006m 3.010m 3.014m 3.018mtime in seconds

0

4.00

8.00

12.016.0

i d ( d 1 ) i n a m p e r e s

p l o t

55

I in(t)

I Lp(t)

V DS (t)

V out (t)

L I

I peak

V inout V N out inV N V +

Output cap.refueling

Output capacitorsupplies the load

Diode blocks

I d (t) I peak / N

0

400m

800m

1.20

1.60


p l o t

1

1

750m

850m

950m

1.05

1.15

i ( l p )

i n a m p e r e s

p l o t

2

2

10.070.0

130

190

250

v d s i n v o

l t s

p l o t

33

8.81

8.83

8.85

8.87

8.89

v o u t

i n v o

l t s

p l o t

44


0

4.00

8.00

12.016.0


p l o t

55

I in(t)

I Lp(t)

V DS (t)

V out (t)

L I

I peak




Diode blocks

I d (t) I peak / N

CCM flyback no parasitics

Input currentI valley

E valley

E peak

Inductor current

Drain voltage

Output voltage

Diode current


11/165


0

100m

200m

300m

400m


P l o t 1

1

0

100m

200m

300m

400m

i ( l p )

i n a m p e r e s

P l o t 2

2

0

100

200

300

400

v d s i n v o

l t s

P l o t 3

3

12.632

12.636

12.640

12.644

12.648

v o u t

i n v o

l t s

P l o t 4

4


-1.00

0

1.00

2.00

3.00


P l o t 5

5

I in(t)

I Lp(t)

V DS (t)

V out (t)

L I

I peak


DCM (core reset)



Diode blocks

I d (t) I peak / N

0

100m

200m

300m

400m


P l o t 1

1

0

100m

200m

300m

400m

i ( l p )

i n a m p e r e s

P l o t 2

2

0

100

200

300

400

v d s i n v o

l t s

P l o t 3

3

12.632

12.636

12.640

12.644

12.648

v o u t

i n v o

l t s

P l o t 4

4


-1.00

0

1.00

2.00

3.00


P l o t 5

5

I in(t)

I Lp(t)

V DS (t)

V out (t)

L I

I peak


DCM (core reset)



Diode blocks

I d (t) I peak / N

E valley = 0 E peak

Flyback, Typical Waveforms, DCM

Input current

Inductor current

Drain voltage

Output voltage

Diode current

DCM flyback no parasitics


12/165


2,

12 p L valley p valley

E L I =

2, 12 p L peak p peak

E L I =

Initially stored energy

Stored energy at t on

( )2 2 2 2, 1 1 12 2 2 p L trans p peak p valley p peak valley E L I L I L I I = = Transmitted energy at T sw

( )2 212

out peak valley p swP I I L F = CCM

DCM, I valley = 0

Energy Transfer in CCM and DCM

Eta, the efficiency

The primary inductance, L p, stores and releases energy

Power (W) is energy (J) averaged over time (s):

212out peak p sw

P I L F =


13/165


Course Agenda


The Parasitic ElementsHow These Parasitics Affect your Design?






14/165


84

X1PSW1RON = 10mROFF = 1Meg

3

7

Cout470uIC = 10

V2 4 0 PULSE 0 5 0 10n 10n 3u 10u

Rload2

5

Vin100

V2

Vout6

2

1

X2XFMRRATIO = -0.1

Ls

Vds

9

IIn.

.Lp{Lp}

Lleak{Leak}

parameters

Lp=2.2mk=0.02Leak=Lp*k

Clump100p

D1

1n5819

Resr150m

rLf250m

Dbody

Considering Parasitic ElementsThe transformer and the MOSFET include parasitics

With parasitics


15/165


CCM mode with parasitics

Considering Parasitic Elements, CCM

-800m

-400m

0

400m

800m


p l o t

11

550m

650m

750m

850m

950m

i ( l p )

i n a m p e r e s

p l o t

2

2

-30.0170

370

570

770

v d s i n v o

l t s

p l o t

3

3

7.20

7.80

8.40

9.00

9.60

v o u t

i n v o

l t s

p l o t

4

4


0

4.00

8.00

12.016.0


p l o t

5

5

I in(t)

I Lp(t)

V DS (t)

V out (t)

I peak

V in( )out in leak V Vf N V V + + +

I d (t)

Leakageinductancecontribution

-800m

-400m

0

400m

800m


p l o t

11

550m

650m

750m

850m

950m

i ( l p )

i n a m p e r e s

p l o t

2

2

-30.0170

370

570

770

v d s i n v o

l t s

p l o t

3

3

7.20

7.80

8.40

9.00

9.60

v o u t

i n v o

l t s

p l o t

4

4


0

4.00

8.00

12.016.0


p l o t

5

5

I in(t)

I Lp(t)

V DS (t)

V out (t)

I peak


I d (t)


Input current

Inductor current

Drain voltage

Output voltage

Diode current


16/165


Considering Parasitic Elements, DCM

-100m

0

100m

200m

300m


p l o t

1

1

-100m

0

100m

200m

300m

i ( l p )

i n a m p e r e s

p l o t

2

2

-30.070.0

170

270

370

v d s i n v o

l t s

p l o t

3

3

12.2

12.4

12.6

12.8

13.0

v o u t

i n v o

l t s

p l o t

4

4


0

1.00

2.00

3.004.00


p l o t

5

5

I in(t)

I Lp(t)

V DS (t)

V out (t)

I peak


I d (t)


DCM (core reset)

Diode blocks here

-100m

0

100m

200m

300m


p l o t

1

1

-100m

0

100m

200m

300m

i ( l p )

i n a m p e r e s

p l o t

2

2

-30.070.0

170

270

370

v d s i n v o

l t s

p l o t

3

3

12.2

12.4

12.6

12.8

13.0

v o u t

i n v o

l t s

p l o t

4

4


0

1.00

2.00

3.004.00


p l o t

5

5

I in(t)

I Lp(t)

V DS (t)

V out (t)

I peak


I d (t)


DCM (core reset)

Diode blocks here

Input current

Inductor current

Drain voltage

Output voltage

Diode current

DCM mode with parasitics


17/165


Who Are the Stray Elements?The study of the drain node reveals a LC network

..

..

L p

l leak

C oss

L p primary inductorlleak leakage inductorC oss output capacitance

Simplified view

V bulk V bulk


18/165


212 OSS DS

W C V =

The MOSFET C OSS is a Non-Linear DeviceThe capacitor value changes with its bias voltage

( ) 0

0

1

DOSS DS

DS

C C V

V V

=

+

C D0 is the cap. for V DS = V 0

Since bias affects the capacitor value:


19/165


As the Voltage Decreases, C OSS Value ChangesThe brutal discharge generates switching losses

OSS C

OSFET

D

S

C I ( ) ( )0t

C C W I t V t dt =

C V

( ) ( )C

C

dV t

I t C dt =

( )( ) ( )

0 0

DS t V DS DS DS DS DS

dV t W C V t dt C V V dV

dt = =

( ) 0 0 DOSS DS DS

C V C V

V 3 2 0 0

23 DS D

W V C V =

The lost energy is smaller than with the non-linear variation!

At turn-off


20/165


Using the Raw C OSS is an OverkillRe-compute the capacitor from the MOSFET data-sheet

2 21 0.5 400 100 2 J2 OSS DS

W C V p= = =

The classical equation gives:

or 200 mW @ 100 kHz

The updated equation gives:

3 2 3 20 0

2 2100 400 10 843 nJ

3 3 DS DW V C V p= = =

or 84 mW @ 100 kHz = 58% reduction

0 DC 0 DV

Overkill


21/165


The Leakage Inductance

The coupling in a transformer is not perfect

Closed path

in the air

Closed pathin the airLeakage flux

Leakage flux

Some induction lines couple in the air: leakage flux


22/165


An Equivalent Transformer Model

For a two-winding transformer, the model is simple:Two leakage inductorsOne magnetizing inductor

lleak 1 l leak 2

L p

1:N

primary secondary

This is commonly known as the "PI" model


23/165


The Transformer Scales the Primary Current

. .

In a perfect transformer, we have:

p I sec

p I I N

=

Primary Secondary

The turns ratio is usually normalized to the primary

1: N

: p s N N : p s

p p

N N

N 1: N

Divide by N p

100

25 p

s

N

N

=

=1: 0.25

. .1 250m


24/165


The Leakage Term also Stores EnergyAt turn-on, the primary current flows in both lleak and L p

( ) p I t

p L

leak l

inon

p leak

V S

L l

=

+ N = 1

During the on-time, both L p and lleak store energy

212leak leak p

W l I =

( ) p I t

inV


25/165


Where does the Current Flow?At turn-off, the energy stored in L p is dumped in the output cap.

The leakage inductor current fills up the drain lump capacitor

p L

( )leak l

I t

( ) ( ) p leak L l

I t I t

( ) p L I t ( )out V t

( )leak l

I t

leak l

lumpC

inV


26/165


Watch out for the Maximum Excursion!

The voltage on the drain increases dangerously!

As the diode conducts, V out reflects over L p

leak l

lumpC

out f V V

N

+

( )out f leak DS ,max in peak lump

V V lV V I N C

+= + +

Characteristicimpedance

inV

Flybackvoltage

( )leak l

I t

( )leak l

I t 0

200400600800

( ) DS V t


27/165


We Need to Clamp that VoltageMOSFETs have a voltage limit they can fly up to: BV DSS A clamping circuit has been installed to respect amargin

out f V V N

+clampV clampV

p L

D Dleak l

in clampV V +

600V DSS BV =


28/165


Resetting the Leakage InductanceBecause of the clamp action, a voltage appears across lleak

clampV p L

leak l

( )leak l

I t

( ) ( ) p leak L l

I t I t

( ) p L

I t

( )leak l

I t

( )out V t

( )leak clamp out f lleak

V V V S

l

+=

This voltage forces a reset of the leakage inductance

( )leak l clamp out f

V V V V = +

leak lV

reset


29/165


Do we Need a Quick Reset?When current flows in lleak , it is diverted from the secondary

( )leak l

I t

( ) ( ) p leak L l

I t I t

( ) p L

I t

( )leak l

I t

( )leak l

I t

The leakage current delays the occurrence of the sec. current

At the switch opening:

( ) ( ) p leak L l

I t I t =

( )sec 0 I t =

p L

leak l


30/165


l leak Delays the Secondary CurrentThe leakage inductor reduces the peak secondary

current( ) I t

t

ont t off t t

peak I

valley I

, p leak L l

I I

leak l I

sec I

Primary andsecondarycurrents.

( )sec I t

( ) p I t

The "stolen" energy is dissipated in heat in the clampingnetwork

Less energy is transmitted to the secondary side efficiencysuffers

p I


31/165


A Reduced Secondary-Side CurrentWe can calculate the leakage inductor reset time

t

sec sec

11

1

peak peak leak

clamp p

out f

I I l I S t

NV N N LV V

= =

+

( )leak peak leak peak

l clamp out f

I l I t

S V V V = =

+

( )leak peak leak peak

l clamp out f

I Nl I t

S NV V V = =

+

N 1

( ) I t

t

peak I

sec I

( ) p I t

t

( )leak

clamp out f

lleak

V V V S

l

+=

( )leak l I t

( )( )

0.25 4.8 3)205ns

0.25 150 19 1

ut

= =

+

0.25

4.8 H

150 V

V 19 V

I 3 A

leak

clamp

out

peak

N

l

V

=

=

=

=

=


32/165


-60.0m

20.0m

100m

180m

260m

i l p i n a m p e r e s

p l o t

1

2

-60.0m

20.0m

100m

180m

260m

i l l e a

k i n a m p e r e s

P l o t 3

3

100m

700m

1.30

1.90

2.50

i d 1 i n a m p e r e s

p l o t

2

4


-40.0

40.0

120

200

280

v d s

i n v o

l t s

P l o t 4

1

I Lp(t)

I d (t)

V DS (t)

I leak (t)

I peak = 236 mA I peak = 210 mA

0

I d,peak =2.1 A

t rr

t = 480 ns-60.0m

20.0m

100m

180m

260m

i l p i n a m p e r e s

p l o t

1

2

-60.0m

20.0m

100m

180m

260m

i l l e a

k i n a m p e r e s

P l o t 3

3

100m

700m

1.30

1.90

2.50

i d 1 i n a m p e r e s

p l o t

2

4


-40.0

40.0

120

200

280

v d s

i n v o

l t s

P l o t 4

1

I Lp(t)

I d (t)

V DS (t)

I leak (t)

I peak = 236 mA I peak = 210 mA

0

I d,peak =2.1 A

t rr

t = 480 ns

Typical Example Simulation Results

Primary current

Leakage inductorcurrent

Sec. current

Drain voltage

11% decrease!


33/165


. .

A Ringing Appears as the Diode Blocks

( ) 0leak l

I t =

in clamp r V V V + +

r V

leak l

As the clamp diode blocks, the drain returns toV in

out f in

V V V N

++

An oscillationtakes place

1

2 leak lump f

l C =

out V

lumpC

lleak is resett

1: N

in clamp r V V V + +

0 V

D

D clamp

D clamp blocks


34/165


V DS (t )

V os = 14 V

The clamp diode forward transit time delays the clamping action

The Clamp Circuit Overshoots

This spike can be lethal to the power MOSFET include margin!


35/165


The Primary Inductor also Rings in DCMWhen L p is reset, the capacitor voltage returns

to V in

. .0 V

leak l

lumpC in r V V +

An oscillationtakes place

( )1

2 p leak lump f

L l C =

+

L p is reset

V in

V in

1: N

D D blocks

D clamp


36/165


Course Agenda


The Parasitic Elements

How These Parasitics Affect your Design?






37/165


The leakage inductor induces a large spike at turn-offThis voltage excursion must be kept under control

How these Parasitics Affect your Design?

BV DSS

clampV 15%

V

t

The lump capacitor on the drain brings switching lossesIs there a way to switch on again when discharged?

Asynchronous switchingFixed frequency

Synchronous switchingVariable frequency

DS inV V >

DS inV V


38/165


600 0.85 510 V DSS D BV k = =

115 Vclamp DSS D os inV BV k V V = =

A vertical MOSFET features a buried parasitic NPN transistorThe collector-base junction of this transistor forms the body-diodeThis diode can accept to avalanche in certain conditionsDo NOT use this diode as a Transient Voltage Suppressor!

Adopt a safety coefficient k D when chosing the maximum V DS (t )15% derating is usually selected

k D = 0.85

Take V os around 15 20 V RCD clampdesign entry

Protecting the Power MOSFET

gate

drain

source


39/165


BV DSS = 600 V

V DS (t )

V r V in

V clamp

V os

Safety margin

100 V / div

Inclusion of a Safety MarginThe voltage on the drain swings up to V clamp

Capture this waveform in worst-case conditions

nominal

max

max

out

out

in

V

I

V

=

=

=

Test at start-up

and in short-circuit


40/165


The reflected voltage affects the power dissipation in the clamp

Do not Reflect too Much Voltage

( )2

,

12 1clamp

cV avg sw leak peak

c

k P F L I

k =

clamp

cr

V k

V =

1 1.5 2 2.5 30

10

20

30

40

50

60

ck

( )WclampP

If V clamp is too close to V r , dissipation occurs k c = 1.3 to 2


41/165


( )c out f clamp

k V V N

V

+

The turns ratio affects the reflected voltage

PIV in out V N V = +

Compute the Transformer Turns Ratio

But also the Peak Inverse Voltage of the secondary diode

Choose a 100%derating factor

PIV 100 V=

BV 200V=

PIV

ringing

If

Then

Always check the margins are not violated in any operating modes

V f

( )d V t

( )out f clamp c

V V V k

N

+


42/165


( )

2

2 out f

clamp clamp

clpsw leak peak

V V V V

N R

F l I

+ = clampclp

clp sw

V C

R F V =

Select the Clamp Passive ElementsThe clamp resistor depends on the maximum peak current

600 V

550 V

600 V

550 V

clpC clp R

D

Watch for the peak current overshoot in fault!

,max ,max,max

sense in peak prop

sense p

V V I t

R L= +

Worst-case value


43/165


It can also forward-bias the MOSFET body diodeDamp it!

V DS (t )

The Leakage Inductor RingsThis ringing can be of high frequency and is radiated-EMI rich

..

damp R

D

clpC

clp R

Watch for

added cap.


44/165


0 1leak damp

lQ

R

= = 0@leak l damp Z f R=

V

Without R damp

With R dampSimilar overshoot

V DS (t) V DS (t)a b

V

Without R damp

With R dampSimilar overshoot

V DS (t) V DS (t)a b

Fighting Parasitic Ringing part IThe installed resistor reduces the ringing on the drain


45/165


Fighting Parasitic Ringing part II

.

.

If the series resistor is not enough, install a damper

1. Measure the ringing: f 0

2. Evaluate leakage impedance at f 0

3. Make4. Try

5. Tweak for power dissipation0

12damp

C f R

=leak damp l R Z =

02leak l leak Z l f =

Ray Ridley Snubber design procedure

damp R

dampC

Eff B h b h Cl i A i


46/165



40.0

160

280

400520

v d r a

i n i n v o

l t s

p l o t

1 1


10.0

130

250

370490

v d r a

i n i n v o

l t s

P l o t 5

2


10.0

130

250

370490

v d r a

i n # a i n v o

l t s

P l o t 4

3


10.0

130

250

370490

v d r a

i n # a i n v o

l t s

P l o t 3

3

No damper zoom

V peak = 510 V

Can forward biasthe body diode No damper

V DS (t)

V DS (t)

V DS (t)

V DS (t)

Rdamp = 290 C damp = 220 pF


V peak = 452 V

V peak = 494 V

a

b

c

F leak = 2.08 MHz


40.0

160

280

400520

v d r a

i n i n v o

l t s

p l o t

1 1


10.0

130

250

370490

v d r a

i n i n v o

l t s

P l o t 5

2


10.0

130

250

370490

v d r a

i n # a i n v o

l t s

P l o t 4

3


10.0

130

250

370490

v d r a

i n # a i n v o

l t s

P l o t 3

3

No damper zoom

V peak = 510 V

Can forward biasthe body diode No damper

V DS (t)

V DS (t)

V DS (t)

V DS (t)



V peak = 452 V

V peak = 494 V

a

b

c

F leak = 2.08 MHz

Effects Brought by the Clamping Action

Wh Di d S l f h Cl ?


47/165


V DS

(t)

V DS (t)

No ringing!

Recovery losses

V = 37 V

I d (t)

V DS

(t)

V DS (t)

No ringing!

Recovery losses

V = 37 V

I d (t)

Can a simple 1N4007 be used in a RCD clamping network?The answer is yes for low power applications (below 20 W)The long recovery time naturally damps the leakage inductor

What Diode to Select for the Clamp?A fast diode is a must: MUR160 is good fit

B S th Cl L l d t R


48/165


0 1 2 340

60

80

100

120

140

V clamp (V)

I peak (A)0 1 2 3

40

60

80

100

120

140

V clamp (V)

I peak (A)

Watch-out for clamp voltage variations, at start-up or in short-circuitThe main problem comes from the propagation delay!

Be Sure the Clamp Level does not Runaway

Ch k th Cl V lt g V i ti


49/165


150u 450u 750u 1.05m 1.35mtime in seconds

-200

0

200

400

600

v d r a

i n i n v o

l t s

p l o t

110


-100

0

100

200

300

v c l a m p

i n v o

l t s

P l o t 2 12


-300m

100m

500m

900m1.30

v s e n s e

i n v o

l t s

P l o t 3

15


-2.00

2.00

6.00

10.0

14.0

v o u t

i n v o

l t s

P l o t 4

16

V DS (t)

V clamp (t)

V sense (t)

V out (t)

overshoot

Max V sense


-200

0

200

400

600

v d r a

i n i n v o

l t s

p l o t

110


-100

0

100

200

300

v c l a m p

i n v o

l t s

P l o t 2 12


-300m

100m

500m

900m1.30

v s e n s e

i n v o

l t s

P l o t 3

15


-2.00

2.00

6.00

10.0

14.0

v o u t

i n v o

l t s

P l o t 4

16

V DS (t)

V clamp (t)

V sense (t)

V out (t)

overshoot

Max V sense

No design margin!

Check the Clamp Voltage Variations

Drainvoltage

Clampvoltage

Sensevoltage

OutputvoltageWorst case

A Zener or TVS to Hard Clamp the Voltage


50/165


Vout

Dclp

Vbulk

TVS

V DS (t)

I d (t)

200t = ns

V DS (t)

I d (t)

200t = ns

( )21

2 z

TVS sw leak peak out f

z

V P F l I

V V

V N

=+

The TVS improves the efficiency in standby but degrades EMIIt costs around 5 cents

A Zener or TVS to Hard Clamp the VoltageTVS do not suffer from voltage runaways in fault conditions

Course Agenda


51/165


Course Agenda








What Control Scheme?


52/165


What Control Scheme?Two control scheme coexist, current-mode andvoltage-mode

Voltage-mode?

Current-mode?

Operatingwaveformsare identical

Voltage-mode?

Current-mode?

Ac -transferfunctionsdiffer

Voltage Mode Control


53/165


S

R

Q

Q

+

-

..

+

-

Voltage-Mode ControlVoltage mode uses a ramp to generate the duty-ratioThe error voltage directly adjusts the duty-ratio

sense R

maxV

out V

FB

dd v

bulk V

( ) D t

( )err V t

( )sawV t ( ) D t

err V

Voltage-Mode Control


54/165


Voltage-Mode ControlPROsPROs

Does not need the inductor current informationCan go to very small duty-ratioCCM operation without sub-harmonic instabilitiesNo need for slope compensation, current limit

unaffected

CONsCONs

No inherent input line feedforward (weak audiosusceptibility)

Cannot use small bulk capacitor, bad ripple rejection2 nd -order system in CCM: mode transition can be a

problem

Limited integrated circuit offer

Peak-Current-Mode Control


55/165



S

R

Q

Q

+

-

.

.

sense RmaxV

out V

FB

dd v

err V

bulk V

Current mode uses the inductor current information asa rampThe error voltage adjusts the inductor peak currentThe duty-ratio is indirectly controlled

( ) D t

( ) L I t ( )err V t

( ) L I t



56/165


Peak Current Mode ControlPROsPROs

Inherent pulse-by-pulse current limitationNatural input line rejectionMode transition DCM to CCM is easyConverter remains a 1 st -order system at low frequencyWidest offer on the market: a really popular technique!

CONsCONs

Leading Edge Blanking limits the minimum duty-ratioRequires slope compensation against sub-harmonic

oscillationsAdditionnal ramp affects the available maximum peak

current

Current sense can sometimes be a problem (floatingsense)

A Dirty Inductor Current Signal


57/165


A Dirty Inductor Current Signal

The inductor current is sensed with a resistor, atransformer

This information is affected by parasitics: false trippingpossible!

3.122m 3.126m 3.131m 3.135m 3.139m

-100m

100m

300m

500m

700m

1

( )senseV t

Can potentiallyfalse trip thecontroller

The LEB Cleanses the Signal


58/165


The LEB Cleanses the Signal

A circuit blinds the controller at turn-on for a small time(250 ns)

It conveys the signal afterwards: Leading Edge Blanking

2

2

( )senseV t

Cleanedges

sense R

CS

DRV

S1

S 2

PWMreset

bulk V

DRV

LEBt

. .

It Limits the Minimum Duty-Ratio


59/165


It Limits the Minimum Duty Ratio

During the LEB duration, the controller is completelyblind!

In output winding short-circuits, failures are likely tooccur

1.2

2.6

4

591u 594u 597u 600u 603u

-3.001.00

5.00

9.00

13.0

0.8 sense R

LEBt

+ 80%

LE B delt t +( ) DRV V t

( )senseV t

( )CS V t

t LEB + t del sets the minimum duty-ratio: cannot go lower, t on ,min

If the Primary Inductor is too Low


60/165


y

In short-circuit situations, you reflect the diode forwarddrop

.

.

bulk V

1 N

f V

f V

N

( ) p L

I t

t sense R

inon

p

f off

p

V S L

V S

NL

=

=

onS

off S

swT

,minont

Almostno decrease

If you hit the minimum on-time, you cannot limit thecurrent!

The Primary Current Runs out of Control


61/165


1.00

3.00

5.00

7.00

9.00

i p r i m

i n a m p e r e s

P l o t 1

7

35.0u 70.0u 105u 140u 175utime in seconds

0

400m

800m

1.20

1.60

v s e n s e

i n v o

l t s

P l o t 2

8

I Lp(t)

V sense (t)

Demagnetizationtoo weak

1 V

Maximum theoretical peak value, 5 A

The current climbs-upto 9 A!!

1.00

3.00

5.00

7.00

9.00

i p r i m

i n a m p e r e s

P l o t 1

7

35.0u 70.0u 105u 140u 175utime in seconds

0

400m

800m

1.20

1.60

v s e n s e

i n v o

l t s

P l o t 2

8

I Lp(t)

V sense (t)

Demagnetizationtoo weak

1 V

Maximum theoretical peak value, 5 A

The current climbs-upto 9 A!!

Chris Bassofirst design

y

The current current climbs cycle by cycle until smokeappears!

Minimum t on

ok

Sub-Harmonic Oscillations


62/165


Ac analysis shows a first-order system at f c


63/165


I L

t dT sw dT sw

T sw

I L(0)

I L(T sw)

S 1 S 2

t

ab

I L(0) I L(T sw) err

i

V

R

I L(T sw) I L(0)

I peak

I L

t dT sw dT sw

T sw

I L(0)

I L(T sw)

S 1 S 2

t

ab


i

V

R

I L(T sw) I L(0)

I L

t dT sw dT sw

T sw

I L(0)

I L(T sw)

S 1 S 2

t

ab


i

V

R

I L(T sw) I L(0)

I peak

( ) (0)'

n

L sw L

d I nT I

d

=

1 peak I a S t = +

2 peak b I S t =

1 2

peak peak I a I b

S S

=

Solvingt

1 2

( )(0) L sw L I T I S S

=

2

1 'S d S d

=

y p y

The condition for instability is: CCM operation + duty-ratio > 50%

Instability Depends on Duty-Ratio


64/165


clock

I peak

I L

Perturbation has gone

I L(0)

I L(0)

t

clock

I peak

I L

Perturbation has gone

I L(0)

I L(0)

t

I L(0)

clock

I peak

Duty clamp

I L

I L(0)

t

I L(0)

clock

I peak

Duty clamp

I L

I L(0)

t

clock

I peak

Duty clamp

I L

I L(0)

t

Duty-ratio < 50%

Duty-ratio > 50%

Asymptotically stable

Asymptotically unstable

( ) (0)'

n

L sw Ld I nT I d

=

With a duty-ratio below 50%, perturbation naturally dies out

The Cure is in the Ramp


65/165


I L

t dT sw dT sw

T sw

I L(0)

I L(T sw)

S 1S 2

t

I L(0)

S acb

I L(T sw)

err

i

V R

I L

t dT sw dT sw

T sw

I L(0)

I L(T sw)

S 1S 2

t

I L(0)

S acb

I L(T sw)

err

i

V R

( )2

2

1( ) (0) (0)

'

n

a

n

L sw L La

S S

I nT I I aS d

d S

= = +

Must staybelow 1

2

2

11

0

a

a

S

S S S

Up tod = 100%

Injecting a ramp on the feedback signal, damping is obtained

A Model to Simulate a Flyback Converter


66/165


A SPICE model can predict subharmonic instabilities

1

D1Ambr20200ctp

23

4

Lp{Lp}

5DC

vout6

vout

X2xXFMRRATIO = -N

Vin100AC = 0

8

R1014.4m

C56600u

v c a

c

P W M s w

i t c h C M

p

d u t y - c y c

l e

X9PWMCML = LpFs = FswRi = RiSe = Se

Rload4

parameters

Vout=19Soff=(Vout/(N*Lp))*Ri

N=250mFsw=65kLp=350uRi=250mA=0.5Se=A*Soff

10

R166k

R210k

9

12

X3AMPSIMP

V22.5

13

LoL1kH

15

CoL1kF

AC = 1Vstim

err

B1VoltageV(err)/3 > 1 ?1 : V(err)/3

19.7V 19.0V

0V

441mV

-79.0V100V

19.0V

774mV

2.50V

2.50V

2.32V2.32V

2.32V

0V

Simulation Results of the CCM Flyback


67/165


As ramp is injected, the double-pole Q is dampedInjecting more ramp turns the converter into voltage-mode

-24.0

-12.0

0

12.0

24.0

1 10 100 1k 10k 100k

-180

-90.0

0

90.0

180

No ramp

( ) H s

( ) H s

250%aS S =

No ramp

250%aS S =

Modern Circuits Include Slope Compensation


68/165


A simple resistor in series with current sense resistor does the job

6

411 R

9C

bulk V

18 R2Q

25 R

20 k ramp R

300 nsdelay

PWM

Q

4.2FBV

PWMreset

2.5V

0.8 V1S

2S

..

6

411 R

9C

bulk V

18 R2Q

25 R

20 k ramp R

300 nsdelay

PWM

Q

4.2FBV

PWMreset

2.5V

0.8 V1S

2S

..

NCP1250

Adjust the resistor to setthe ramp to any level

Course Agenda


69/165









Modulation Strategies


70/165


on

off

off

on

LeadingLeading edgemodulation

TrailingTrailing edge

modulation

Clock

Clock

off

feedback

feedback

The most popular modulation strategy is trailing-edge

Leading-edge modulation often appears in post-regulatorsV GS (t )

V GS (t )

Fixed Frequency Operation


71/165


The vast majority of converters use fixed-frequency operationSwitching losses depend on frequency: high frequency, highlosses!

Capacitive losses are a brake to efficiency improvement

CCM operation induces high losses on the secondary diodePotential shoot-trough hampers synchronous rectificationThe Right Half-Plane Zero severely limits the available

bandwidth

( ) DS V t

( ) D I t ( )d I t

( ) DS V t

Hard blocking

Noise and losses!

The Right-Half-Plane Zero


72/165


In a CCM flyback, I out is delivered during the off-time:

T sw

D 0T sw

I d (t )

t

I L(t )

in

p

V L

I d 0

T sw

D 1T sw

I d (t )

t

I L(t )

d

I L1

I d 1

I L0

If D brutally increases, D' reduces and I out drops!What matters is the inductor current slew-rate

( ) Ld V t dt

in

p

V L

Processing the Output Power Demand


73/165


If I L(t ) can rapidly change, I out increases when D goes up

100u 300u 500u 700u 900u

d (t ) V out (t )

I L(t )

I out (t )

200 s

d = 58.3%

d = 59%

Failing to Increase the Current in Time


74/165


If I L(t ) is limited because of a big L p, I out drops when D increases

2

100u 300u 500u 700u 900u

d (t )

d = 59%

d = 58.3%

V out (t )

I L(t )

I out (t )

10 s

V out drops!

I out drops!

The RHPZ is a Positive Root


75/165


Small-signal equations can help us to formalize it

2

2

2

'load z

p

R D N DL

=

The negative signindicates a positive root!

( )( )

1 2

0 2

0 0

1 1

1

z zout

s s

v sG

d s s sQ

+

=

+ +

Voltagemode

Currentmode

Voltage mode or current mode, the RHPZ remains the same

( )

( ) ( )

1 2 3

0

1 1 1

z z zout

c

s s s

v sG

v s D s

+ + =

Simulating the RHPZ


76/165


To limit the effects of the RHPZ, limit the duty ratio slew-rateChoose a crossover frequency equal to 20-30% of RHPZ position

A simple RHPZ can be easily simulated:

12

E110k

R110k

3

C110n SUM2

K1

K2

4

X1SUM2K1 = 1K2 = 1

1

0

1

( ) ( ) ( ) ( ) 11out in in in

R sV s V s V s V s

sC

= =

V out (s)V in(s)

A Zero Producing a Phase Lag


77/165


With a RHPZ we have a boost in gain but a lag in phase!

0

( ) 1 s

G s

= +

LHPZ

RHPZ

0

( ) 1 s

G s

=

-40.0

-20.0

0

20.0

40.0

1 10 100 1k 10k 100k 1Megfrequency in hertz

-180

-90.0

0

90.0

180

|V out (s)|

arg V out (s)

-90

+1

Is There a RHPZ in DCM?


78/165


A RHPZ also exists in DCM boost, buck-boost converters

When D 1 increases, [ D 1, D 2] stays constant but D 3 shrinks

T sw

D 1T sw

I d (t )

t D 2T sw

D 3T sw

I L,peak (t )



79/165


T sw

D 1T sw

t D 2T sw

D 3T sw

1d

The triangle is simply shifted to the right by 1d

The refueling time of the capacitor is delayed and a drop occurs

I d (t )

I L,peak (t )



80/165


If D increases, the diode current is delayed by


180m

220m

260m

300m

340m

v d u t y

i n v o

l t s

-1.00

1.00

3.00

5.00

7.00

i ( b 2 )

, i ( b 2 ) # a i n a m p e r e s

P l o t 1

23

4


6.65

6.75

6.85

6.95

7.05

v o u t

i n v o

l t s

P l o t 3

1

2.02m 2.04m 2.06m 2.09m 2.11m

6.65

6.75

6.85

6.95

7.05

v o u t

i n v o

l t s

P l o t 2

1

D (t ) I d (t )

V out (t )

V out (t )

1d

1d

Averaged models can predict the DCM RHPZ

A Large-Signal Model is Available


81/165



Vout

16

R11150

C51m

R10

150m3

Vin10V

11

L175u

5

R150k

R3

10k

6

8

X2AMPSIMP

V22.5

Verr

1

LoL1kH

10

CoL1kF

V1xAC = 1

vout

vout

d a

c

P W M s w

i t c h V M

p

X3PWMVML = 75uFs = 100k

15.0V

15.0V

10.0V

10.0V

2.50V

278mV278mV

0V

( )( )

( )( )( )( )

1

1

2

2

1 1 1 1

z zout d

p p

s s s sv s H

d s s s s s

+ =

+ +

1

1 z

out ESR

sC R

=2 2

load z

Rs

M L=

1

2 1 1

1 p

out ESR

M s

M C R

=

2

21 1

2 p sw M

s F D

=

2 12 1

out d

V M H

D M

=

MerciVatch!

The Model Predicts it!


82/165



11.06 kHz z f =

2 141 kHz z f =

14.2 Hz p f =

28.75 dBd H =

247.1 kHz p f =

28.6 dB

-45

f p1

4.2 Hz 1 kHz 47 kHz 141 kHz 1 10 100 10k 100k 1Meg

-40.0

-20.0

0

20.0

40.0

-180

-90.0

0

90.0

180

8

7

f z2

f p2 f z1

Going to Variable Frequency


83/165


More converters are using variable-frequency operationThis is known as Quasi-Square Wave Resonant mode: QRValley switching ensures extremely low capacitive lossesDCM operation saves losses on the secondary diode

Easier synchronous rectificationThe Right Half-Plane Zero is pushed to high frequencies

( ) DS V t

( ) D I t ( )d I t

( ) DS V t

Smooth signals

Less noise

Low CV losses

What is the Principle of Operation?


84/165


The drain-source signal is made of peaks and valleysA valley presence means:The drain is at a minimum level, capacitors are naturally

discharged

The converter is operating in the discontinuous conductionmode

2.061m 2.064m 2.066m 2.069m 2.071m

0

120

240

360

480

( ) DS

V t DTt off t on

V in valley

V

A QR Circuit Does not Need a Clock


85/165


The system is a self-oscillating current-mode converter

S

R

Q

Q

+

-

..

+

-.

GFB Rsense

V out

C out

Resr

Rload

R pullup

N p:N s

V dd

V bulk

FB

L p

CTR

65 mV

Demagdetector

A Winding is Used to Detect Core ResetWhen the flux returns to zero, the aux. voltage drops


86/165


0

200

400

600

800

2.251m 2.255m 2.260m 2.264m 2.269m

-800m

-400m

0

400m

800m

-20

-10

0

10

20V A

V

( ) DS V t

( ) p L

I t

. .

.

( ) p L

I t

bulk V

aux

d V N

dt

=

0 =

Core isreset

delay

delay

( )auxV t

g pDiscontinuous Mode is always maintained

set

The Frequency Linearly Changes


87/165


As the peak current and the on-slope vary, T sw changes

swT

,on LLt ,max peak I

,max peak I

( ) p L

I t

Excellent behavior in short-circuit conditions!

,sw LLT ,on HLt ,sw HLT

1P

2P

lowlow rms currents in the MOSFET (weak stress)

off f pS V NL=

( )off out f pS V V NL= +

, ,on LL in LL pS V L=, ,on HL in HL pS V L=

t

t

The Excursion Can be Quite Large


88/165


In heavy load low-line conditions, F sw decreasesIn light-load and high-line operations, F sw can go very high

( )VinV ( )VinV

( )kHzswF

( )A peak I

100 200 300 40030

40

50

60

70

80

100 200 300 4002.4

2.6

2.8

3

3.2

3.4

EMI and switching losses are at stake as F sw goes upStandby power obviously suffers from this condition

In a Bounded System Discrete Jumps

A h l d li h h f h k


89/165


As the load gets lighter, the frequency goes to the skyModern controllers fold the frequency back with a VCOProblem, the only places to re-start are valleys: discrete jumps

Outputcurrent

New Controllers Lock in the Valleys

T h i h NCP1380 l k h ll


90/165


To prevent the noise, the NCP1380 locks the valleyThe current is allowed to move within a certain limitWhen it exceeds this limit, the controller selects a new valleyAs the load gets lighter, a VCO takes over and reduce F sw

0 20 40 602 10

4

4 104

6 104

8 104

1 105

F s w

( H z )

P out (W)

1st2nd3rd4th

1st2nd3rd4thVCOmode

VCOmodeP out decreasesP out increases

NCP1379/1380

Course Agenda


91/165




How These Parasitics Affect your Design?Current-Mode is the Most Popular Scheme

Fixed or Variable Frequency?

More Power than Needed



What is The Problem?

A t i d ig d t t id i 85 t 265 V


92/165


A converter is designed to operate on wide mains 85 to 265 Vrms

It can deliver a maximum power before protection trips

The maximum power delivered at high line is larger than that atlow line

85 V rms to 265 V rmsIncrease loaduntil protectiontrip.

What Does the Standard Say?

There is a test called Limited Power Source LPS


93/165


There is a test called Limited Power Source, LPS

The maximum power the converter can deliver must beclamped

If clamped, the manufacturer can use inferior fire proofingmaterials Output Voltage

( )Vout V

rmsV dcV

Output Current( )Aout I

Apparent Power( )VAS

20 20 8 5 out V 20 30out V < 20 30out V < 8 100

- 20 60out V < 150 out V 100

IEC950 safety standard

19-V adapter, I out, max = 5 A

Why the Power Runs Away in a Flyback?,max

,maxin

peak peak prop

V I I tL= +The inductor


94/165


,max

0.8 peak

sense

I

R

in

p

V S

L=

propt

delt

p I I t L

( ) p L

I t

( )outCS t

( )GS V t

PWM is reset

, peak LL I

Highline

Lowline

Depends ondrive capabilityand MOSFET

QG

, peak HL I The inductor

current slopeincreases at highline.

The controllertakes time to reactto an overcurrent

situation.The inductor

current keepsgrowing until theMOSFET turns off.

The overshoot islarger at higherslopes (High V in)

The Effect in a DCM Converter

A flyback converter operated in DCM obeys the formula:


95/165


A flyback converter operated in DCM obeys the formula:

2,max

12out p peak sw

P L I F =

Primaryinductor

Max. peakcurrent infault

Switchingfrequency

Converterefficiency

As L p and F sw are fixed, I peak, max changes with line input

,,max,

insense peak LL prop

sens

L

e p

LV V I t R L

= +

,max peak I

( ) p I L

,,max,

insense peak HL prop

sens

L

e p

H V V I t R L

= +

Low line High line

, ,

,max,,

peak in HL in LL

p sense peak HLin LL

prop sense

I V V L V I

V t R

=

+

A 13.5% overshoot translatesin a 28% power increase

( )21.13 1.28= ( is considered constant over the range)

t

L p = 250 H Vsense = 1 V t prop = 350 ns Vin,LL = 120 V in,HL = 370 V Rsense =

The Power Increases at High Line


96/165


Lp 250 H, V 1 V, t p p 350 ns, V , 120, V , 370 V, R 0.33 , F sw = 65 kHz

100 200 300 40045

50

55

60

65

( )VinV

( )Wout P

46 W

63W

In this example, the converter stays DCM over the whole inputrange.

17 Wout P =

= 85% = 89%

How to Compensate the Runaway?How do we compensate this excess of power?we reduce the maximum peak current at high


97/165


we reduce the maximum peak current at highline

this is called Over Power Protection OPP peak I peak I

inV inV

,max peak I , peak LL I , peak HL I

HL LL

How to calculate the compensated high-line current?Equate low-line power with high-line power and solve

for I peak

HL LL

2,max, ,max,1

2 pout eak H HL p w L s HLP L F I =

Solve for I peak

( ),max peak in I f V =

Reducing the Peak Current

The final inductor peak current must equal:


98/165


,ma

,max,

x,

2 out LL peak HL

p sw HL

I L F

P

=

The amplitude of the sensed voltage must reduce by:

You must subtract the prop. delay to obtain the controllersetpoint

,,max,

in HLsense peak HL prop

sense p

V V I t

R L=

The final inductor peak current must equal:

,,max,

in HLsense peak HL prop sense

p

V V V I t R

L

=

For What Final Result?

Thanks to the OPP, the power stays under control


99/165


100 200 300 40040

50

60

70

( )VinV

( )Wout P

46 W

63 W

42 W 46 W 4 Wout P =

Thanks to the OPP, the power stays under control

The CCM Case is a Different Picture

In DCM, the valley current is zero, the stored energy is:


100/165


In DCM, the valley current is zero, the stored energy is:2

,max

12 p peak

E L I =

The peak current runaway, alone, affects the transmitted powerIn CCM, the valley current changes the formula:

( )2 2

,max

12 p peak valley E L I I =

,max peak I

( ) p I L

t

valley I

The Converter Changes its Operating ModeIn fault mode, the converter operates in deep CCM at low lineAs the input voltage increases, the valley current decreases


101/165


p g , y

Maximum current in fault

Maximum current in fault

( ) p L

I t

t

t

,minin

p

V

L

,maxin

p

V

L

( )out f p

V V

NL

+

( )out f p

V V

NL

+

,max, p LL I

,max, p HL I

, , p valley LL I

, , p valley HL I

,on LLt

,on HLt 0

Low line

High line

LL E

HL E

HL LL E E >

Computing the Transmitted Power in CCMFirst, we write the t

onand t

off equations in

CCM


102/165


CCM( )

p L I t

t

,minin

p

V

L

( )out f p

V V NL

+

peak I

valley I

ont off t

swT

in peak valley on

p

V I I t L

= + ( )out f valley peak off p

V V I I t NL

+= sw on off T t t = +

(1) (2) (3)

Solving for the Valley CurrentBy combining the 3 equations, we have:

( ) ( )


103/165


( ) p peak valleyon

in

L I I t

V

=

( ) p peak valleyoff sw on sw

in

L I I t T t T

V

= =

Replace t off in(2):( )( ) f out valley p peak p sw in

valley peak p in

V V I L I L T V I I

L NV

+ +=

Solve for I valley :( )

( )sw f out

valley peak

p f out

in

in

T V V V I I

L V V N V

+=

+ +

,maxsense

peak propse se p

n

n

iV I t R L

V = +

Max faultcurrent

( )( )sw in f out

L

p f out in

T V V V I

L V V NV

+ =

+ +

LL or HL

L peak valley I I I =

Inductor ripplecurrent

Identifying the Operating ModeHaving the ripple on hand, we can confirm the

mode:I N I


104/165


Lon p

in

I t L

V

=

( ) L

off p

out f

N I t L

V V

=

+

0on off sw

valley

t t T I

+ =>

CCM

on off sw

sw off on

t t T DT T t t

+ 0.5 under damping

Asymptotically stable

Q = 0.5

phase margin depends on the needed response: fast, no overshootgood practice is to shoot for 60and make sure m always > 45

What Compensator Types do we Need?

There are basically 3 compensator types:type 1, 1 pole at the origin, no phase boost


119/165


type 2, 1 pole at the origin, 1 zero, 1 pole. Phase boost up to 90type 3, 1 pole at the origin, 1 zero pair, 1 pole pair. Boost up to 180

10 100 1k 10k 100k

( )G s

( )G s

270

b o o s t

1 2 5 10 20 50 100 200 500 1k

( ) 270G s =

( )G s

10 100 1k 10k 100k

( )G s

( )G s

270

b o o s t

Type 1 Type 2 Type 3Boost = 0 Boost up to 90 Boost up to 180

Fixed-Frequency Current-Mode

2 First, check the operating mode, CCM or DCM?


120/165


, 22load in

p crit out sw

in

R V L

V F N V N

=

+

L p > L p,crit ? Yes, CCM else DCM

Assume CCM, compute the duty-ratio:

out

out in

V D

V NV =

+

Compute M and : L

22 pout

Lin load sw

L N V

M NV R T = =

Evaluate the dc gain and poles/zeros positions:

( )0 2

11

2 1

load

sense FB

L

RG R G N D

M

=

+ +

Fixed-Frequency Current-ModeCompute the poles/zeros positions:

( )2

2

2

1

2load

z

D R f

DL N

=

1

12 z R

f C

=( )

1

3

1 1

2 L

p

D D f

R C + +

=


121/165


Check the quality coefficient at F sw /2in

n sense p

V S R

L= ( )1e c nS M S =

1 = no compensation( )( )

11 0.5 p c

Q M D

=

Apply to formula to plot the ac response:

( ) 1 2

0 2

2

1

1 11

11

z z

n p n p

s s

H s G s ssQ

+

+ ++

1 e

cn

S M S = + n swT

=

2 2 p DL N 1 2 t R ou ES R C 1 2p load out R C

3 rd order


2

Extract the magnitude and the argument definitions


122/165


( ) 2

1

22

1

10 0 2 2 22

1 11

20log1 1

z z

p n n p

f f f f

H f G f f f f f f Q

+ + =

+ +

( )1 2 1

1 1 1 12

1arg tan tan tan tan

1 z p n p z

n

f f f f H f

f f f Q f f f

=

Plot them with Mathcad for instance.

RHPZ


20Extract the information at the selected crossover frequency


123/165


10 100 10 3 104 10520

10

0

10

100

0

100

( ) H s

( ) H s

( ) 16.3dB3kHz H = ( )arg 3 kH 3z 2 H =

dB

Hz

Sub-harmonicoscillations

Damp poleswith S e

Low line, high power


The compensation strategy is the following:compensate the gain loss at fc so that: ( )3 kHz 16 3dBG = +


124/165


compensate the gain loss at f c so that:

evaluate the boost in phase at f c

to get phase 70 margin:

( )3 kHz 16.3dBG

( )Boost PM argH 90 3.15c f = = Boost = 0 select type 1 origin pole

Boost < 90 select type 2 origin pole, 1 pole, 1 zerok -factor can be used to place the pole and the zero

tan 45 12

boost k

= +

poles and zeros are coincident

1 1 3 3 kHz pk c f kf k = = = 13

3 kHz1

c zk

f k f

k = = =


Plot the compensator transfer function80 180

( )G s


125/165


10 100 10 3 10 4 10 520

0

20

40

60

260

240

220

200

( )G s

( )G s

dB

Hz

( )

1

2

110 2

0

1

20log

1k

zk

pk p

f

f G f G

f f f f

+ = +

1

1 1

1

180tan tan

zk pk

f f boost

f f =


Plot the loop gain transfer function G(s) H (s) and check the margi100 0

( )T


126/165


10 100 10 3 10 4 10 550

0

50

300

200

100

360

( )T s

( )T s

dB

Hz

f c = 3 kHz

70m =

Sweep ESR , C out , Rload and verify the resultsLow line, high power

Fixed-Frequency Current-ModeIn case the converter transitions to DCM, update the equation

20


127/165


10 100 10 3 104 10530

20

10

0

10

50

0

50( ) H s

( ) H s

( ) 1 2

1 2

0

1 1

1 1

z z

p p

s s

H s Gs s

+

=

+ +

Yes, analytical analysis is long and tedious.But, it teaches where the threats are and how to deal with!

Variable-Frequency Current-ModeObserving the waveforms helps us to derive an average mode

( )a I t ( )c I t


128/165


a c

p

Vc/(2*Ri)d1.Ic

Ia IcIt gives birth to a large-signal model

peak I

swdT swT

peak I

( ) 2sw peak c T

I I t =

( )2 i out out inc

in out

R P V NV V V V

+=

1c psw

i in out

V LT

R V V

= +

1

2 out ic in

P Rd

V V =Senseresistor

Variable-Frequency Current-ModeLinearization is needed to get a small-signal model

Implement this small-signal model in a flyback configuration a

v ( c , p ) .k


129/165


c

p

v c.k c

k c p

i c.k i c

v ( a , c ) .k a c

i c

X5XFMRRATIO = N

Resr

Cout

Rload

Vout

Lp

Vin

http://cbasso.pagesperso-orange.fr/Spice.htm


130/165

Use a SPICE Model to Stabilize the Converter

R10

2Vin340AC = 0

18 4

X2xXFMRRATIO = -250m

vout

16DCD1Ambr20200ctp

20

L12.2u

R120m vout

vint

R15

parameters

Vout=19

Ibridge=250uRlower=2.5/Ibridge

v c a

c

P W M s w

i t c h

C M

p

d u t y - c y c l e

19.0V

340V

-78.4V 19.6V

19.0V

116mV

0V

19.0V


131/165


1

C52m

15m13

Lp{Lp}

6

27

C1220u

85mRupper=(Vout-2.5)/Ibridge

Lp=600uFs=70kRsense=0.5Se=0

fc=1kpm=60Gfc=-21pfc=-88

G=10^(-Gfc/20)boost=pm-(pfc)-90pi=3.14159K=tan((boost/2+45)*pi/180)

Fzero=fc/kFpole=k*fc

Rpulldown=4.7kRLED=CTR*Rpulldown/GCzero=1/(2*pi*Fzero*Rupper)Cpole=1/(2*pi*Fpole*Rpulldown)

CTR=0.9Pole=15k

B1

Voltage

(V(err)-1.2)/3 > 1 ?1 : (V(err)-1.2)/3

15

14

CoL1kF

VstimAC = 1

8 5

LoL1kH

2V5gnd

UC384X19

X3OP384X1

R247k

R347k

err

Rload20

X9PWMCML = LpFs = FsRi = RsenseSe = Se

9

Vdd5

10

11

X10TL431_G

Rupper2{Rupper}

Rlower2{Rlower}

Rled{RLED}

Czero1{Czero}

vout

Cpole2

{Cpole}

X7OptocouplerCpole = 1/(6.28*pole*pullup)CTR = CTR

vint

R4{Rpulldown}

Verr

19.0V 19.0V

470mV

2.39V

0V

2.39V 2.39V

2.50V

2.61V

5.00V

17.6V

2.49V

18.8V Cannot bebeaten forsimplicityand speed!

Automate thecompensation!

Unveil the Transfer Function in a Second

20.0

40.0

90.0

180

dB

( ) H s


132/165


-40.0

-20.0

0

10 100 1k 10k 100k

-180

-90.0

0

90.0

180

-60.0

-30.0

0

30.0

60.0

dB

-180

-90.0

0 ( ) H s

( )T s

( )T s

Loop gain

Power stage gain

m

f c

Course Agenda


Th P i i El


133/165



How These Parasitics Affect your Design?Current-Mode is the Most Popular Scheme

Fixed or Variable Frequency?

More Power than NeededThe Frequency Response


How is regulation performed?Text books only describe op amps in compensators

out V


134/165


err V

The market reality is different: the TL431 rules!

TL431 optocoupler

err V

out V Im thelaw!

The TL431 Programmable ZenerThe TL431 is the most popular choice in nowadays designsIt associates an open-collector op amp and a reference voltageThe internal circuitry is self-supplied from the cathode currentWhen the R node exceeds 2 5 V it sinks current from its cathode


135/165


When the R node exceeds 2.5 V, it sinks current from its cathode

2.5V

K

A

R

TL431A

K

A

R

RAK

The TL431 is a shunt regulator

A Rabbit and a (French) SnailThe TL431 lends itself very well to optocoupler control

out V dd V

out V Fast lane Slow lane


136/165


lower R

1 R LED R

bias R

FBV

2C 1C

TL431

1 I LED I

1 I

min 2.5 VV =

1 V f V

1 Vbias

bias

I R

=

bias R

R LED must leave enough headroom over the TL431: upper limit!

LED R

dc representation

pullup R

Understanding the Fast Lane DrawbackThis LED resistor is a design limiting factor in low output voltages:

431,min,max min

i

CTRCTR

out f TL LED pullup

dd CE t bi ll

V V V R R

V V I R

+


137/165


, minCTRdd CE sat bias pullupV V I R

When the capacitor C 1 is a short-circuit, R LED fixes the fast lane gain( )out V s

LED R

pullup R

dd V

1 I

c I 0 V

in ac

( )FBV s

1( ) CTRFB pullupV s R I =

1

( )out LED

V s I

R=

( )CTR( )

pullupFB

out LED

RV sV s R=

This resistor plays a role in dc too!

lower R

1 R

The Static Gain LimitLet us assume the following design:

,max

5 1 2.520k 0.3

4.8 0.3 1 0.3 20 LED R

m k

+ 5 V1 V

out V

V

=

=


138/165


431,min

,

min

1 V

2.5 V4.8 V

300 mV

1 mA

CTR 0.320 k

f

TL

dd

CE sat

bias

pullup

V

V

V

V

I

R

=

=

=

=

=

==

,max 857 LED R

0

20CTR 0.3 7 or 17 dB

0.857 pullup

LED

RG

R> > >

In designs where R LED fixes the gain, G0 cannot be below 17 dB

You cannot amplify by less than 17 dB

Forbidden Compensation AreasYou must identify the areas where compensation is possible

18040.0

dB

Not ok


139/165


10 100 1k 10k 100k

-180

-90.0

0

90.0

-40.0

-20.0

0

20.0

( )arg H s

( ) H s

-17 dB

500

500 Hzc f >

okRequires

17 dBor more

Requiresless

than 17 dBof gain

Injecting Bias CurrentMake sure enough current always biases the TL431If not, open-loop gain suffers a 10-dB difference can be observed!

> 10 dB diff


140/165


I bias = 1.3 mA

I bias = 300 A

> 10-dB difference

Easysolution

I bias

Rbias

1 1 k 1bias

Rm

= =

Small-Signal AnalysisThe TL431 is an open-collector op amp with a reference voltageNeglecting the LED dynamic resistance, we have:

( )out V s ( ) ( ) ( )

1out opV s V s I s

=


141/165


LED R

lower R

1 R

1C 1 I

( )opV s

( )1 LED R

( ) ( ) ( )11

11

op out out upper upper

sC V s V s V s

R sR C = =

0

( )( )

11

1

11 upper

out LED upper

sR C I s

V s R sR C

+=

We know that: 1( ) CTRFB pullupV s R I =

( )( )1

1

CTR 1 pullup upper FBout LED upper

R sR C V sV s R sR C

+=

Creating a High-Frequency PoleIn the previous equation we have:

a static gain

a 0-dB origin pole frequency 1 =

0 = CTR pullup

LED

RG R


142/165


a 0 dB origin pole frequency

a zero

We are missing a pole for the type 2!

1

1

1 zupper R C

=

o

1 p

upper C R

pullup R

2C

( )FBV s

dd V

Add a cap. fromcollector to ground

( )( ) ( )

1

1 2

CTR 1

1 pullup upper FB

out LED upper pullup

R sR C V s

V s R sR C sR C

+ = +

Type 2 transfer function

Understanding the Optocoupler PoleThe optocoupler also features a parasitic capacitorit comes in parallel with C 2 and must be accounted for

V out (s)


143/165


FB c

e

R pullup

C

V dd

V FB (s)

optocoupler

C opto

2 || optoC C C =

Extracting the PoleThe optocoupler must be characterized to know where its pole is

2

Rpullup

5

Cdc10uFIc

Rled20k

( )O s


144/165


1

Rpullup20k

Vdd5

3

X1SFH615A-4

4

Vbias

Rbias

VFB

6

Vac

IF

Adjust V bias to have V FB at 2-3 V to be in linear region, then ac-sweepThe pole in this example is found at 4 kHz

-3 dB

( )O s

( )O s

1 1 2 nF2 6.28 20 4opto pullup pole

C R f k k

= =

Another designconstraint!

4 k

The TL431 in a Type 1 CompensatorTo make a type 1 (origin pole only) neutralize the zero and the pole

( )( ) ( )

1

1 2

CTR 1

1 pullup upper FB

out LED upper pullup

R sR C V s

V s R sR C sR C

+ =

+


145/165


1 2upper pullupsR C sR C = 1 2 pullupupper

RC C R

= o1

1

CTR

pupper LED

pullup

R RC

R

=substitute

o

2

CTR p

LEDC R =

2

CTR2 po LED

C f R

=

Once neutralized, you are left with an integrator

( ) 1

po

G ss

= ( ) o| | pcc

f G f

f

=o c p f c

f G f = 2CTR

2 c f c LEDC

G f R

=

A Type 1 Design ExampleWe want a 5-dB gain at 5 kHz to stabilize the 5-V converter

5 V

1 V

2 5 V

out

f

V

V

V

=

=

= Apply 15%


146/165


431,min

,

min

520

2.5 V

4.8 V300 mV

1 mA

CTR 0.3

20 k

10 1.77

5 kHz

TL

dd

CE sat

bias

pullup

fc

c

V

V V

I

R

G

f

==

=

=

=

= =

=

,max 857 LED R 728 LED R =

Apply 15%margin

2

CTR 0.37.4 nF

2 6.28 1.77 5 728c f c LED

C G f R k

= =

C opto = 2 nF

7.4 2 5.4 nFC n n= = 1 2 14.7 nF pullup

upper

RC C

R=

Simulation of the Type 1SPICE can simulate the design automate elements calcula

chris basso apec seminar 2011

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