class 05 device physics ii

8/22/2019 Class 05 Device Physics II

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Class 05: Device Physics II

Topics:

1. Introduction

2. NFET Model and Cross Section with Parasitics

3. NFET as a Capacitor

4. Capacitance vs. Voltage Curves

5. NFET as a Capacitor - Band Diagrams at V=0

6. NFET as a Capacitor - Accumulation V0

8. NFET as a Capacitor - Inversion V>>0

9. Band Diagrams, Charges, E-Field, and Potential

10. Band Diagrams at various biasing

11. Depletion Layer Width vs. Substrate Doping12. NFET Cross Section, Parasitics, and Biasing

13. Full CV Curve for reference


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Class 05: Device Physics II

Goal is to understand the parasitic regions and terms shown in the model and cross section

Last lecture covered the pn junctions of the source and drain

This lecture will cover the channel

Question - where is the biggest capacitor?

NFET Model and Cross Section with Parasitics (Martin p.101)


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Class 05: Device Physics IINFET as a Capacitor (Martin p.87, Singh p.418)

The channel region of an FET can be thought of as a series connection

of capacitors, the capacitance due to the thin oxide, and the capacitance due to

the semiconductor.

The thin oxide capacitance is fixed.

The semiconductor capacitance depends on the biasing


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Class 05: Device Physics IICapacitance vs. Voltage Curves (Singh p.419)

Much like IV curves define a transistor, CV curves define capacitors

Three regions of importance: (1) accumulation (2) depletion (3) inversion

Further foils will describe each of these regions

Once again, this is the channel region of a transistor and how it behaves when biased

To obtain a CV curve, one biases the top plate with a DC bias, and uses an AC signal

to determine the response of the carriers at the surface to the AC signal. So from

I=C dv/dt, one can back out the capacitance based on the measured current


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Class 05: Device Physics IINFET as a Capacitor - Band Diagrams at V=0 (Sze p.427)

This state is referred to as the flat-bandcondition

that is, no applied potential, the bands are flat in the ideal

case. So why is Vfb not at Vg=0 in the CV plot below?

Important terms to take from these diagrams are:

d insulator thickness

qB Energy of offset between Fermi and intrinsic levels

Important observations to make:

How can you tell from the band diagram which is n-type andwhich is p-type semiconductor?

Even the oxide has bands of allowed states, it is just that

the band gap is very large

This portion of CV curve referred to as the flat band capacitance


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Class 05: Device Physics IINFET as a Capacitor - Accumulation V


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Class 05: Device Physics IINFET as a Capacitor - Depletion V>0 (Sze p.428; Martin p.89)

This state is referred to as the depletioncondition because the

majority carrier are depleted from the surface


With a parallel plate analogy, this is where the thickness of the Cs plate

is increasing, due to the increase in the depletion regions.

Thus the capacitance is going down.

CG

= COX

Cdep

/ (COX

+ Cdep

) < COX


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Class 05: Device Physics IINFET as a Capacitor - Inversion V>>0 (Sze p.428; Martin p.89)

This state is referred to as the inversioncondition because the

minority carriers are brought to the surface of the channel. However,

minority carrier respond slower to the AC signal (minority

carrier lifetimes). Thus inversion in a CV curve is only obtained

with very slow varying signals.


With a parallel plate analogy, this is where the thickness of the Cs plate

is at its maximum.

During normal operation of a transistor, the carriers are suppliedby the source and drain, so there is no lack of carriers.

The definition of inversion is where surface potential > bulk potential

Vt is defined as the condition in which the surface is inverted, based on Cmi


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Class 05: Device Physics IIBand Diagrams, Charges, E-Field, and Potential (Sze p.434)

Spice model parameter

PHI is 2s


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Class 05: Device Physics IIBand Diagrams at various biasing (Sze p.430)


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Class 05: Device Physics IIDepletion Layer Width vs. Substrate Doping (Sze p.437)


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Class 05: Device Physics IINFET Cross Section, Parasitics, and Biasing (Martin p.101)

We have covered the source/drain to substrate junctions, and now

the gate/oxide/surface junction

Next, how they come together for the operation of an NFET


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Class 05: Device Physics IIFull CV Curve for reference (Sze p.438)

class 05 device physics ii

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