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IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 1/27 Class-AB Single-Stage OpAmp for Low-Power Switched-Capacitor Circuits S. Sutula 1 , M. Dei 1 , L. Terés 1,2 and F. Serra-Graells 1,2 [email protected] 1 Integrated Circuits and Systems (ICAS) Instituto de Microelectrónica de Barcelona, IMB-CNM(CSIC) 2 Dept. of Microelectronics and Electronic Systems (DEMISE) Universitat Autònoma de Barcelona (UAB) Lisbon, May 2015 IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)

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IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 1/27

Class-AB Single-Stage OpAmpfor Low-Power Switched-Capacitor

Circuits

S. Sutula1, M. Dei1, L. Terés1,2 and F. Serra-Graells1,[email protected]

1Integrated Circuits and Systems (ICAS)Instituto de Microelectrónica de Barcelona, IMB-CNM(CSIC)

2Dept. of Microelectronics and Electronic Systems (DEMISE)Universitat Autònoma de Barcelona (UAB)

Lisbon, May 2015

IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)

IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 2/27

1 Introduction

2 Class-AB Architecture

3 Process-Independent Circuits

4 Practical Design

5 Experimental Results

6 Conclusions

IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)

IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 3/27

1 Introduction

2 Class-AB Architecture

3 Process-Independent Circuits

4 Practical Design

5 Experimental Results

6 Conclusions

IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)

IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 4/27

Low-Power Switched-Capacitor Design

Low-Voltage Approach

I Bulk-driven OpAmpsI Internal supply multipliersI Inverter-based OpAmpsI Switched OpAmps

I Nominal-voltage downscaling

J Moderate power savings

Low-Current Approach

I Telescopic diff. pairs withLCMFB

I Dynamic biasing by RC biastees

I Hybrid-Class-A/ABI Adaptive biasing

I Higher power savingsJ Parameter-variation sensitivity

IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)

IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 5/27

1 Introduction

2 Class-AB Architecture

3 Process-Independent Circuits

4 Practical Design

5 Experimental Results

6 Conclusions

IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)

IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 6/27

Single-Stage Class-AB OpAmp

I Two complementary diff. pairsI Dynamic current mirrorsI Separate Class-AB controlI Partial positive feedbackI CMFB control through the

NMOS-pair tail

I Gain improvement by the outputcascode transistors

I No need for the Millercompensation capacitors

I High-peak Class-AB currentsonly in the output transistors

IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)

IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 7/27

Single-Stage Class-AB OpAmp

I Supposing all boxed devicesoperating in strong inversion:

D.=

ABA + B√

Ionp

D=

√Iinp

A+

√nβ2

Vcp

I Desired Class-AB behavior:

Ioutp ≡ 0 Vcp ≡ Vxp Ionp ≡ Iinp

Ioutp 6≡ 0 Vcp 6≡ Vxp

{Ionp � Iinp

Ionp � Iinp

IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)

IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 8/27

1 Introduction

2 Class-AB Architecture

3 Process-Independent Circuits

4 Practical Design

5 Experimental Results

6 Conclusions

IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)

IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 9/27

Type I

Iinp =B(

2√

IonnD −

√Ionp

D +√

IinpA

)(√Ionp

D −√

IinpA

)+C(√

2ItailD −

√Ionp

D −√

IonnD +

√Iinp

A +√

IinnA

)(√

IonpD −

√Ionn

D −√

IinpA +√

IinnA

)I Cross-coupled pair

for the Class-ABoperation

I Crossing transistor asa Class-AB limiter

I Independence fromthe technologyparameters

J Need for an extrabias reference

IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)

IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 10/27

Type I with Class-AB Smoother

I Low-levelcommon-modecurrent injection

I Instability preventionunder a highClass-AB modulation

J Need for extracurrent sources

IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)

IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 11/27

Type II

Iinp =[

2(

B√

IonnD +C

√Ionp

D

)−(B+C)

(√Ionp

D −√

IinpA

)](√Ionp

D −√

IinpA

)

D .= A(B+C)A+B+C Imax '

1+ AC

1+ AB+C

Itail > Itail

I Independence from thetechnology parameters

I Auto-biased Class-ABlimiter

I Self-latch prevention

I Simple sizing procedure

IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)

IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 12/27

1 Introduction

2 Class-AB Architecture

3 Process-Independent Circuits

4 Practical Design

5 Experimental Results

6 Conclusions

IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)

IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 13/27

Type-II OpAmp Using a 0.18-µm CMOS TechnologyI Circuit design based on the

inversion-coefficient

I Reduced set of transistormatching groups

I Minimum-channel-lengthdevices can be used

I Bias for cascode transistorsoptimized for maximumoutput full scale

I 1.8-V nominal voltagesupply of the CMOStechnology

IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)

IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 14/27

Simulation Results

I DC transfer curve

I Analytical versusnumericalbehavior

I Class-AB achievesabout ×4 biascurrent

− 1 − 0.5 0 0.5 10

2

4

6

8

10

Ionn Ionp

I inp − I inn [mA]

[mA]

AnalyticalNumerical

IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)

IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 15/27

Simulation Results

I Frequencyresponse

I 200-pF loadcapacitance

103 104 105 106 107 108 109

0

−60

−120

−180

Frequency [Hz]

Phase[°]

PhaseGain

0

10

20

30

40

50

60

70

80

72 dB

50 °

Differentia

lGain[dB]

IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)

IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 16/27

Simulation Results

I Step response for several load conditions

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

−1

0

1

2

Time × Input Frequency [-]

Differentia

lOutpu

tVo

ltage

[V]

650 µF at 1 Hz, 650 nF at 1 kHz 650 pF at 1 MHz

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

−1

0

1

2

Time × Input Frequency [-]

Differentia

lOutpu

tVo

ltage

[V]

650 µF at 1 Hz, 650 nF at 1 kHz 650 pF at 1 MHz

I Stability robustness

IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)

IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 17/27

Integration

I Standard0.18-µm 1P6MCMOStechnology

I 0.07-mm2 area

I Additional CMFBaveragingcapacitors for SCapplications

IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)

IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 18/27

Integration

I Standard0.18-µm 1P6MCMOStechnology

I 0.07-mm2 area

I Additional CMFBaveragingcapacitors for SCapplications

IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)

IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 19/27

1 Introduction

2 Class-AB Architecture

3 Process-Independent Circuits

4 Practical Design

5 Experimental Results

6 Conclusions

IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)

IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 20/27

Step Response

−1

0

1SimulatedMeasured

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20

5

10Isupply

Iopp Iopn

Time [ms]

Cur

rent

[mA

]D

iff. O

utpu

t Vo

ltage

[V]

IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)

IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 21/27

Full-Scale Evaluation

0 20 40 60 80 100 120 140 160 180 200−2

−1

0

1

2

Time [ms]

Differentia

lOutpu

tVo

ltage

[V]

IdealSimulatedMeasured

0 20 40 60 80 100 120 140 160 180 200−2

−1

0

1

2

Time [ms]

Differentia

lOutpu

tVo

ltage

[V]

IdealSimulatedMeasured

I 3.3-Vpp differential full scale at 1.8-V voltage supply

IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)

IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 22/27

Figure-of-Merit Comparison

Parameter [1] [2] [3] [4] [5] Thiswork Units

Technology 0.5 0.5 0.25 0.13 0.18 0.18 µmSupply 2 2 1.2 1.2 0.8 1.8 VDC gain 43 45 69 70 51 72 dBCload 80 25 4 5.5 8 200 pFGBW 0.725 11 165 35 0.057 86.5 MHzPhase margin 89.5 N/A 65 45 60 50 °Slew rate, SR 89 20 329 19.5 0.14 74.1 V/µsStatic power, P 0.12 0.04 5.8 0.11 0.0012 11.9 mWArea 0.024 0.012 N/A 0.012 0.057 0.07 mm2

FOM 59.33 12.50 0.28 0.98 0.93 1.25 Vµs

pFµW

FOM =SR·Cload

P

[Vµs

pFµW

]

IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)

IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 23/27

1 Introduction

2 Class-AB Architecture

3 Process-Independent Circuits

4 Practical Design

5 Experimental Results

6 Conclusions

IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)

IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 24/27

Conclusions

I New family of Class-AB OpAmps

I Single-stage topology

I No need for an internal frequency compensation

I Class-AB current peaks in the output transistors only

I Low sensitivity to the technology parameter variations

I Simple analytical design flow

I Successfully used in a 16-bit 100-kS/s ΔΣ ADC

Thank you!

IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)

IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 25/27

References[1] A. J. Lopez-Martin, S. Baswa, J. Ramirez-Angulo, and R. G. Carvajal,

“Low-Voltage Super Class AB CMOS OTA Cells With Very High Slew Rate andPower Efficiency,” IEEE Journal of Solid-State Circuits, vol. 40, pp. 1068–1077,2005.

[2] J. Ramirez-Angulo, R. G. Carvajal, J. A. Galan, and A. Lopez-Martin, “A Free ButEfficient Low-Voltage Class-AB Two-Stage Operational Amplifier,” IEEETransactions on Circuits and Systems II: Expressed Briefs, vol. 53, pp. 568–571,2006.

[3] M. Yavary and O. Shoaei, “Very Low-Voltage, Low-Power and Fast-Settling OTAfor Switched-Capacitor Applications,” in Proceedings of the InternationalConference on Microelectronics, 2002, pp. 10–13.

[4] M. Figueiredo, R. Santos-Tavares, E. Santin, J. Ferreira, G. Evans, and J. Goes,“A Two-Stage Fully Differential Inverter-Based Self-Biased CMOS Amplifier WithHigh Efficiency,” IEEE Transactions on Circuits and Systems I: Regular Papers,vol. 58, pp. 1591–1603, 2011.

[5] M. R. Valero, S. Celma, N. Medrano, B. Calvo, and C. Azcona, “An UltraLow-Power Low-Voltage Class AB CMOS Fully Differential OpAmp,” inProceedings of the IEEE International Symposium on Circuits and Systems, 2012,pp. 1967–1970.

IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)

IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 26/27

Normalized Current Transfer Curve for Different B/C Ratios

IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)

IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 27/27

Normalized Current Transfer Curve Under Corners for B/C=3

−1 −0.5 0 0.5 10

1

2

3

4

2 IonnItail 2 Ionp

Itail

(Iinp − Iinn) /Itail

typical at 20 °Cfast at -40 °Cslow at 80 °C

IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)