designandmodelingofa0.4mw/ch multi-channelintegratedcircuit ...pserra/cnm/2010 - design and modeling...

DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 1/26

Design and Modeling of a 0.4mW/ChMulti-Channel Integrated Circuitfor Infrared Gas Recognition

S. Sutula, C. Ferrer and F. [email protected]

Integrated Circuits and Systems (ICAS)Instituto de Microelectrónica de Barcelona, IMB-CNM(CSIC)

November 2010

S. Sutula et al. IMB-CNM(CSIC)


1 Introduction

2 ROIC Channel Architecture

3 Pre-Amplification and Filtering

4 Blind Cancellation and Lock-in Demodulation

5 Integrating A/D Conversion

6 Post Layout High Level Modeling

7 CMOS Integration and Experimental Results

8 Conclusions



1 Introduction







8 Conclusions



Introduction

I Real-time gas recognition forenvironmental monitoring,toxic gas detection. . .

I IR spectroscopic absorptiondigital fingerprint

I Thermal µbolometer LWIRsensing array

I Multi-channel ROIC for fastacquisition and low-noise

I Channel lock-in demodulationfor high-accuracy

I Low-power operation toavoid thermal drifts of IRsensors

I Compact pitch for directsensors-ROIC bonding



1 Introduction







8 Conclusions



ROIC Channel Architecture

Vsens

Vamp

Ieff

Vlockin

Gm(2bit)Cint 1( bit)

fc(2bit)

G(2bit)

Vblind

event

Vintup

20bitCounter

event

Ibias(2bit)

A/D Converter

Bias & ref.generator

Config.Register

progin

dataout

down

Vcom

+Vth

-Vth

progout

datain

Rsens

I External lock-in synchronizationI Dedicated blind channel for cancellation of

common disturbing signalsI Individual configuration register per channel

I Highprogrammability

I No externalcomponents

I Built-in biasgenerators for lowcrosstalk

I Digital onlyinterface

∆Vsens = Ibias∆Rsens



1 Introduction







8 Conclusions



Pre-Amplification and FilteringJ Sub-Hz high-pass specs

J Independent gain and cornerprogrammability required

I Highly linear cap amplifier:

G = ∆Vamp

∆Vsens= CA

CB

I Subthreshold MRC filtering:

fc = fcoe−Vcorner

Ut fco = 12π

Itun(PTAT)

CBUt

I Fast initialization switch

CB

Vref

VsensCA

Vamp

Vcorner

Vtun

+

Itun

M2

M1

P£

init



Pre-Amplification and FilteringI Gain tuning by P scaling

I Multi-decade filter log tuning:

Vcorner = M∆Vcorner = MUt ln (NK)

fc = fco(NK)M

fc×10±3 ⇔ Vcorner±173mV at 25oC

M2M1

1 N:

K 1Vref

1 N:

K 1

¢Vcorner

M£

Vcorner

CB

Vref

VsensCA

Vamp

Vcorner

Vtun

+

Itun

M2

M1

P£

init



1 Introduction







8 Conclusions



Blind Cancellation and Lock-in Demodulation

I Differential to single endedI Voltage-to-current conversionI Lock-in demodulation

I Low-power subthreshold OTA:

Gm = Ieff∆Vamp

= Iota2nUt

∝ Ut

Iota ∝ IS = 2nβU 2t

I Current-domain lock-indemodulation by cross-coupling

I Voltage log compression allowsfast switching at low-power

Vamp

Iota

M3M4

M1 M2

Vblind

M5 M6

Ieff

M7 M8

Vlockin

+

Vref

PDM stageof the ADC

(cascode topology not shown)



1 Introduction







8 Conclusions



Integrating A/D ConversionI PDM noise shapingI Digital counter as low-pass filter

I Asynchronous operation for verylow-power and low-crosstalk

Ieff

Cint 1( bit)

event

Vintup

20bitCounter

event

Pulse density modulation

dataout

down

+Vth

-Vth

datain

Digitalfiltering





I Loss-less analog integrator with CDSfor high-linearity and noise reduction:

fPDM = IeffCintVth

Vint

Cint

Vref

Creset CDS/

Ieff

V Vref th-

upevent

down

Vref+Vth

event

init





I Loss-less analog integrator with CDSfor high-linearity and noise reduction:

fPDM = IeffCintVth

I Built-in threshold comparator:

Vth = nUt ln X

I Thermal compensation of Gm :

qadc = bnadcc nadc = TsampfPDM = CA

CB

Gm

Vth

Tsamp

Cint∆Rsens

Vint

Cint

Vref

Creset CDS/

Ieff

V Vref th-

upevent

down

Vref+Vth

event

init

Vint

up down

Vref

M5M4

X 1X1

M1 M3



1 Introduction







8 Conclusions



Post Layout High Level ModelingI Simulation time

reduction

I Complete read-outchannel model

I Entire set of channelconfigurations

Overflow2

DataOut1

Preamplifier

Vsens Vamp

PDM

Ieff

Vint

Up

Down

event

Lock-in Demodulator

Vamp

Vblind

Vlockin

Ieff

Integrator

Ieff

eventVint Digital

Filter

Up

Down

DataOut

Overflow

Vlockin3

Vblind2

Vsens1



Post Layout High Level ModelingI Simulation time

reduction

I Complete read-outchannel model

I Entire set of channelconfigurations

I Wide range ofnonidealitiesmodeling

I Technology processand temperature

I Flicker and thermalnoise options

I External sensormodeling

Overflow2

DataOut1

Preamplifier

Vsens Vamp

PDM

Ieff

Vint

Up

Down

event

Lock-in Demodulator

Vamp

Vblind

Vlockin

Ieff

Integrator

Ieff

eventVint Digital

Filter

Up

Down

DataOut

Overflow

Vlockin3

Vblind2

Vsens1

DC Output Level

Vamp1

WhiteNoise

OutputRangeLimit

NoiseModeling

H_n

1/w_ns+1

Low-Pass

1

1/w_ls+1High -Pass

s

s+w_hGain

A

Vdc

Vsens1



1 Introduction







8 Conclusions



CMOS Integration and Experimental Results

I 0.35µm 2P4M CMOSchannel module test chip

I Main design parameters:

CA = 20pFCB = 0.1, 0.2, 0.4, 1pFK = 10N = 1, 11M = 3

Itun = 100nAIota = 1, 2, 5, 10µAVth = 120mV

Tpulse = 500ns

10 full channelsfor crosstalk study

blindchannel

channelblocks

sensorbias

high-passpre-amp

reference generator PDM

config.register

async.counter

100 m¹

I Access to intermediate stages



CMOS Integration and Experimental ResultsI Sub-Hz pre-amplifier

independent tuning(16 configurations)

Frequency [Hz]

100k10k1k1001010.1

-30

-20

-10

0

10

20

30

40

50

gain<1:0>=00

01

10

11

corner<1:0>=00011011

-30

-20

-10

0

10

20

30

40

50

jj

¢/¢

VV

amp

sens

[dB

]j

j¢

/¢V

Vamp

sens

[dB

]





I Highly linear PDMup to pulse widthhard limit

100

transc<1:0>=00

01

10

11

¢ [mV]Vamp

1010.1

1M

100k

10k

1k

12Tpulse

fPDM

[Hz]

for cint<0>=0





I Highly linear PDMup to pulse widthhard limit

I 9bit digitalprogrammability perchannel

I No crosstalkobserved betweenchannels

experimental (vs simulated)results per channel

Parameter Value UnitsIbias bias<1:0>=00 0.97 (1) µA

01 1.9 (2)10 4.6 (5)11 9.1 (10)

fc corner<1:0>=00 0.3 (0.25) Hz01 3.9 (4.1)10 50 (60)11 625 (825)

G gain<1:0>=00 27 (26) dB01 34 (34)10 40 (40)11 46 (45)

Gm transc<1:0>=00 (15) µS01 (30)10 (70)11 (130)

Cint cint<0>=0 (5) pF1 (10) pF

Total Harmonic Distortion <0.25 %Crosstalk <0.5 LSB

Vnieq for Rsens=300kΩ (100) nVrms/√

HzSupply voltage 3.3 VSupply current 100 µA

Silicon area 300×715 µm2



1 Introduction







8 Conclusions



Conclusions

I Digital read-out channel for IR spectroscopic gas recognitionI Fully integrable sub-Hz high-pass pre-amplificationI Blind cancellation and lock-in demodulationI Highly linear integrating A/D conversionI High-programmability (9bit) per channelI Low-current (100µA) and compact (0.2mm2) channel

module in 0.35µm 2P4M CMOS technologyI Experimental results agree with simulated performanceI Post layout high level modelingI No-crosstalk reported between channels

. . . thanks for your attention!



Improvements?J Pre-amplifier dynamic offset

¢Vsens

Vtun1

M1

Vtun3

M3

¢Vout/Ut

0 1 2-1-2

0

4

8

-4

-8

¢I c

ap/I

tuneff

M1M3

¢Vout

¢Icap

¢Vsens

Vtun1

M1

¢Vout/Ut

0 1 2-1-2

0

4

8

-4

-8

¢I c

ap/I

tuneff

¢Vout

¢Icap

(a) (b)

J OTA linear range

Imax

M3 M4

M9 M10

Iout

M11 M12

M6

Itun

Imax

M2M1

M7M8

M5

Itun

Vcom+Vdiff

2Vcom -Vdiff

2

I A 32-channel ROIC is underdevelopment!


designandmodelingofa0.4mw/ch multi-channelintegratedcircuit ...pserra/cnm/2010 - design and modeling...

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