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General DescriptionThe MAX11301 integrates a PIXI™, 12-bit, multichannel, analog-to-digital converter (ADC) and a 12-bit, multichan-nel, buffered digital-to-analog converter (DAC) in a single integrated circuit. This device offers 20 mixed-signal high-voltage, bipolar ports, which are configurable as an ADC analog input, a DAC analog output, a general purpose input (GPI), a general-purpose output (GPO), or an analog switch terminal. One internal and two external temperature sensors track junction and environmental temperature. Adjacent pairs of ports are configurable as a logic-level translator for open-drain devices or an analog switch. PIXI ports provide highly flexible hardware configuration for 12-bit mixed-signal applications. The MAX11301 is best suited for applications that demand a mixture of analog and digital functions. Each port is individually configurable with up to four selectable voltage ranges within -10V to +10V. The MAX11301 allows for the averaging of 2, 4, 8, 16, 32, 64, or 128 ADC samples from each ADC-configured port to improve noise performance. A DAC-configured output port can drive up to 25mA. The GPIO ports can be pro-grammed to user-defined logic levels, and a GPI coupled with a GPO forms a logic-level translator. Internal and external temperature measurements monitor programmable conditions of minimum and maximum tem-perature limits, using the interrupt to notify the host if one or more conditions occur. The temperature measurement results are made available through the serial interface.The MAX11301 features an internal, low-noise 2.5V volt-age reference and provides the option to use external voltage references with separate inputs for the DAC and ADC. The MAX11301 uses a 400kHz I2C-compatible serial interface, operating from a 5V analog supply and a 1.8V to 5.0V digital supply. The PIXI port supply voltages operate from a wide -12.0V to +12.0V. The MAX11301 is available in a 40-pin TQFN, 6mm x 6mm package or a 48-pin TQFP, 9mm x 9mm package specified over the -40°C to +105°C temperature range.

Applications ● Base-Station RF Power Device Bias Controllers ● System Supervision and Control ● Power-Supply Monitoring ● Industrial Control and Automation ● Control for Optical Components

Benefits and Features ● 20 Configurable Mixed-Signal Ports Maximize Design

Flexibility Across Platforms• Up to 20 12-Bit ADC Inputs

- Single-Ended, Differential, or Pseudo-Differential - Range Options: 0 to 2.5V, ±5V, 0 to +10V, -10V to 0V

- Programmable Sample Averaging Per ADC Port - Unique Voltage Reference for Each ADC PIXI Port

• Up to 20 12-Bit DAC Outputs - Range Options: ±5V, 0 to +10V, -10V to 0V - 25mA Current Drive Capability with Overcurrent Protection

• Up to 20 General-Purpose Digital I/Os - 0 to +5V GPI Input Range - 0 to +2.5V GPI Programmable Threshold Range - 0 to +10V GPO Programmable Output Range - Logic-Level Shifting Between Any Two Pins

• 60Ω Analog Switch Between Adjacent PIXI Ports• Internal/External Temperature Sensors, ±1˚C

Accuracy ● Adapts to Specific Application Requirements and

Allows for Easy Reconfiguration as System Needs Change

● Configurability of Functions Enables Optimized PCB Layout

● Reduces BOM Cost with Fewer Components in Small Footprint• 36mm2 40-Pin TQFN • 49mm2 48-Pin TQFP

Ordering Information appears at end of data sheet.

PIXI is a trademark of Maxim Integrated Products, Inc..

For related parts and recommended products to use with this part, refer to www.maximintegrated.com/MAX11301.related.

19-7579; Rev 1; 7/19

Click here for production status of specific part numbers.

MAX11301 PIXI, 20-Port Programmable Mixed-Signal I/O with 12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO

EVALUATION KIT AVAILABLE

http://www.maximintegrated.com/MAX11301.relatedhttps://www.maximintegrated.com/en/storefront/storefront.html


www.maximintegrated.com Maxim Integrated │ 2

DAC SEQUENCER

INT

CNVT

D0N

INTERNALREFERENCE

ADC

2.5V

2.5V

SERIAL INTERFACE

AND DIGITALCORE

ADC SEQUENCER

20

20

20

20

20

DAC

GPI

GPO

AD1

AD0

SCL

SDA

EXT AND INT TEMP SENSORS

TEMPERATURE MONITORS D0P

D1ND1P

DGND AGND AVSSIO

DVDD DAC_REF ADC_INT_REF ADC_EXT_REF AVDD AVDDIO

MAX11301

REFERENCE MUX

(0≤x≤18)

PORT[x+1]

PORT[x]

AGND1

PIXI PORT MANAGER

CLOCK GENERATOR

Functional Diagram

DVDD to DGND .......................................................-0.3V to +6VAVDD to AGND .......................................................-0.3V to +6VAVDDIO to AVSSIO ...............................................-0.3V to +25VAVDDIO to AGND ..................................................-0.3V to +17VAVSSIO to AGND ..................................................-14V to +0.3VAGND to AGND1 ..................................................-0.3V to +0.3VAGND to DGND ...................................................-0.3V to +0.3VAGND1 to DGND .................................................-0.3V to +0.3V(PORT0 to PORT19) to AGND ............max of (VAVSSIO - 0.3V)

or -14V to min of (VAVDDIO + 0.3V) or +17V(PORT0 to PORT19) to AGND (GPI and Bidirectional Level

Translator Modes) .........-0.3V to min of (VAVDD + 0.3V) or +6VCNVT to DGND ............-0.3V to min of (VDVDD + 0.3V) or +6VINT to DGND ...........................................................-0.3V to +6V(SDA, SCL) to DGND ..............................................-0.3V to +6V(AD0, AD1) to DGND ....-0.3V to min of (VDVDD + 0.3V) or +6V

DAC and ADC Reference Pins to AGND (DAC_REF, ADC_INT_REF, ADC_EXT_REF) ................... -0.3V to min of

(VAVDD +0.3V) or +4VTemperature Sensor Pins (D0N, D0P, D1N, D1P) to AGND......................... -0.3V to min of

(VAVDD + 0.3V) or +6VCurrent into Any PORT Pin ..............................................100mACurrent into Any Other Pin Except Supplies

and Ground .....................................................................50mAContinuous Power Dissipation (TA = +70°C) (Multilayer board) TQFN (derate 37mW/°C above +70°C) ...................2963mW TQFP (derate 36.2mW/°C above +70°C) ...............2898.6mWOperating Temperature Range ..........................-40ºC to +105°CStorage Temperature Range .............................-65ºC to +150°CLead Temperature (soldering, 10s) .................................+300°CSoldering Temperature (reflow) .......................................+260°C

TQFN Junction-to-Case Thermal Resistance (θJC) .................1°C/WJunction-to-Ambient Thermal Resistance (θJA)...........27°C/W

TQFP Junction-to-Case Thermal Resistance (θJC) .................2°C/WJunction-to-Ambient Thermal Resistance (θJA)........27.6°C/W

ADC Electrical Specifications(VAVDD = 4.75V to 5.25V, VDVDD = 3.3V, VAVDDIO = +12.0V, VAGND = VDGND = 0V, VAVSSIO = -2.0V, VDACREF = 2.5V, VADCREF = 2.5V (Internal), fS = 400ksps, 10V analog input range set to range 1 (0 to +10V). TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITSDC ACCURACY (Note 3)Resolution 12 BitsIntegral Nonlinearity INL ±2.5 LSBDifferential Nonlinearity DNL No missing codes over temperature ±1 LSBOffset Error ±0.5 ±8 LSBOffset Error Drift ±0.002 LSB/ºCGain Error ±11 LSBGain Error Drift ±0.01 LSB/ºC

Channel-to-Channel Offset Matching 1 LSB

Channel-to-Channel Gain Matching 2 LSB



Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

(Note 1)Package Thermal Characteristics

Electrical Characteristics

ADC Electrical Specifications(VAVDD = 4.75V to 5.25V, VDVDD = 3.3V, VAVDDIO = +12.0V, VAGND = VDGND = 0V, VAVSSIO = -2.0V, VDACREF = 2.5V, VADCREF = 2.5V (Internal), fS = 400ksps, 10V analog input range set to range 1 (0 to +10V). TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITSDYNAMIC PERFORMANCE (SINGLE-ENDED INPUTS)Signal-to-Noise Plus Distortion SINAD fS = 400ksps, fIN = 10kHz 70 dBSignal to Noise SNR fS = 400ksps, fIN = 10kHz 71 dBTotal Harmonic Distortion THD fS = 400ksps, fIN = 10kHz -75 dBSpurious-Free Dynamic Range SFDR fS = 400ksps, fIN = 10kHz 75 dBCrosstalk -85 dBDYNAMIC PERFORMANCE (DIFFERENTIAL INPUTS)Signal-to-Noise Plus Distortion SINAD fS = 400ksps, fIN = 10kHz 71 dBSignal to Noise SNR fS = 400ksps, fIN = 10kHz 72 dBTotal Harmonic Distortion THD fS = 400ksps, fIN = 10kHz -82 dBSpurious-Free Dynamic Range SFDR fS = 400ksps, fIN = 10kHz 82 dBCrosstalk -85 dBCONVERSION RATE

Throughput (Note 4)

ADCCONV[1:0] = 00 200

kspsADCCONV[1:0] = 01250

ADCCONV[1:0] = 10 333

ADCCONV[1:0] = 11 400

Acquisition Time tACQ

ADCCONV[1:0] = 00 3.5

μsADCCONV[1:0] = 012.5

ADCCONV[1:0] = 10 1.5

ADCCONV[1:0] = 11 1.0ANALOG INPUT (All Ports)

Absolute Input Voltage (Note 5) VPORT

Range 1 0 10

VRange 2 -5 +5Range 3 -10 0Range 4 0 2.5

Input ResistanceRange 1, 2, 3 70 100 130 kΩRange 4 50 75 100 kΩ



Electrical Characteristics (continued)

(VAVDD = 4.75V to 5.25V, VDVDD = 3.3V, VAVDDIO = +12.0V, VAGND = VDGND = 0V, VAVSSIO = -2.0V, VDACREF = 2.5V, VADCREF = 2.5V (Internal), fS = 400ksps, 10V analog input range set to range 1 (0 to +10V). TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)

(VAVDD = 5.0V, VDVDD = 3.3V, VAVDDIO = +12.0V, VAGND = VDGND = 0V, VAVSSIO = -2.0V, VDACREF = 2.5V, VADCREF = 2.5V (Internal), fS = 400ksps, 10V analog input range set to range 1 (0 to +10V). TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITSADC INTERNAL REFERENCEReference Output Voltage Internal references at TA = +25°C 2.494 2.5 2.506 VREF Output Tempco (Note 6) TC-VREF ±10 ±25 ppm/°C

Capacitor Bypass at ADC_INT_REF 4.7 10 µF

DAC INTERNAL REFERENCEReference Output Voltage Internal references at TA = +25°C 2.494 2.5 2.506 VREF Output Tempco (Note 6) TC-VREF ±10 ±25 ppm/°CCapacitor Bypass at DAC_REF 4.7 10 µFADC EXTERNAL REFERENCEReference Input Range 2 2.75 VDAC EXTERNAL REFERENCEReference Input Range 1.25 2.5 V

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITSGPIO EXCEPT IN BIDIRECTIONAL LEVEL TRANSLATION MODEProgrammable Input Logic Threshold

VITH 0.3 VDACREF V

Input High Voltage VIH VITH + 0.3 V

Input Low Voltage VIL VITH - 0.3 VHysteresis ±30 mV

Programmable Output Logic Level VOLVL 04 x VD-ACREF

V

Propagation Delay from GPI Input to GPO Output in Unidirectional Level Translating Mode

Midscale threshold-5V logic swing 2 µs

BIDIRECTIONAL LEVEL TRANSLATION PATH AND ANALOG SWITCHInput High Voltage VIH 1 VInput Low Voltage VIL 0.2 VOn-Resistance From VAVSSIO + 2.50V to VAVDDIO - 2.50V 60 Ω

Propagation Delay10kΩ pullup resistors to rail in each side. Midvoltage to midvoltage when driving side goes from high to low

1 µs



REF Electrical Specifications

GPIO Electrical Specifications



PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITSANALOG SWITCHTurn-On Delay (Note 7) 400 nsTurn-Off Delay (Note 7) 400 nsOn-Time Duration (Note 7) 1 µsOff-Time Duration (Note 7) 1 µs

On-Resistance From VAVSSIO + 2.50V to VAVDDIO - 2.50V60 Ω

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITSDC ACCURACYResolution N 12 Bits

Output Range (Note 5) VPORT

Range 1 0 +10VRange 2 -5 +5

Range 3 -10 0Integral Linearity Error INL From code 100 to code 3996 ±0.5 ±1.5 LSBDifferential Linearity Error DNL ±0.5 ±1 LSBOffset Voltage At code 100 ±20 LSB

Offset Voltage Tempco 15 ppm/°CGain Error From code 100 to code 3996 -0.6 +0.6 % of FS

Gain Error Tempco From code 100 to code 3996 4 ppm of FS/°C

Power-Supply Rejection Ratio PSRR 0.4 mV/V

DYNAMIC CHARACTERISTICSOutput Voltage Slew Rate SR 1.6 V/µs

Output Settling Time To ±1 LSB, from 0 to full scale, output load capacitance of 250pF (Note 8) 40 µs

Settling Time After Current- Limit Condition 6 µs

Noise f = 0.1Hz to 300kHz 3.8 mVP-P



GPIO Electrical Specifications (continued)

DAC Electrical Specifications


(VAVDD = 5.0V, VDVDD = 1.62V to 5.50V, VAVDDIO = +12.0V, VAGND = VDGND = 0V, VAVSSIO = -2.0V, VDACREF = 2.5V, VADCREF = 2.5V (Internal), fS = 400ksps, 10V analog input range set to range 1 (0 to +10V). TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITSTRACK-AND-HOLDDigital Feedthrough 5 nV·sHold Step (Note 6) 1 6 mVDroop Rate (Note 6) 0.3 15 mV/s

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITSI2C IO DC SPECIFICATION

Input Logic-High Voltage (SDA, SCL, AD0, AD1, CNVT)

VDVDD = 2.5V to 5.5V0.7 x

VDVDD VVDVDD = 1.62V to 2.5V

0.85 x VDVDD

Input Logic-Low Voltage (SDA, SCL, AD0, AD1, CNVT)

VDVDD = 2.5V to 5.5V0.3 x

VDVDD VVDVDD = 1.62V to 2.5V

0.15 x VDVDD

Input Leakage Current (SDA, SCL, AD0, AD1, CNVT) -10 +10 µA

Input Capacitance (SDA, SCL, AD0, AD1, CNVT) 10 pF

Output Logic-Low Voltage (SDA) ISNK = 3mA 0.4 V

Output Logic-Low Voltage (INT)ISNK = 5mA, VDVDD = 2.5V to 5.5V 0.4

VISNK = 2mA, VDVDD = 1.62V to 2.5V 0.2

I2C TIMING REQUIREMENTS (Fast Mode) (See Figure 1)Serial Clock Frequency fSCL 0 400 kHz

Bus Free Time Between STOP and START Condition tBUF 1.3 µs

Hold Time (Repeated) START Condition tHD;STA

After this period, first clock pulse is generated 0.6 µs

SCL Pulse-Width Low tLOW 1.3 µsSCL Pulse-Width High tHIGH 0.6 µs



DAC Electrical Specifications (continued)

Interface Digital IO Electrical Specifications

(VAVDD = 5.0V, VDVDD = 1.62 to 5.50V, VAVDDIO = +12.0V, VAGND = VDGND = 0V, VAVSSIO = -2.0V, VDACREF = 2.5V, VADCREF = 2.5V (Internal), fS = 400ksps, 10V analog input range set to range 1 (0 to +10V). TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)

Figure 1. I2C Timing

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITSSetup Time for Repeated START Condition tSU;STA 0.6 µs

Data Hold Time tHD;DAT 0 900 nsData Setup Time tSU;DAT 100 ns

SDA and SCL Receiving Rise Time tr (Note 6)

20 x (VDVDD /5.5V)

300 ns

SDA and SCL Receiving Fall Time tf (Note 6)

20 x (VDVDD /5.5V)

300 ns

SDA Transmitting Fall Time tof20 x

(VDVDD /5.5V)

250 ns

Setup Time for STOP Condition tSU;STO 0.6 µsBus Capacitance Allowed Cb VDVDD = 2.5V to 5.5V 400 pF

Pulse Width of Suppressed Spike tSP 50 ns

SDA

SCL

tBUF

tSU;STO

t rtSPtHD;STA

tSU;STA

tf

t HIGH

tSU;DAT

tHD;DAT

trtLOW

tHD;STA

tf

S SSr P



Interface Digital IO Electrical Specifications (continued)

Internal and External Temperature Sensor Specifications(VAVDD = 4.75V to 5.25V, VDVDD = 3.3V, VAVDDIO = +12.0V, VAGND = VDGND = 0V, VAVSSIO = -2.0V, VDACREF = 2.5V, VADCREF = 2.5V (Internal), fS = 400ksps, 10V analog input range set to range 1 (0 to +10V). TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITSACCURACY

Accuracy of Internal Sensor (Notes 6, 9)

0°C ≤ TJ ≤ +80°C ±0.3 ±2.0 °C-40°C ≤ TJ ≤ +125°C ±0.7 ±5 °C

Accuracy of External Sensor (Notes 6, 9)

0°C ≤ TRJ ≤ +80°C ±0.3 ±2.0 °C-40°C ≤ TRJ ≤ +150°C ±1.0 ±5 °C

Temperature Measurement Resolution 0.125 °C

External Sensor Junction Current High 68 μALow 4 μA

External Sensor Junction CurrentHigh Series resistance cancellation mode 136 μALow Series resistance cancellation mode 8 μA

Remote Junction Current Conversion Ratio 17

D0N/D1N Voltage Internally generated 0.5 V

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITSVAVDD 4.75 5.25 VVDVDD 1.62 5.50 VVAVDDIO VAVDD 15.75 VVAVSSIO -12.0 0 VVAVDDIO to VAVSSIO VAVDD 24 V

IAVDD

All ports in high impedance 14 18

mALPEN = 1 11All ports in ADC-related modes 17All ports in DAC-related modes 18

IDVDD Serial interface in idle mode 2 μAIAVDDIO All ports in mode 0 150 μAIAVSSIO All ports in mode 0 -400 μA



Electrical Characteristics

Power-Supply Specifications

The values of VAVDDIO and VAVSSIO supply voltages depend on the application circuit and the device configuration.

VAVDDIO needs to be the maximum of those four values:

● If one or more ports are in mode 3, 4, 5, 6, or 10 (DAC-related modes), VAVDDIO must be set, at minimum, to the value of the largest voltage driven by any of the ports set in those modes. For improved linearity, it is recommended to set VAVDDIO 2.0V above the largest voltage value.

● If one or more ports are in mode 7, 8, or 9 (ADC-related modes), VAVDDIO must be set, at minimum, to the value of the largest voltage applied to any of the ports set in those modes.

● If one or more ports are in mode 11 or 12 (Analog switch-related modes), VAVDDIO must be set, at minimum, to 2.0V above the value of the largest voltage applied to any of the ports functioning as analog switch terminals.

● VAVDDIO cannot be set lower than VAVDD.

VAVSSIO needs to be the minimum of those four values:

● If one or more ports are in mode 3, 4, 5, 6, or 10 (DAC-related modes), VAVSSIO must be set, at maximum, to the value of the lowest voltage driven by any of the ports set in those modes. For improved linearity, it is recommended to set VAVSSIO 2.0V below the lowest voltage value.

● If one or more ports are in mode 7, 8, or 9 (ADC-related modes), VAVSSIO must be set, at maximum, to the value of the lowest voltage applied to any of the ports set in those modes.

● If one or more ports are in mode 11 or 12 (Analog Switch-related modes), VAVSSIO must be set, at maximum, to 2.0V below the value of the lowest voltage applied to any of the ports functioning as analog switch terminals.

● VAVSSIO cannot be set higher than VAGND.For example, the MAX11301 can operate with only one voltage supply of 5V (±5%) connected to AVDD, AVDDIO, and DVDD, and one ground of 0V connected to AGND, DGND, and AVSSIO. However, the level of performance presented in the electrical specifications requires the setting of the supplies connected to AVDDIO and AVSSIO as previously described.

ADC RANGE-10V TO 0V -5V TO +5V 0V TO +10V 0 TO 2.5V

DA

C R

AN

GE -10V TO 0V

VAVDDIO = +5VVAVSSIO = -12V




-5V TO +5V VAVDDIO = +7VVAVSSIO = -10VVAVDDIO = +7VVAVSSIO = -7V



0V TO +10V VAVDDIO = +12VVAVSSIO = -10VVAVDDIO = +12VVAVSSIO = -5V





Recommended VDDIO/VSSIO Supply Selection


PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITSPIXI PORTSInput Capacitance All PIXI ports 20 pFInput Resistance All PIXI input pins except ADC mode 50 75 100 kΩ

Startup Time Between stable supplies and accessing registers 100 ms

HIGH-VOLTAGE OUTPUT DRIVER CHARACTERISTICS

Maximum Output Capacitance 250 pF

Output Low Voltage, DAC Mode Sinking 25mA, VAVSSIO = 0V, VAVDDIO = 10VVAVSSIO

+ 1.0 V

Output High Voltage, DAC Mode Sourcing 25mA, VAVSSIO = 0V, VAVDDIO = 10VVAVDDIO

- 1.5 V

Output Low Voltage, GPO Mode Sinking 2mA, VAVSSIO = 0V, VAVDDIO = 10VVAVSSIO

+ 0.4 V

Output High Voltage, GPO Mode Sourcing 2mA, VAVSSIO = 0V, VAVDDIO = 10VVAVDDIO

- 0.4 V

Current LimitShort to AVDDIO 75 mAShort to AVSSIO 75 mA

Note 2: Electrical specifications are production tested at TA = +25°C. Specifications over the entire operating temperature range are guaranteed by design and characterization. Typical specifications are at TA = +25°C.

Note 3: DC accuracy specifications are tested for single-ended ADC inputs only.Note 4: The effective ADC sample rate for port X configured in mode 6, 7, or 8 is: [ADC sample rate per ADCCONV]/(([number of ports in modes 6,7,8] + [1 if TMPSEL ≠ 000]) x [2# OF SAMPLES for port X])Note 5: See the Recommended VDDIO/VSSIO Supply Selection table for each range. For ports in modes 6, 7, 8, or 9, the voltage

applied to those ports must be within the limits of their selected input range, whether in single-ended or differential mode. Note 6: Specification is guaranteed by design and characterization.Note 7: Switch controlled by GPI-configured port. One switch terminal connected to 0V, the other terminal connected to 5V through

a 5mA current source. Timing is measured at the 2.5V transition point. Turn-on and turn-off delays are measured from the edge of the control signal to the 2.5V transition point. Turn-on and turn-off durations are measured between control signal transitions.

Note 8: In DAC-related modes, the rate, at which PIXI ports configured in mode 1, 3, 4, 5, 6, or 10 are refreshed, is as follows: 1/(40µs x [number of ports in modes 1, 3, 4, 5, 6, 10])Note 9: Typical (TYP) values represent the errors at the extremes of the given temperature range.



Common PIXI Electrical Specifications

(TA = +25°C, unless otherwise noted.)

-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

0 1000 2000 3000 4000

DN

L (L

SB)

DIGITAL OUPUT CODE (DECIMAL)

RANGE 0V TO 10VRANGE -5V TO +5VRANGE -10V TO 0V

ADC DIFFERENTIAL NONLINEARITYvs. DIGITAL OUTPUT CODE

INTERNAL REFERENCEtoc02

-2.5

-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

2.5

0 1000 2000 3000 4000

INL

(LSB

)



ADC INTEGRAL NONLINEARITYvs. DIGITAL OUTPUT CODE

EXTERNAL REFERENCEtoc03

-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

0 1000 2000 3000 4000

DN

L (L

SB)



ADC DIFFERENTIAL NONLINEARITYvs. DIGITAL OUTPUT CODE


-9

-8

-7

-6

-5

-4

-3

-2

-1

0

1

-50 -25 0 25 50 75 100 125

OFF

SET

ERR

OR

(LS

B)

TEMPERATURE (°C)

RANGE 0-10VRANGE -5V - +5VRANGE -10 - 0VRANGE 0 - 2.5V

ADC OFFSET ERRORvs. TEMPERATURE

toc05

-4.5

-3.5

-2.5

-1.5

-0.5

0.5

1.5

-50 -25 0 25 50 75 100 125

GAI

N E

RR

OR

(LS

B)

TEMPERATURE (°C)

RANGE 0-10V RANGE -5V - +5V

RANGE -10 - 0V RANGE 0 - 2.5V

ADC GAIN ERRORvs. TEMPERATURE

toc06

-8

-7

-6

-5

-4

-3

-2

-1

0

1

4.7 4.8 4.9 5 5.1 5.2 5.3

OFF

SET

ERR

OR

(LS

B)

SUPPLY VOLTAGE (V)



ADC OFFSET ERRORvs. SUPPLY VOLTAGE

toc07

-2.5

-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

2.5

0 1000 2000 3000 4000

INL

(LSB

)



ADC INTEGRAL NONLINEARITYvs. DIGITAL OUTPUT CODE


-4

-3

-2

-1

0

1

4.7 4.8 4.9 5 5.1 5.2 5.3

GAI

N E

RR

OR

(LS

B)

SUPPLY VOLTAGE (V)



ADC GAIN ERRORvs. SUPPLY VOLTAGE

toc08

0.1

1

10

100

1000

10000

100000

-50 -25 0 25 50 75 100 125

SUPP

LY C

UR

REN

T (µ

A)

TEMPERATURE (°C)

SUPPLY CURRENTvs. TEMPERATURE

ADC RANGE 0V TO 10V

IAVDD

toc9a

IAVSSIO

IAVDDIO

IAVDDIO


Maxim Integrated │ 12www.maximintegrated.com

Typical Operating Characteristics


0.1

1

10

100

1000

10000

100000

-50 -25 0 25 50 75 100 125

SUPP

LY C

UR

REN

T (µ

A)

TEMPERATURE (°C)


ADC RANGE -5V TO +5V

IAVDD

toc9b

IAVSSIO

IAVDDIO

IAVDDIO

0.1

1

10

100

1000

10000

100000

-50 -25 0 25 50 75 100 125

SUPP

LY C

UR

REN

T (µ

A)

TEMPERATURE (°C)


ADC RANGE -10V TO 0V

IAVDD

toc9c

IAVSSIO

IAVDDIO

IAVDDIO

14

14.5

15

15.5

16

16.5

17

17.5

18

0 5 10 15 20

I AVD

DC

UR

REN

T (m

A)

NO.OF ADC-CONFIGURED PORTS

IAVDDvs. ADC CHANNELS

ADC RANGE0V TO 10V

toc10


ADC RANGE-10V TO 0V

2.494

2.496

2.498

2.500

2.502

2.504

2.506

-50 -25 0 25 50 75 100 125

REF

EREN

CE

VOLT

AGE

(V)

TEMPERATURE (°C)

ADC INTERNAL REFERENCEvs. TEMPERATURE

toc11

-1.5

-1

-0.5

0

0.5

1

1.5

0 1000 2000 3000 4000

INL

(LSB

)

DAC CODE (DECIMAL)


DAC INTEGRAL NONLINEARITYvs. DIGITAL CODE


-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

0 1000 2000 3000 4000

DN

L (L

SB)

DAC CODE (DECIMAL)


DAC DIFFERENTIAL NONLINEARITYvs. DIGITAL OUTPUT CODE


-1.5

-1

-0.5

0

0.5

1

1.5

0 1000 2000 3000 4000

INL

(LSB

)

DAC CODE (DECIMAL)


DAC INTEGRAL NONLINEARITYvs. DIGITAL CODE


-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

0 1000 2000 3000 4000

DN

L (L

SB)

DAC CODE (DECIMAL)


DAC DIFFERENTIAL NONLINEARITYvs. DIGITAL OUTPUT CODE


-2.5

-1.5

-0.5

0.5

1.5

2.5

3.5

-50 -25 0 25 50 75 100 125

OFF

SET

ERR

OR

(LS

B)

TEMPERATURE (°C)

RANGE 0V TO 10V

RANGE -5V TO +5V

RANGE -10V TO 0V

DAC OFFSET ERRORvs. TEMPERATURE

toc16



Typical Operating Characteristics (continued)


-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

-50 -25 0 25 50 75 100 125

GAI

N E

RR

OR

(LS

B)

TEMPERATURE (°C)

RANGE 0V TO 10V

RANGE -5V TO +5V

RANGE -10V TO 0V

DAC GAIN ERRORvs. TEMPERATURE

toc17

-2

-1

0

1

2

3

4

4.7 4.8 4.9 5 5.1 5.2 5.3

OFF

SET

ERR

OR

(LS

B)

SUPPLY VOLTAGE (V)

RANGE 0V TO 10V

RANGE -5V TO +5V

RANGE -10V TO 0V

DAC OFFSET ERRORvs. SUPPLY VOLTAGE

toc18

-1.5

-1.3

-1.1

-0.9

-0.7

-0.5

-0.3

-0.1

4.7 4.8 4.9 5 5.1 5.2 5.3

GAI

N E

RR

OR

(LS

B)

SUPPLY VOLTAGE (V)

RANGE 0V TO 10V

RANGE -5V TO +5V

RANGE -10V TO 0V

DAC GAIN ERRORvs. SUPPLY VOLTAGE

toc19

0.1

1

10

100

1000

10000

100000

-50 -25 0 25 50 75 100 125

SUPP

LY C

UR

REN

T (µ

A)

TEMPERATURE (°C)


DAC RANGE 0V TO 10V

IAVDD

toc20a

IAVSSIO

IAVDDIOIAVDDIO

0.1

1

10

100

1000

10000

100000

-50 -25 0 25 50 75 100 125

SUPP

LY C

UR

REN

T (µ

A)

TEMPERATURE (°C)


DAC RANGE -5V TO +5V

IAVDD

toc20b

IAVSSIO

IAVDDIOIAVDDIO

0.1

1

10

100

1000

10000

100000

-50 -25 0 25 50 75 100 125

SUPP

LY C

UR

REN

T (µ

A)

TEMPERATURE (°C)


DAC RANGE -10V TO 0V

IAVDD

toc20c

IAVSSIO

IAVDDIO IAVDDIO

13

14

15

16

17

18

19

0 5 10 15 20

I AVD

DC

UR

REN

T (m

A)

NO. OF DAC-CONFIGURED PORTS

IAVDDvs. DAC CHANNELS

ADC RANGE0V TO 10V

toc21a


ADC RANGE-10V TO 0V

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

0 5 10 15 20

I AVD

DIO

CU

RR

ENT

(mA)


IAVDDIOvs. DAC CHANNELS

ADC RANGE0V TO 10V

toc21b


ADC RANGE-10V TO 0V

0

1

2

3

4

5

6

7

0 5 10 15 20

I AVSS

IOC

UR

REN

T (m

A)


IAVSSIOvs. DAC CHANNELS

ADC RANGE0V TO 10V

toc21c


ADC RANGE-10V TO 0V





2.494

2.496

2.498

2.500

2.502

2.504

2.506

-50 -25 0 25 50 75 100 125

REF

EREN

CE

VOLT

AGE

(V)

TEMPERATURE (°C)

DAC INTERNAL REFERENCEvs. TEMPERATURE

toc22

2V/div

toc23

5µs/div

DAC SETTLING TIME CHANGE FROM PSV1 TO PSV2

PSV1 = 0X000PSV2 = 0XFFF

2V/div

toc24a

2.5µs/div

DAC SETTLING TIME CHANGE FROM MIN TO MAX

NO LOAD

2V/div

toc24b

2.5µs/div

DAC SETTLING TIME CHANGE FROM MAX TO MIN

NO LOAD

2V/div

toc24c

50µs/div

DAC SETTLING TIME CHANGE FROM MIN TO MAX

1µF CAP LOAD

2V/div

toc24d

50µs/div

DAC SETTLING TIME CHANGE FROM MAX TO MIN

1µF CAP LOAD

0.00

0.05

0.10

0.15

0.20

0.25

0.30

-50 -25 0 25 50 75 100 125

DR

OO

P R

ATE

(mV/

s)

TEMPERATURE (°C)

AVDD = 4.75V

AVDD = 5V

AVDD = 5.25V

DAC DROOP RATEvs. TEMPERATURE

(DAC RANGE 0 TO 10V)toc25a

0.00

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

-50 -25 0 25 50 75 100 125

DR

OO

P R

ATE

(mV/

s)

TEMPERATURE (°C)

AVDD = 4.75V

AVDD = 5V

AVDD = 5.25V


(DAC RANGE -5V TO +5V)toc25b

VAVDD = 4.75VVAVDD = 5VVAVDD = 5.25V





-0.40

-0.35

-0.30

-0.25

-0.20

-0.15

-0.10

-0.05

0.00

-50 -25 0 25 50 75 100 125

DR

OO

P R

ATE

(mV/

s)

TEMPERATURE (°C)

AVDD = 4.75V

AVDD = 5V

AVDD = 5.25V


(DAC RANGE -10V TO 0)toc25c

VAVDD = 4.75V

VAVDD = 5V

VAVDD = 5.25V

0.000

0.100

0.200

0.300

0.400

0.500

0.600

0.700

0.800

0.900

1.000

-50 -25 0 25 50 75 100 125

VOLT

AGE

(V)

TEMPERATURE (°C)

DAC VOH AND VOLvs. TEMPERATURE

(ILOAD = 25mA)toc26

VOH

VOL

60.0

60.2

60.4

60.6

60.8

61.0

61.2

61.4

61.6

61.8

62.0

-50 -25 0 25 50 75 100 125

CU

RR

ENT

(mA)

TEMPERATURE (°C)

DAC DRIVE CURRENT LIMIT vs. TEMPERATURE

DAC = 0V, SHORTED TO VDDIOtoc27

60.0

60.2

60.4

60.6

60.8

61.0

61.2

61.4

61.6

61.8

62.0

-50 -25 0 25 50 75 100 125

CU

RR

ENT

(mA)

TEMPERATURE (°C)

DAC DRIVE CURRENT LIMIT vs. TEMPERATURE

DAC = 10V, SHORTED TO VSSIOtoc28

CS5V/div

toc29

10µs/div

MAJOR-CODE TRANSITION GLITCHDAC CODE FROM 0x7FF TO 0x800

DAC VOUTAC-COUPLED1mV/div

20µV/div

toc30

1s/div

DAC OUTPUT NOISEINTERNAL REFERENCE

(0.1Hz TO 10Hz)

20µV/div

toc31

1s/div

DAC OUTPUT NOISEEXTERNAL REFERENCE

(0.1Hz TO 10Hz)

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

4.7 4.8 4.9 5 5.1 5.2 5.3

OFF

SET

(mV)

SUPPLY VOLTAGE (V)

Vth = 0.9V

Vth = 1.65V

Vth = 2.5V

GPI OFFSETvs. SUPPLY VOLTAGE

toc32

VTH = 0.9V

VTH = 1.65V

VTH = 2.5V





0

1

2

3

4

5

6

-50 -25 0 25 50 75 100 125

OFF

SET

(mV)

TEMPERATURE (°C)

Vth = 0.9V

Vth = 1.65V

Vth = 2.5V

GPI OFFSETvs. TEMPERATURE

toc33

VTH = 0.9V

VTH = 1.65V

VTH = 2.5V

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

-50 -25 0 25 50 75 100 125

TEM

PER

ATU

RE

ERR

OR

(°C

)

TEMPERATURE (°C)

INTERNAL TEMPERATURESENSOR ERROR

vs. TEMPERATUREtoc35

20

22

24

26

28

30

32

34

36

38

40

-50 -25 0 25 50 75 100 125

HYS

TER

ESIS

(±m

V)TEMPERATURE (°C)

VTH = 0.9V

VTH = 1.65V

VTH = 2.5V

GPI HYSTERESISvs. TEMPERATURE

toc34

VTH = 0.9V

VTH = 1.65V

VTH = 2.5V

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-50 -25 0 25 50 75 100 125

TEM

PER

ATU

RE

ERR

OR

(°C

)

TEMPERATURE (°C)

EXTERNAL TEMPERATURESENSOR ERROR

vs. TEMPERATUREtoc36




TQFN6mm x 6mm

MAX11301

TOP VIEW

DVD

D

SCL

AD0

AD1

INT

DG

ND

POR

T8

POR

T6

POR

T5

POR

T9

POR

T10

POR

T11

POR

T4

AVD

DIO

PORT13

PORT14

PORT15

PORT2

PORT1

PORT0

AGND

SDA

POR

T7

PORT16 AVDD

PORT17

PORT18

PORT19

D0N

D0P

DAC_REF+

AVDDIO

D1PAGND1

D1N

CN

VT

ADC

_IN

T_R

EF

ADC

_EXT

_REF

POR

T3

PORT12 20

19

18

17

16

15

14

13

12

11

21

10987654321

222324252627282930

31

32

33

34

35

36

37

38

39

40

EP



Pin Configurations

PORT11

PORT10

AVSSIO

PORT9

PORT8

PORT7

PORT6

AVSSIO

PORT5

PORT4

AVDDIO

PORT3

PORT19

DGND

DVDD

SDA

SCL

AD0

AD1

INT

CNVTADC_INT_REF

ADC_EXT_REF

DAC_REF

1

2

3

4

5

6

7

8

9

10

11

12

36

35

34

33

32

31

30

29

28

27

26

25

AGN

D

AGN

D

POR

T1

D1P

D1N

AVSS

IO

TQFP7mm x 7mm

81mm2, total area including pins

D0P

D0N

AVD

D

AVD

D

13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37

AVSS

IO

POR

T18

POR

T17

POR

T16

AVSS

IO

POR

T15

POR

T14

POR

T13

AVD

DIO

AGN

D

POR

T12

MAX11301PO

RT2

POR

T0

AVSS

IO

EP



Pin Configurations (continued)

PINNAME FUNCTION

TQFN TQFP1 2 DGND Digital Ground2 3 DVDD Positive Digital Supply3 4 SDA Serial Interface Input and Output4 5 SCL Serial Interface Clock Input5 6 AD0 Slave Address Bit 06 7 AD1 Slave Address Bit 17 8 INT Interrupt Open-Drain Output. Active low.8 9 CNVT ADC Trigger Control Input. Active low.

9 10 ADC_INT_REF ADC Internal Voltage Reference Output. Connect a bypass capacitor at this pin (4.7µF to 10µF).

10 11 ADC_EXT_REF ADC External Voltage Reference Input. Connect a bypass capacitor at this pin (4.7µF to 10µF).

11 12 DAC_REF DAC External/Internal Voltage Reference Input. Connect a bypass capacitor at this pin (4.7µF to 10µF).

12 13 D0P 1st External Temperature Sensor Positive Input13 14 D0N 1st External Temperature Sensor Negative Input14 15, 16 AVDD Positive Analog Supply. For TQFP, connect both pins to AVDD.15 17, 18 AGND Analog Ground. For TQFP, connect both pins to AGND.16 19 PORT0 Configurable Mixed-Signal Port 017 20 PORT1 Configurable Mixed-Signal Port 118 21 PORT2 Configurable Mixed-Signal Port 219 22 D1P 2nd External Temperature Sensor Positive Input20 23 D1N 2nd External Temperature Sensor Negative Input21 25 PORT3 Configurable Mixed-Signal Port 3

22, 33 26, 39 AVDDIO Analog Positive Supply For Mixed-Signal Ports. Connect both pins to AVDDIO.23 27 PORT4 Configurable Mixed-Signal Port 424 28 PORT5 Configurable Mixed-Signal Port 525 30 PORT6 Configurable Mixed-Signal Port 626 31 PORT7 Configurable Mixed-Signal Port 727 32 PORT8 Configurable Mixed-Signal Port 828 33 PORT9 Configurable Mixed-Signal Port 929 35 PORT10 Configurable Mixed-Signal Port 1030 36 PORT11 Configurable Mixed-Signal Port 1131 37 PORT12 Configurable Mixed-Signal Port 1232 38 AGND1 Analog Ground



Pin Description

PINNAME FUNCTION

TQFN TQFP34 40 PORT13 Configurable Mixed-Signal Port 1335 42 PORT14 Configurable Mixed-Signal Port 1436 43 PORT15 Configurable Mixed-Signal Port 1537 45 PORT16 Configurable Mixed-Signal Port 1638 46 PORT17 Configurable Mixed-Signal Port 1739 47 PORT18 Configurable Mixed-Signal Port 1840 1 PORT19 Configurable Mixed-Signal Port 19

—24, 29,34, 41,44, 48

AVSSIO Analog Negative Supply for Mixed-Signal Ports. For TQFP, connect all pins to AVSSIO.

— — EP Exposed Pad. For TQFN, connect EP to AVSSIO. For TQFP, connect EP to AGND.



Pin Description (continued)

PA Biasing—PIXI Solution

PIXITM

MAX11301

DAC0 TO 10V

MAX44285

FB2

VOUT2_DET

PTMA210152STAGE 2

PTMA210152STAGE 1

RF IN

TDD_CLK2

IOUT2_DET

VG2

VIN_DET

DAC0 TO 10V

DAC0 TO 10V

ADC0 TO 10V

ADC0 TO 2.5V

MAX17503DC/DC

MAX14850 USBMAXQ622

VOUT2(15V TO 28V)

VIN(36V)

VIN(36V)

RS

DAC0 TO 10V

MAX44285

FB1

VOUT1_DET

TDD_CLK1

IOUT1_DET

VG1

DAC0 TO 10V

ADC0 TO 10V

ADC0 TO 2.5V

MAX17503DC/DC

VOUT1(15V TO 28V) RS

ISO_I2C I2C



Typical Application Circuit

Detailed DescriptionFunctional OverviewThe MAX11301 has 20 configurable mixed-signal I/O ports. Each port is independently configured as a DAC output, an ADC, a GPI input, a GPO, or an analog switch terminal. User-controllable parameters are avail-able for each of those configurations. The device offers one internal and two external temperature sensors. The serial interface operates as a Fast Mode I2C-compatible interface.The DAC is used to drive out a voltage defined by the DAC data register of the DAC-configured ports. The DAC uses either an internal or external voltage reference. The selection of the voltage reference is set for all the ports and cannot be configured on a port-by-port basis. The ADC converts voltages applied to the ADC-configured ports. The ADC can operate in single-ended mode or in differential mode, by which any two ports can form a dif-ferential pair. The port configured as the negative input of the ADC can be used by more than one differential ADC input pairs. The ADC uses either an internal or external voltage reference. In some configurations, the ADC uses the DAC voltage reference. The ADC voltage reference selection can be configured on a port-by-port basis. Interrupts provide the host with the occurrence of user-selected events through the configuration of an interrupt mask register.

ADC OperationsThe ADC is a 12-bit, low-power, successive approxima-tion analog-to-digital converter, capable of sampling a single input at up to 400ksps. The ADC’s conversion rate can be programmed to 400ksps, 333ksps, 250ksps, or 200ksps. The default conversion rate setting is 200ksps. Each ADC-configured port can be programmed for one of five input voltage ranges: 0 to +10V, -5V to +5V, -10V to 0V, and 0 to +2.5V. The ADC uses the internal ADC 2.5V voltage reference, the external ADC voltage reference, or, in some cases, the DAC voltage reference. The voltage reference can be selected on a port-by-port basis.

ADC ControlThe ADC can be triggered using an external signal CNVT or from a control bit. CNVT is active-low and must remain low for a minimal duration of 0.5 µs to trigger a conver-sion. Four configurations are available:

• Idle mode (default setting).• Single sweep mode. The ADC sweeps sequentially the ADC-configured ports, from the lowest index port to the highest index port, once CNVT is asserted. • Single conversion mode. The ADC performs a single conversion at the current port in the series of ADC-configured ports when CNVT is asserted. • Continuous sweep mode. The ADC continuously sweeps the ADC-configured ports. The CNVT port has no effect in this mode.

ADC Averaging FunctionADC-configured ports can be configured to average blocks of 2, 4, 8, 16, 32, 64, or 128 conversion results. The corresponding ADC data register is updated only when the averaging is completed, thus decreasing the throughput proportionally. If the number of samples to average is modified for a given port, the content of the ADC data register for that port is cleared before starting to average the new block of samples.

ADC Mode ChangeWhen users change the ADC active mode (continuous sweep, single sweep, or single conversion), the ADC data registers are reset. However, ADC data registers retain content when the ADC is changed to idle mode.

ADC ConfigurationsThe ADC can operate in single-ended, differential, or pseudo-differential mode. In single-ended mode, the PIXI port is the positive input to the ADC while the negative input is grounded internally (Figure 2). In differential mode (Figure 3), any pair of PIXI ports can be configured as inputs to the differential ADC. In pseudo-differential mode (Figure 4), one PIXI port produces the voltage applied to the negative input of the ADC while another PIXI port forms the positive input.The ADC data format is straight binary in single-ended mode, and two’s complement in differential and pseudo-differential modes.



DAC OperationsThe MAX11301 uses a 12-bit DAC, which operates at the rate of 40µs per port. Since up to 20 ports can be config-ured in DAC-related modes, the minimum refresh rate per port is 1.25kHz. No external component is required to set the offset and gain of the DAC drivers. The PIXI port driver features a wide output voltage range of ±10V and high current capa-bility with dedicated power supplies (AVDDIO, AVSSIO).The DAC uses either the internal or external voltage refer-ence. Unlike the ADC, the DAC voltage reference cannot be configured on a port-by-port basis. DAC mode configu-ration is illustrated in Figure 5.DAC operations can be monitored by the ADC. In such a mode, the ADC samples the DAC-configured port to allow the host to monitor that the voltage at the port is within

expectations given the accuracy of the ADC and DAC. This ADC monitoring mode is shown in Figure 6.By default, the DAC updates the DAC-configured ports sequentially. However, users can configure the DAC so that its sequence can jump to update the port that just received new data to convert. After having updated this port, the DAC continues its default sequence from that port. In that mode, users should allow a minimum of 80µs between DAC data register updates for subsequent jump operations.In addition to port-specific DAC data registers, the host can also use the same data for all DAC-related ports using one of two preset DAC data registers. All DAC output drivers are protected by overcurrent limit circuitry. In case of overcurrent, the MAX11301 generates an interrupt. Detailed status registers are offered to the host to determine which ports are current limited.

ADC I2CSERIAL INTERFACE

PORT

12 BITSUP TO 400ksps

SCALING BLOCK

REFERENCE MUX

ADC_INT_REF ADC_EXT_REF

INT

SEQUENCER

CNVT

DIGITAL CORE


ANY PORT

12 BITSUP TO 400ksps

SCALING BLOCK

REFERENCE MUX

ANY OTHER PORT

SCALING BLOCK

SEQUENCER


INT

CNVT

DIGITAL CORE



Figure 2. ADC with Single-Ended Input

Figure 3. ADC with Differential Inputs

General-Purpose Input and OutputEach PIXI port can be configured as a GPI or a GPO. The GPI threshold is adjusted by setting the DAC data register of that GPI port to the corresponding voltage. If the DAC data register is set at 0x0FFF, the GPI threshold is the DAC reference voltage. The amplitude of the input signal must be contained within 0V to VAVDD. The GPI-configured port can be set to detect rising edges, falling edges, either rising or falling edges, or none.When a port is configured as GPO (Figure 8), the ampli-tude of its logic-one level is set by its DAC data register. If

the DAC data register is set at 0x0FFF, the GPO logic-one level is four times the DAC reference voltage. The logic-zero level is always 0V. The host can set the logic state of GPO-configured ports through the corresponding GPO data registers.

Unidirectional and Bidirectional Level Translator OperationsBy combining GPI- and GPO-configured ports, unidirec-tional level translator paths can be formed. The signaling at the input of the path can be different from the signaling at the end (Figure 9). For example, a unidirectional path


ANY PORT

SCALING BLOCK

REFERENCE MUX

ANY OTHER PORT

SCALING BLOCK

SEQUENCER

DAC

DAC_REFINTERNAL OR

EXTERNAL FOR ALL PORTS

SCALING BLOCK

SEQUENCER


INT

CNVT

DIGITAL CORE

I2CSERIAL INTERFACE

DIGITAL CORE

SEQUENCER

SCALING BLOCK

PORT

40µs to ±1 LSB

DAC_REFINTERNAL OR

EXTERNAL FOR ALL PORTS

DAC

0mA → 25mACURRENT LIMIT at

50mA

INT



Figure 4. ADC with Pseudo-Differential Input Set by DAC

Figure 5. DAC Configuration

could convert a signal from 1.8V logic level to 3.3V logic level. The unidirectional path configuration allows for the trans-mission of signals received on a GPI-configured port to one or more GPO-configured ports.Pairs of adjacent PIXI ports can also form bidirectional level translator paths that are targeted to operate with open-drain drivers (Figure 10). When used as a bidi-rectional level translator, the pair of PIXI ports must be accompanied with external pullup resistors to meet proper logic levels.

Internally or Externally Controlled Analog Switch OperationTwo adjacent PIXI ports can form a 60Ω analog switch that is controlled by two different configurations. In one configuration, the switch is dynamically controlled by any other GPI-configured PIXI port, as illustrated in Figure 11. The signal applied to that GPI-configured port can be inverted. In the other configuration, the switch is programmed to be permanently “ON” by configuring the corresponding PIXI

port. To turn the switch “OFF”, the host must set that PIXI port in high-impedance configuration.

Power-Supply Brownout DetectionThe MAX11301 features a brownout detection circuit that monitors AVDDIO and AVDD pins. When AVDDIO goes below approximately 4.0V, an interrupt is registered, and the interrupt port is asserted if not masked. When AVDD goes below approximately 4.0V, the device resets.

I2C OperationsThe MAX11301 serial interface is compatible with the I2C Fast Mode (SCL at 400kHz). The MAX11301 has a configurable 7-bit slave address. The first four bits of all MAX11301 slave addresses are always 0111. Slave address bits A2, A1, and A0 are shown in Table 1. The AD0 and AD1 inputs are connected to any of three signals: DGND, DVDD, SDA, or SCL giving eight possible slave addresses, and allowing up to eight MAX11301 devices to share the bus. Basic write and read transactions are structured as shown in Table 2 and Table 3, respectively. For write transac-tions, the targeted register content is modified only after

I2CSERIAL INTERFACE

DIGITAL CORE

SEQUENCER

SCALING BLOCK

PORT

ADC

REFERENCE MUX

SCALING BLOCK

SEQUENCER

DAC_REFINTERNAL OR EXTERNAL

FOR ALL PORTS

ADC_INT_REF DAC_REF

DAC

INT

CNVT



Figure 6. DAC Configuration with ADC Monitoring

Table 1. MAX11301 Slave Addresses

Table 2. Single Register I2C Write Transaction Format

Table 3. Single Register I2C Read Transaction Format

PIN AD1 PIN AD0SLAVE ADDRESS

A6 A5 A4 A3 A2 A1 A0DGND DGND 0 1 1 1 0 0 0DGND SDA 0 1 1 1 0 0 1DGND SCL 0 1 1 1 0 1 0DGND DVDD 0 1 1 1 0 1 1DVDD DGND 0 1 1 1 1 0 0DVDD SDA 0 1 1 1 1 0 1DVDD SCL 0 1 1 1 1 1 0DVDD DVDD 0 1 1 1 1 1 1

B7 B6 B5 B4 B3 B2 B1 B0 N/ACKSTART1st byte 7-Bit Slave Address[6:0] R/WB ACK2nd byte 0 Address[6:0] ACK3rd byte Data[15:8] ACK4th byte Data[7:0] ACKSTOP

B7 B6 B5 B4 B3 B2 B1 B0 N/ACKSTART1st byte 7-Bit Slave Address[6:0] R/WB ACK2nd byte 0 Address[6:0] ACKRESTART1st byte 7-Bit Slave Address[6:0] R/WB ACK3rd byte Data[15:8] ACK4th byte Data[7:0] NACK (from host)STOP



Table 4. Multiple Register I2C Write Transaction Format

Table 5. Multiple Register I2C Read Transaction Format

B7 B6 B5 B4 B3 B2 B1 B0 N/ACKSTART1st byte 7-Bit Slave Address[6:0] R/WB ACK2nd byte 0 Address_N[6:0] ACK3rd byte Data_N[15:8] ACK4th byte Data_N[7:0] ACK5th byte Data_N+1[15:8] ACK6th byte Data_N+1[7:0] ACK7th byte Data_N+2[15:8] ACK8th byte Data_N+2[7:0] ACK9th byte Data_N+3[15:8] ACK10th byte Data_N+3[7:0] ACK11th byte ACK… …41st byte Data_N+19[15:8] ACK42nd byte Data_N+19[7:0] ACKSTOP

B7 B6 B5 B4 B3 B2 B1 B0 N/ACKSTART1st byte 7-Bit Slave Address[6:0] R/WB ACK2nd byte 0 Address_N[6:0] ACKRESTART1st byte 7-Bit Slave Address[6:0] R/WB ACK3rd byte Data_N[15:8] ACK4th byte Data_N[7:0] ACK5th byte Data_N+1[7:0] ACK6th byte Data_N+1[15:8] ACK7th byte Data_N+1[7:0] ACK8th byte Data_N+2[15:8] ACK9th byte Data_N+2[7:0] ACK10th byte Data_N+3[15:8] ACK11th byte Data_N+3[7:0] ACK… …41st byte Data_N+19[15:8] ACK

42nd byte Data_N+19[7:0] NACK (from host)

STOP



the third byte has been fully received. A burst transaction would simply be the extension of the single register trans-action, where the address is automatically incremented from one data word to the next (Table 4 and Table 5). Each time a new data sample is read or written, the register address is incremented by one until it reaches the last register address. The RESTART shown in Tables 3 and 5 could be replaced by a STOP followed by a START.

If a transaction targets an unused address, nothing is written within the MAX11301 for write transactions, and all zeros are read back for read transactions. Similarly, if a write transaction targets a read-only register, nothing is written to the device.

DAC

I2CSERIAL INTERFACEPORT GPI

±30mV HYSTERESIS

SEQUENCER

DAC_REF INTERNAL OR EXTERNAL FOR ALL PORTS

DIGITAL CORE

INT

I2CSERIAL INTERFACE

GPO

SCALING BLOCK

DAC

DIGITAL CORE

PORT

CURRENT LIMIT at 50mA

SEQUENCER


INT



Figure 7. GPI Mode

Figure 8. GPO Mode

Burst Transaction Address Incrementing ModesWith a burst transaction, the address of the initial register is entered once. The data of the targeted register can then be written or read. If the serial clock keeps running with-out issuing RESTART, the device increments the address pointer and writes or reads the next data after the next two bytes. This scheme goes on until the host produces a NACK (read transactions) or a STOP (write transactions). There are two address incrementing modes. In one mode, the address is simply incremented by one (default mode), while in the other, the address is incremented contextu-

ally. When writing DAC data registers in a burst fashion using contextual addressing, the host would write the address of the first port that is DAC-configured (starting from the lowest port index). As long as the host does not issue a STOP and another two bytes are received, the next DAC-configured port is written. This scheme contin-ues until the last DAC-configured port is reached. At that point, any additional serial clock cycle results in looping back to the first DAC-configured port. The contextual addressing scheme is only valid for writ-ing DAC data registers, as described above, and reading ADC data registers.

GPO

SCALING BLOCK

ANY OTHER PORTGPI

ANY PORT

SEQUENCER SEQUENCER

I2CSERIAL INTERFACE

DIGITAL CORE

DAC DAC


INT

LOGICCONTROLLER

CHIP1 WITH VDD1 LOGIC LEVEL

VDD1

PORT[i] PORT[i+1]

VDD2

LOGICCONTROLLER

CHIP2 WITH VDD2 LOGIC LEVEL

MAX11301



Figure 9. Unidirectional Level Translator Path Mode

Figure 10. Bidirectional Level Translation Application Diagram

Interrupt OperationsThe MAX11301 issues interrupts to alert the host of vari-ous events. All events are recorded by the interrupt reg-ister. The assertion of an interrupt register bit results in the assertion of the interrupt port (INT) if that interrupt bit is not masked. By default, all interrupts are masked upon power-up or reset. The interrupts are listed hereafter.The ADCFLAG (ADC Flag) interrupt indicates that the ADC just completed a conversion or set of conversions. It is asserted either at the end of a conversion when the ADC is in single-conversion mode or at the end of a sweep when the ADC is either in single-sweep mode or continuous-sweep mode. ADCFLAG is cleared when the interrupt register is read.The ADCDR (ADC Data Ready) interrupt is asserted when at least one ADC data register is refreshed. Since one conversion per ADC-configured port is performed per sweep, many sweeps may be required before refresh-ing the data register of a given ADC-configured port that utilizes the averaging function. (See the ADC Averaging Function section) To determine which ADC-configured port received a new data sample, the host must read the ADC status registers. ADCDR is cleared after the interrupt register and both ADC status registers are read subsequently.The ADCDM (ADC Data Missed) interrupt is asserted when any ADC data register is not read by the host before new data is stored in that ADC data register. ADCDM is cleared after the interrupt register is read.The GPIER (GPI Event Received) interrupt indicates that an event has been received on one of the GPI-configured ports. Each GPI port can be configured to generate an interrupt for an event such as detecting a rising edge, a falling edge, or either edge at the corresponding port. If the GPI port is configured to detect no edge, it is equiva-lent to masking the interrupt related to that port. A GPI sta-tus register allows the host to identify which port detected the event. GPIER is cleared after the interrupt register and both GPI status registers are read subsequently. The GPIEM (GPI Event Missed) interrupt informs the host that it did not service the GPI interrupt caused by the

occurrence of an event recorded by GPI status registers before another event was received on the same port. The host must read the interrupt register and the GPI status registers whenever a GPI event received interrupt occurs; otherwise, the GPIEM register is asserted upon receiving the next event. This interrupt must be used in conjunction with the GPIER interrupt bit to operate properly. GPIEM is cleared after the interrupt register and both GPI status registers are read subsequently. The DACOI (DAC Overcurrent) interrupt indicates that a DAC-configured port current exceeded approximately 50mA. This limit is not configurable. A DAC overcurrent status register allows the host to identify which DAC-configured port exceeded the 50mA current limit. DACOI is cleared after the interrupt register is read, and both DAC overcurrent status registers are read subsequently.The TMPINT[2:0] (Internal Temperature Monitor) inter-rupt has three sources of interrupt, each independently controllable: a new internal temperature data is ready, the internal temperature value exceeds the maximum limit, or the internal temperature value is below the minimum limit. TMPINT is cleared after the interrupt register is read.The TMPEXT1[2:0] (1st External Temperature Monitor) interrupt has three sources of interrupt, each indepen-dently controllable: a new first external temperature data is ready, the first external temperature value exceeds the maximum limit, or the first external temperature value is below the minimum limit. TMPEXT1 is cleared after the interrupt register is read.The TMPEXT2[2:0] (2nd External Temperature Monitor) interrupt has three sources of interrupt, each indepen-dently controllable: a new second external temperature data is ready, the second external temperature value exceeds the maximum limit, or the second external tem-perature value is below the minimum limit. TMPEXT2 is cleared after the interrupt register is read.The VMON (High-Voltage Supply Monitor) Supply Voltage Failure) interrupt is triggered when AVDDIO supply voltage falls below 4V, approximately. VMON is cleared after the interrupt register is read.

GPI ANY OTHER PORT

PIXI PORT[i+1]PIXI PORT[i]



Figure 11. PIXI Ports as a Controllable Analog Switch

Temperature Sensors OverviewThe MAX11301 integrates one internal and two external temperature sensors. The external sensors are diode-connected transistors, typically a low-cost, easily mount-ed 2N3904 NPN type, that replace conventional thermis-tors or thermocouples. The external sensors’ accuracy is typically ±1°C over the -40°C to +150°C temperature range with no calibration necessary. Use of a transistor with a different ideality factor produces a proportionate dif-ference in the absolute measured temperature. Parasitic series resistance results in a temperature reading error of about 0.25°C per Ohm of resistance. The MAX11301 features a series resistance cancellation mode (RS_CANCEL) that eliminates this error for resistances up

to 10Ω. The external sensors can also measure the die temperature of other ICs, such as microprocessors, that contain a substrate-connected diode available for temperature-sensing purposes. Temperature data can be read from the temperature data registers. The tempera-ture data format is in two’s complement, with one LSB representing 0.125°C.



Tabl

e 6.

Reg

iste

r Tab

le (R

ead/

Writ

e)

Reg

iste

r Des

crip

tion

Reg

iste

r bits

that

are

sho

wn

unus

ed d

o no

t im

pact

dev

ice

func

tiona

lity

and

read

out

as

“0”.

AD

DR

ESS

DES

CR

IPTI

ON

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

DEF

AU

LT0x

00 (R

)D

evic

e ID

DEV

ID[1

5:0]

0x14

24

0x01

(R)

Inte

rrupt

VM

ON

TMP

EX

T2[2

:0]

TMP

EX

T1[2

:0]

TMP

INT[

2:0]

DA

CO

IG

PID

MG

PID

RA

DC

DM

AD

CD

RA

DC

FLA

G0x

0000

0x02

(R)

ADC

dat

a st

atus

; po

rts 0

-15

AD

CS

T[15

:0]

0x00

00

0x03

(R)

ADC

dat

a st

atus

; po

rts 1

6-19

UN

USE

DA

DC

ST[

19:1

6]0x

0000

0x04

(R)

Ove

rcur

rent

st

atus

; por

ts

0-15

DA

CO

IST[

15:0

]0x

0000

0x05

(R)

Ove

rcur

rent

st

atus

; por

ts

16-1

9U

NU

SED

DA

CO

IST[

19:1

6]0x

0000

0x06

(R)

GPI

sta

tus;

por

ts

0-15

GP

IST[

15:0

]0x

0000

0x07

(R)

GPI

sta

tus;

por

ts

16-1

9U

NU

SED

GP

IST[

19:1

6]0x

0000

0x08

(R)

Inte

rnal

te

mpe

ratu

re d

ata

UN

USE

DTM

PIN

TDAT

[11:

0]0x

0000

0x09

(R)

1st e

xter

nal

tem

pera

ture

dat

aU

NU

SED

TMP

EX

T1D

AT[1

1:0]

0x00

00

0x0A

(R)

2nd e

xter

nal

tem

pera

ture

dat

aU

NU

SED

TMP

EX

T2D

AT[1

1:0]

0x00

00

0x0B

(R)

GPI

dat

a; p

orts

15

-0G

PID

AT[1

5:0]

0x00

00

0x0C

(R)

GPI

dat

a; p

orts

19

-16

UN

USE

DG

PID

AT[1

9:16

]0x

0000

0x0D

(R/W

)G

PO d

ata;

por

ts

15-0

GP

OD

AT[1

5:0]

0x00

00

0x0E

(R/W

)G

PO d

ata;

por

ts

19-1

6U

NU

SED

GP

OD

AT[1

9:16

]0x

0000

0x10

(R/W

)D

evic

e co

ntro

l R

eset

BRST

LPEN

RS_C

ANCE

LTM

PPER

TmPC

TL[2

:0]

THSH

DN

DAC

REF

ADC

conv

[1:0

]D

ACC

tL[1

:0]

ADC

CTL

[1:0

]0x

0000

0x11

(R/W

)In

terru

pt m

ask

VM

ON

MS

KTM

PE

XT2

MS

K[2

:0]

TMP

EX

T1M

SK

[2:0

]TM

PIN

TM

SK

[2:0

]D

AC

OI

MS

KG

PID

MM

SK

GP

IDR

MS

KA

DC

DM

MS

KA

DC

DR

MS

KA

DC

FLA

GM

SK

0xFF

FF

0x12

(R/W

)G

PI IR

Q m

ode;

po

rts 0

–7G

PIM

D_7

[1:0

]G

PIM

D_6

[1:0

]G

PIM

D_5

[1:0

]G

PIM

D_4

[1:0

]G

PIM

D_3

[1:0

]G

PIM

D_2

[1:0

]G

PIM

D_1

[1:0

]G

PIM

D_0

[1:0

]0x

0000

0x13

(R/W

)G

PI IR

Q m

ode;

po

rts 8

–15

GP

IMD

_15[

1:0]

GP

IMD

_14[

1:0]

GP

IMD

_13[

1:0]

GP

IMD

_12[

1:0]

GP

IMD

_11[

1:0]

GP

IMD

_10[

1:0]

GP

IMD

_9[1

:0]

GP

IMD

_8[1

:0]

0x00

00

0x14

(R/W

)G

PI IR

Q m

ode;

po

rts 1

6–19

UN

USE

DG

PIM

D_1

9[1:

0]G

PIM

D_1

8[1:

0]G

PIM

D_1

7[1:

0]G

PIM

D_1

6[1:

0]0x

0000

0x16

(R/W

)D

AC p

rese

t da

ta #

1 U

NU

SED

DA

CP

RS

TDAT

1[11

:0]

0x00

00

0x17

(R/W

) D

AC p

rese

t da

ta #

2 U

NU

SED

DA

CP

RS

TDAT

2[11

:0]

0x00

00

0x18

(R/W

)Te

mpe

ratu

re

mon

itor

Con

figur

atio

n U

NU

SED

TMP

EX

T2M

ON

CFG

[1

:0]

TMP

EX

T1M

ON

CFG

[1

:0]

TMP

INTM

ON

CFG

[1

:0]

0x00

00

0x19

(R/W

)In

tern

al

tem

pera

ture

hig

h th

resh

old

UN

USE

DTM

PIN

THI[1

1:0]

0x07

FF



Tabl

e 6.

Reg

iste

r Tab

le (c

ontin

ued)

AD

DR

ESS

DES

CR

IPTI

ON

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

DEF

AU

LT

0x1A

(R/W

)In

tern

al

tem

pera

ture

low

th

resh

old

UN

USE

DTM

PIN

TLO

[11:

0]0x

0800

0x1B

(R/W

)1s

t ext

erna

l te

mpe

ratu

re h

igh

thre

shol

d U

NU

SED

TMP

EX

T1H

I[11:

0]0x

07FF

0x1C

(R/W

)1s

t ext

erna

l te

mpe

ratu

re lo

w

thre

shol

d U

NU

SED

TMP

EX

T1LO

[11:

0]0x

0800

0x1D

(R/W

)2n

d ext

erna

l te

mpe

ratu

re h

igh

thre

shol

d U

NU

SED

TMP

EX

T2H

I[11:

0]0x

07FF

0x1E

(R/W

)2n

d ext

erna

l te

mpe

ratu

re lo

w

thre

shol

d U

NU

SED

TMP

EX

T2LO

[11:

0]0x

0800

0x20

(R/W

)Po

rt 0

confi

gura

tion

FUN

CID

_0[3

:0]

FUN

CP

RM

_0[1

1:0]

0x00

00

0x21

(R/W

)Po

rt 1

confi

gura

tion

FUN

CID

_1[3

:0]

FUN

CP

RM

_1[1

1:0]

0x00

00

0x22

(R/W

)Po

rt 2

confi

gura

tion

FUN

CID

_2[3

:0]

FUN

CP

RM

_2[1

1:0]

0x00

00

0x23

(R/W

)Po

rt 3

confi

gura

tion

FUN

CID

_3[3

:0]

FUN

CP

RM

_3[1

1:0]

0x00

00

0x24

(R/W

)Po

rt 4

confi

gura

tion

FUN

CID

_4[3

:0]

FUN

CP

RM

_4[1

1:0]

0x00

00

0x25

(R/W

)Po

rt 5

confi

gura

tion

FUN

CID

_5[3

:0]

FUN

CP

RM

_5[1

1:0]

0x00

00

0x26

(R/W

)Po

rt 6

confi

gura

tion

FUN

CID

_6[3

:0]

FUN

CP

RM

_6[1

1:0]

0x00

00

0x27

(R/W

)Po

rt 7

confi

gura

tion

FUN

CID

_7[3

:0]

FUN

CP

RM

_7[1

1:0]

0x00

00

0x28

(R/W

)Po

rt 8

confi

gura

tion

FUN

CID

_8[3

:0]

FUN

CP

RM

_8[1

1:0]

0x00

00

0x29

(R/W

)Po

rt 9

confi

gura

tion

FUN

CID

_9[3

:0]

FUN

CP

RM

_9[1

1:0]

0x00

00

0x2A

(R/W

)Po

rt 10

co

nfigu

ratio

n FU

NC

ID_1

0[3:

0]FU

NC

PR

M_1

0[11

:0]

0x00

00

0x2B

(R/W

)Po

rt 11

co

nfigu

ratio

n FU

NC

ID_1

1[3:

0]FU

NC

PR

M_1

1[11

:0]

0x00

00

0x2C

(R/W

)Po

rt 12

co

nfigu

ratio

n FU

NC

ID_1

2[3:

0]FU

NC

PR

M_1

2[11

:0]

0x00

00

0x2D

(R/W

)Po

rt 13

co

nfigu

ratio

n FU

NC

ID_1

3[3:

0]FU

NC

PR

M_1

3[11

:0]

0x00

00

0x2E

(R/W

)Po

rt 14

co

nfigu

ratio

n FU

NC

ID_1

4[3:

0]FU

NC

PR

M_1

4[11

:0]

0x00

00

0x2F

(R/W

)Po

rt 15

co

nfigu

ratio

n FU

NC

ID_1

5[3:

0]FU

NC

PR

M_1

5[11

:0]

0x00

00

0x30

(R/W

)Po

rt 16

co

nfigu

ratio

n FU

NC

ID_1

6[3:

0]FU

NC

PR

M_1

6[11

:0]

0x00

00

0x31

(R/W

)Po

rt 17

co

nfigu

ratio

n FU

NC

ID_1

7[3:

0]FU

NC

PR

M_1

7[11

:0]

0x00

00

0x32

(R/W

)Po

rt 18

co

nfigu

ratio

n FU

NC

ID_1

8[3:

0]FU

NC

PR

M_1

8[11

:0]

0x00

00



Tabl

e 6.

Reg

iste

r Tab

le (c

ontin

ued)

AD

DR

ESS

DES

CR

IPTI

ON

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

DEF

AU

LT

0x33

(R/W

)Po

rt 19

co

nfigu

ratio

n FU

NC

ID_1

9[3:

0]FU

NC

PR

M_1

9[11

:0]

0x00

00

0x40

(R)

Port

0 AD

C d

ata

UN

USE

DA

DC

DAT

_0[1

1:0]

0x00

00

0x41

(R)

Port

1 AD

C d

ata

UN

USE

DA

DC

DAT

_1[1

1:0]

0x00

00

0x42

(R)

Port

2 AD

C d

ata

UN

USE

DA

DC

DAT

_2[1

1:0]

0x00

00

0x43

(R)

Port

3 AD

C d

ata

UN

USE

DA

DC

DAT

_3[1

1:0]

0x00

00

0x44

(R)

Port

4 AD

C d

ata

UN

USE

DA

DC

DAT

_4[1

1:0]

0x00

00

0x45

(R)

Port

5 AD

C d

ata

UN

USE

DA

DC

DAT

_5[1

1:0]

0x00

00

0x46

(R)

Port

6 AD

C d

ata

UN

USE

DA

DC

DAT

_6[1

1:0]

0x00

00

0x47

(R)

Port

7 AD

C d

ata

UN

USE

DA

DC

DAT

_7[1

1:0]

0x00

00

0x48

(R)

Port

8 AD

C d

ata

UN

USE

DA

DC

DAT

_8[1

1:0]

0x00

00

0x49

(R)

Port

9 AD

C d

ata

UN

USE

DA

DC

DAT

_9[1

1:0]

0x00

00

0x4A

(R)

Port

10 A

DC

dat

a U

NU

SED

AD

CD

AT_1

0[11

:0]

0x00

00

0x4B

(R)

Port

11 A

DC

dat

a U

NU

SED

AD

CD

AT_1

1[11

:0]

0x00

00

0x4C

(R)

Port

12 A

DC

dat

a U

NU

SED

AD

CD

AT_1

2[11

:0]

0x00

00

0x4D

(R)

Port

13 A

DC

dat

a U

NU

SED

AD

CD

AT_1

3[11

:0]

0x00

00

0x4E

(R)

Port

14 A

DC

dat

a U

NU

SED

AD

CD

AT_1

4[11

:0]

0x00

00

0x4F

(R)

Port

15 A

DC

dat

a U

NU

SED

AD

CD

AT_1

5[11

:0]

0x00

00

0x50

(R)

Port

16 A

DC

dat

a U

NU

SED

AD

CD

AT_1

6[11

:0]

0x00

00

0x51

(R)

Port

17 A

DC

dat

a U

NU

SED

AD

CD

AT_1

7[11

:0]

0x00

00

0x52

(R)

Port

18 A

DC

dat

a U

NU

SED

AD

CD

AT_1

8[11

:0]

0x00

00

0x53

(R)

Port

19 A

DC

dat

a U

NU

SED

AD

CD

AT_1

9[11

:0]

0x00

00

0x60

(R/W

)Po

rt 0

DAC

dat

a U

NU

SED

DA

CD

AT_0

[11:

0]0x

0000

0x61

(R/W

)Po

rt 1

DAC

dat

a U

NU

SED

DA

CD

AT_1

[11:

0]0x

0000

0x62

(R/W

)Po

rt 2

DAC

dat

a U

NU

SED

DA

CD

AT_2

[11:

0]0x

0000

0x63

(R/W

)Po

rt 3

DAC

dat

a U

NU

SED

DA

CD

AT_3

[11:

0]0x

0000

0x64

(R/W

)Po

rt 4

DAC

dat

a U

NU

SED

DA

CD

AT_4

[11:

0]0x

0000

0x65

(R/W

)Po

rt 5

DAC

dat

a U

NU

SED

DA

CD

AT_5

[11:

0]0x

0000

0x66

(R/W

)Po

rt 6

DAC

dat

a U

NU

SED

DA

CD

AT_6

[11:

0]0x

0000

0x67

(R/W

)Po

rt 7

DAC

dat

a U

NU

SED

DA

CD

AT_7

[11:

0]0x

0000

0x68

(R/W

)Po

rt 8

DAC

dat

a U

NU

SED

DA

CD

AT_8

[11:

0]0x

0000

0x69

(R/W

)Po

rt 9

DAC

dat

a U

NU

SED

DA

CD

AT_9

[11:

0]0x

0000

0x6A

(R/W

)Po

rt 10

DAC

dat

a U

NU

SED

DA

CD

AT_1

0[11

:0]

0x00

00

0x6B

(R/W

)Po

rt 11

DAC

dat

a U

NU

SED

DA

CD

AT_1

1[11

:0]

0x00

00

0x6C

(R/W

)Po

rt 12

DAC

dat

a U

NU

SED

DA

CD

AT_1

2[11

:0]

0x00

00

0x6D

(R/W

)Po

rt 13

DAC

dat

a U

NU

SED

DA

CD

AT_1

3[11

:0]

0x00

00

0x6E

(R/W

)Po

rt 14

DAC

dat

a U

NU

SED

DA

CD

AT_1

4[11

:0]

0x00

00

0x6F

(R/W

)Po

rt 15

DAC

dat

a U

NU

SED

DA

CD

AT_1

5[11

:0]

0x00

00

0x70

(R/W

)Po

rt 16

DAC

dat

a U

NU

SED

DA

CD

AT_1

6[11

:0]

0x00

00

0x71

(R/W

)Po

rt 17

DAC

dat

a U

NU

SED

DA

CD

AT_1

7[11

:0]

0x00

00

0x72

(R/W

)Po

rt 18

DAC

dat

a U

NU

SED

DA

CD

AT_1

8[11

:0]

0x00

00

0x73

(R/W

)Po

rt 19

DAC

dat

a U

NU

SED

DA

CD

AT_1

9[11

:0]

0x00

00



Register Detailed DescriptionDevice ID Register (Read)

Interrupt Register (Read)

BIT FIELD NAME DESCRIPTION

15:0 DEVID[15:0] Device ID0001_0100_0010_0100

BIT FIELD NAME DESCRIPTION0 ADCFLAG ADC flag interrupt

• Asserted when the ADC completes a conversion (ADC set in single-conversion mode) or when the ADC completes a sweep (ADC set in single-sweep or continuous-sweep mode).

• No interrupt is generated when the ADC is in idle mode.• Cleared after the interrupt register is read.

1 ADCDR ADC data ready interrupt• Asserted when any ADC data register receives a new data sample. If a port is configured to

average 2N samples, it takes 2N sweeps for that port data register to be refreshed and assert ADCDR.

• Data registers are refreshed either at the end of a conversion (ADC set in single-conversion mode) or at the end of a sweep (ADC set in single-sweep or continuous-sweep mode).

• Cleared after the interrupt register is read, and after both ADCST[15:0] and ADCST[19:16] registers are read subsequently.

2 ADCDM ADC data missed interrupt• Asserted when the host missed reading a port’s ADC data register by the time that port’s ADC

data register is overwritten by new data.• Cleared after the interrupt register is read.

3 GPIDR GPI event ready interrupt• Asserted when a new event is captured by GPI-configured ports. The type of event is set by the

corresponding GPI IRQ mode register. The host can then consult GPIST[15:0] and GPIST[19:16]registers to identify the port that caused the interrupt.

• Cleared after the interrupt register is read, and after both GPIST[15:0] and GPIST[19:16] are read subsequently.

4 GPIDM GPI event missed interrupt• Asserted when the host missed reading the GPI status register by the time that register is

overwritten.• Must be used in conjunction wit

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