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Clock mechanism in a SDH based NESunil Kumar

ASTE-P (2011 batch)

Introduction

A SDH based Add Drop Multiplexer (aka ADM) has to provide the cross-connection of data for various

ports. To perform the cross connection, data from line cards to cross connect card must be in a common

clock domain. This common clock is derived from one of the recovered clocks resulting in

synchronization of the NE (Network Element) with the SDH network.

SERDES E

lastic

store

Scram

-bler

Backpla

ne

Interface

Lineside

Back

plane

side

Figure: Block Diagram depicting clock domains in a SDH based NE

Description

From line side STM data is received through the SFP module, which converts optical data in to the

electrical form. In SDH protocol, separate clock is not accompanied with the data but is derived from the

data itself using Clock Data Recovery (CDR) module. To get a better quality of clock and to avoid

complete failure of the CDR, there should not be continuous 0s or 1s in received data. In order to

guarantee sufficient transitions in outgoing data, SDH employs a scrambler.

All the data except first row of section overhead (i.e. framing bytes) is scrambled.

Scrambler used in SDH is a 7 bit self-synchronizing one: X7+ X

6+ 1.

The recovered 8 KHzclocks from all the STM ports in the NE are given to a Timing Source Selector (TSS)

present on a control card. TSS selects one of these 8 KHz as an input to the PLL (Zarlink device), this

clock selection is done as per the nomination in GUI. The PLL then generates a system clock; its output

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rate can be set depending upon the requirement. Zarlink device has the following three modes of

operation:-

Free Run mode:free running clock.

Normal mode: provides an output signal which is frequency and phase locked to the selected

input reference signal.

Hold over mode: In case there is a failure of the nominated clock, for next 24 hrs PLL will

provide a frequency equal to the frequency that PLL was generating in Normal Mode. Still if the

nominated clock is not restored within a fixed time, PLL will enter in Free Run mode.

SERDESmodule performs the serialization/de-serialization, bit alignment and word alignment over the

received data.

In the Line card there is an Over Head Termination (OHT) module, which performs the frame recovery,

insertion/extraction of overhead bytes etc. This module also has an elastic store. The functionality of

the elastic store (an Asynchronous-FIFO) is to move the data across the different clock domains without

any data loss. The input side of the elastic store runs at line clock and the output side runs at the systemclock.

This is how data (in system clock domain) from OHT (of different line cards) is given to a cross connect

(XC) card.

(The writer has worked for 4.5 years in R&D Department of Tejas Networks Ltd a telecom equipment maker).