clocked synchronous state machine design design a clocked synchronous state machine with two inputs,...
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Clocked Synchronous State Machine Design
•Design a clocked synchronous state machine with two inputs, A and B and a single output Z that is equal to 1 if:
–A has the same value at each of the two previous clock ticks, or–B has been 1 since the last time that the first condition was true.
•Otherwise Z should be 0.
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Clocked Synchronous State Machine Design
• A has the same value at each of the two previous clock ticks, or
• B has been 1 since the last time that the first condition was true.
Output00 01 11 10 Z
Initial State INIT 0
S*
MeaningInput - AB
S
Output00 01 11 10 Z
Initial State INIT A0 A0 A1 A1 0Got a 0 on A A0 0Got a 1 on A A1 0
S*
MeaningInput - AB
S
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Clocked Synchronous State Machine Design
• A has the same value at each of the two previous clock ticks, or
• B has been 1 since the last time that the first condition was true.
• Try:– (A,B) = (0,0),(0,0),(0,1),(0,0)– (A,B) = (0,0),(0,0),(0,1),(1,0)
Output00 01 11 10 Z
Initial State INIT A0 A0 A1 A1 0Got a 0 on A A0 OK OK A1 A1 0Got a 1 on A A1 A0 A0 OK OK 0
Got two equal A OK
S*
MeaningInput - AB
S
Output00 01 11 10 Z
Initial State INIT A0 A0 A1 A1 0Got a 0 on A A0 OK OK A1 A1 0Got a 1 on A A1 A0 A0 OK OK 0
Got two equal A OK ? OK OK ? 1
S*
MeaningInput - AB
S
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Clocked Synchronous State Machine Design
• A has the same value at each of the two previous clock ticks, or
• B has been 1 since the last time that the first condition was true.
• Try the sequence (A,B) = (1,0), (1,0), (1,1), (0,0).
Output00 01 11 10 Z
Initial State INIT A0 A0 A1 A1 0Got a 0 on A A0 OK OK A1 A1 0Got a 1 on A A1 A0 A0 OK OK 0
Two equal, A=0 last OK0 OK0 OK0 OK1 A1 1Two equal, A=1 last OK1 A0 OK0 OK1 OK1 1
S*
MeaningInput - AB
S
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State Minimization
• Equivalence:– For a given input, two states are
equal if their outputs are the same, and their next state is the same or an equivalent one.
Output0 1 Z
A A B 0B C D 0C A D 0D E F 1E A F 1F G F 1G A F 1
S*
Input - XS
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State Assignment• Procedures concerned with
methods for assigning binary values to states in such a way as to reduce the cost of the combinational circuit that drives the flip-flops.
• Methods:– Choose an initial coded state
which the machine can easily be forced to at reset.
– Minimize the number of state variables that change on each transition.
– Maximize the number of state variables that do not change
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State Assignment• Methods:
– Exploit symmetries by assigning state variables differing only in one bit to both states or group of states.
– If there are unused states, then choose the best of the available state-variable combinations to achieve the foregoing goal.
– Decompose the set of state variables into individual bits or fields, with well defined meaning.
– Consider using more than the minimum number of state variables to make decomposed assignments possible.
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State Assignment
• Unused states:– Minimal risk – assumes that it is
possible for the state machine to get into one unused or illegal state.
– Minimal cost – assumes that the state machine will never enter an unused state.
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Designing State Machines Using State Diagrams
• State-diagram design is simpler but it is more prone to errors.– State table is an exhaustive listing
of the next states for each state/input combination. No ambiguity is possible.
– When constructing a state diagram there is no guarantee that the transition expressions written on the arcs leaving a particular state, cover all input combination exactly once.
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Designing State Machines Using State Diagrams
• Design a state machine to control the tail lights of a 1965 Ford Thunderbird. The tail lights are composed of three light on each side which operate for the turns in the manner shown in the picture below.
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Designing State Machines Using State Diagrams
• The state machine has:– Three inputs: left, and right turns,
and hazard.
– Six outputs: LA, LB, LC, RA, RB, and RC.
– Free running clock with frequency equal to the flashing rate.
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Designing State Machines Using State Diagrams
• LA = L1+L2+L3+LR3• LB = L2+L3+LR3• LC = L3+LR3• RA = R1+R2+R3+LR3• RB = R2+R3+LR3• RC = R3+LR3
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Designing State Machines Using State Diagrams
• Mutual exclusion: For each state the logical product of each pair of transition expression on arcs leaving that state is zero.
• All inclusion: For each state the logical sum of the transition expressions on all arcs leaving the state is one.
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Designing State Machines Using State Diagrams
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Designing State Machines Using State Diagrams
• IDLE state of 000.
• Q1 and Q0 are used to count in gray code sequence (IDLE→L1→L2→L3→IDLE) (IDLE→R1→R2→R3→IDLE).
• Q2 identifies LEFT or RIGHT turn.
• HAZ state of 100.
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Designing State Machines Using State Diagrams
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Feedback Sequential Circuits
• Fundamental mode circuits:– Most common example of
feedback sequential circuits.– Inputs are not normally allowed
to change simultaneously.
• Feedback sequential circuits may be Mealy or Moore circuits.
• A circuit with n feedback loops has n binary state variables and 2n states.
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Feedback Sequential Circuits
• Analysis:– Assumes that input changes occur one
at a time to allow enough time between successive changes for the circuit to settle into a internal stable state.
– Break the feedback loops so that the next value stored in each loop can be predicted as a function of the circuit inputs and the current value stored in all loops.
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Feedback Sequential Circuits
• Y* = (C D ) + (C D’ + Y’)’• Y* = C D + C’ Y + D Y
• Q = Y* = C D + C’ Y + D Y• QN = C D’ + Y’
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Feedback Sequential Circuits
• Total state: combination of internal state (value of feedback loop) and input state (current input value) .
• Stable total state: Total state whose next state predicted by the state table is the same as the current internal state.
• Unstable total state: Total state whose next state predicted by the state table is the same as the current internal state.
• Note that Q and QN are outputs, not state variables.
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Feedback Sequential Circuits
• Simultaneous input changes don’t always cause unpredictable behavior.
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Races• A race is said to occur when multiple
internal variables change state as a result of a single input changing state.
• Noncritical race: the final state does not depend on the order in which the state variables change.
• Starting at state 011/00 change CLK to 1.
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Races• Critical race: the final state depends on the
order in which the state variables change.
• State 010/10 has been changed from 000 to 110.
• Try starting at state 011/00 change CLK to 1 and see what state you end up at.
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State Tables and Flow Tables
• Once it has been determined that a transition table does not have any critical races, the state-variable combinations can be named and outputs can be determined to obtain a state/output table.
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State Tables and Flow Tables
• Flow table eliminates:– Rows for unused internal states (states
that are stable for no input combination).– Next state entries for total states that
cannot be reached from a stable total state as the result of a single input change.
• It eliminates multiple hops and show only the ultimate destination of each transition.
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State Tables and Flow Tables
• Assume internal state S0/10.• Change D to 1, then 0.• Change clock to 0.• Change D to 1, then 0.• What happens when clock changes
to 1.
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SSI Latches andFlip-Flops
• PLDs and FPGAs have to a large extent eliminated their use.
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Debouncer• Bouncing – Behavior of mechanical
of switches which causes their contacts to close, and open several times before finally reaching a resting or stable closed state.
• Typically switches bounce for 10 – 20 ms, which is a very long time compared to the switching speeds of logic gates.
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Debouncer• Debouncing – providing a single
signal change or pulse for each switch transition.
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Registers• Collection of two or more D flip-
flops with a common clock input.• Often used to store a collection of
related bits, such as a byte of data.• May also be used to store unrelated
bits of data.
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Registers
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Registers
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PLD
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PLD
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PLD
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PLD
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PLD