cmos comparator

7/31/2019 CMOS COMPARATOR

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TERM PAPER

EEM-511: ANALOG ELECTRONICS

DESIGN

CMOS COMPARATOR

SUBMITTED TO: SUBMITTED BY:

PROF. V.PREM PYARA VIPUL SAXENA

HEAD, IIIrd

B.SC (ENGG.)

DEPT.OF ELECTRICAL ENGINEERING R.NO: 094047

D.E.I S.NO:50


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CMOS Comparator

The comparator is a circuit that compares an analog signal with another analog signal or reference and

outputs a binary signal based on comparison. The concept of binary signal is too ideal for real world

situations, where there is a transition region between the two levels. It is important for the comparator

to pass through this transition region quickly. The comparator is widely used in the process of converting

analog signal to digital signal and in many other processes where signals are to be compared.

Characterization of a Comparator

The figure below shows the circuit symbol for the comparator. The symbol is same as that of an

operational amplifier because a comparator has many characteristics same as that of a high gain

amplifier. A positive voltage applied at the VP will cause the output to go positive while a positive input

VN will cause the output to go negative. The upper and lower voltage limits of the comparator output

are defined as VOH and VON respectively.

The ideal transfer curve of the comparator is shown. The output of the comparator is high when the

input voltage at the non-inverting( positive) pin is more positive than the input voltage at the inverting

(negative) pin and vice-versa. This is an ideal case and is generally not useful for real world situations.


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Static characteristics

The ideal aspect of the model is the way in which the output makes a transition between VOL and VOH.

The output changes state as input changes by V where V approaches zero. This implies a gain of

infinity as shown below

Gain=AV=limV0 VOH VOLV The dc transfer curve of the first order model that is an approximation to a realizable comparator circuit

is shown below. The difference between this and the previous model is the finite gain which can be

expressed as

AV =VOHVOLVIH

VIL

Where VIH and VIL represent the input voltage difference to just saturate the output at its upper and

lower limits, respectively. This input change is called the resolution of the comparator.

Dynamic Characteristics

The dynamic characteristics of a comparator include both the small signal and large signal behavior.

There is a characteristic delay between the input excitation and the output response which is known as

propagation delay time of the comparator. It is very important parameter since it is often the speed

limitation in conversion rate of A/D converter. In CMOS comparator propagation delay time is generallya function of amplitude of the input. A larger input will result in smaller delay. There is an upper limit to

which the input can be increased and a further increase in input will no longer affect the delay. This

mode of operation is called slewing or slew rate. The small signal dynamics are characterized by

frequency response of the comparator. A simple model of this behavior assumes that the differential

voltage gain AV is given as


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AV(s) = 0+1

Where0 is the dc gain and =1/c is the -3dB frequency of the single (dominant) poleapproximation to the frequency response of the comparator.

Open loop comparators

Open-loop, continuous time comparators are an operational amplifier without frequency compensation

to obtain the largest possible bandwidth, hence improving its time response. Since the precise gain and

linearity are of no interest in comparator design, no-compensation does not pose a problem. However,

due to its limited gain-bandwidth product, open-loop comparators are too slow for many applications.

On the other hand, a cascade of open-loop amplifiers usually has a significantly larger gain

bandwidth product than a single-stage amplifier with the same gain. However, since it costs

more area and power consumption, cascading does not give practical advantages for manyapplications.

The comparator shown above is a two stage open loop comparator. It has two poles of interest,

one is the output pole of first stage p1 and the second is the output pole of second stage, p2.

These poles are expressed as

P1= 1

1(2+4) P2= 1

2(6+7)Where C1 is the sum of capacitances connected to the output of first stage and C2is the sum of

capacitances connected to the output of the second stage. The frequency response can be

expressed as

AV=AV0

( sp1+1) sp2+1


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Fully dynamic latched comparators

ResistorDivider Comparator (or Lewis-Gray Comparator)

Since the input transistor M1A/B and M2A/B operate in the triode region and act like voltage

controlled resistors, this comparator is called Resistive Divider Comparator. The advantage of this

comparator is its low power consumption (No DC power consumption) and adjustable

threshold voltage (decision level) which is defined as

Vin(threshold)=(WB/WA)Vref (1)

Where WA=W1A=W2A WB=W1B=W2B Vin=Vin+ -Vin- Vref=Vref+-Vref-

During reset phase (Clk=0V), PMOS reset transistor M9 and M10 charge Outnodes up

to VDD(this makes NMOS transistor M3 and M4 on and the node voltage atVD3,4discharge to

ground) and input transistor M1 and M2 discharge Di nodes to ground while NMOS

transistor M5 and M6 are off. During evaluation phase (Clk=VDD), as both switch transistor

M5 and M6 are on, each node voltage atDi+and Di instantly rises up to the certain values,

which are defined as

VDi+=rds1 on (Vout-)/( rds1 on+ rds3,4 on+ rds5,6 on) (2)

VDi-=rds2 on (Vou+)/( rds2 on+ rds3,4 on+ rds5,6 on) (3)

Then, each Outnode voltage starts to discharge from VDDto ground inversely proportional to

the applied input voltage such a way; Vin+ VDi VGS3 ID3 Vout- VGS4 Vout+ (VGS3).

With positive feedback operation from the back-to-back cross-coupled inverter pairs (M7/M3 and


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M8/M4), one Outnode will discharge to ground and the other Outnode will charge up to VDDagain

and this comparator will finish its comparison. Since the input transistor M1 and M2 are operated

in the linear region during evaluation phase, the transconductance for those transistors are can be

approximately written as

gm1,2=nCox(W1,2/L) Vds1,2

gm3,4=nCox(W3,4/L)( Vgs3,4-Vtn)

The transconductance of transistor M3 and M4 is much larger than that of the input transistor pair;

hence the differential voltage gain built between Di nodes from the input transistor pair is not big

enough to overcome an offset voltage caused from such a small mismatch between transistor M3

and M4 pair. As a result, those transistors are the most critical mismatch pair in this comparator

and needed to be sized big enough to minimize the offset voltage at the cost of the increased power

consumption. Besides, the mismatch between transistor M5 and M6 pair (which is switches and

operated in the linear region) also causes the considerable input-referred offset voltage.

Furthermore, as the common mode voltage Vcom of the input transistor pair increases, the relative

difference between the voltage controlled resistors (rds1,2) becomes smaller at the same amount ofthe input voltage difference Vin and this in turn increases the offset voltage.

It can be concluded that despite its advantages such as zero-static power consumption

and adjustable threshold voltage, since Lewis-Gray comparator shows a high offset voltage

and its high offset voltage dependency on a different common mode voltage Vcom, it is only

suitable for low resolution comparison.

Pre-amplifier Based Latched Comparators

The main advantages of the pre-amplifier based latched comparators are their fast speed and low

input referred latch offset voltage. Typically, pre-amplifier, which consists of one or two stages of an

open-loop comparator, has a gain of 4 - 10 V/V and it can reduce the input referred latch offset

voltage by its gain. For example, if a pre-amplifier has gain of 10 V/V and a latch stage has an offset


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voltage of 50mV, then the input-referred latch offset voltage will be 5 mV. In addition, by using pre-

amplification stage, kickback noise can be considerably reduced (by isolation between the drains of

the differential pair transistors and the regeneration nodes) and meta-stability problem also can be

relaxed. Latched comparators commonly employ one or two clock signals (Clkand Clkb) to

determine the modes of operation: Track Mode (Reset): output is reset and input is tracked,

Latch Mode (Evaluation): output is toggled by using a positive feedback.

During reset phase (Clkb=0V), both complementary outputVout+ and Vout are reset to 0V by reset

(switch) transistor M10 and M11. During evaluation phase (Clkb=VDD), as the reset transistors are

off, the comparison will be performed by a positive feedback from transistor M7 and M9. While this

comparator present low kickback noise, relatively large static power consumption and slow

regeneration due to its limited current operation make it less attractive.

It can be concluded that pre-amplifier based latched comparators, which is a combination of a pre-

amplifier and a latch, offer fast speed and low offset while they still consume static power.

Pull up pre-amplifier

M1 M2Vi+

Vi-

Vo+

Vo-

Pull-up

L

1

mL

m1V

LW

LW

g

gA

:uppulldiodeNMOS

L

1

p

n

mL

m1V

LW

LW

g

gA

:uppulldiodePMOS

Lm1V RgA

:uppullResistor


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NMOS diff. pair loaded with PMOS diodes and resistors High DM gain, low CM gain, good CMRR Simple, no CMFB Gain not well-defined

Songs Preamplifier(Differential mode)

Songs Preamplifier(Common mode)

Vid gm1Vid ro1

ro3 RL

Vod

Vic

gm1Vgs1

2ro5

1

gm3

Voc

Vgs1

Lm1

Lo3o1m1

dm

V

Rg

//R//rrgA

cm m1V

m1 o5 m3

m3 o5

g 1A 1 2g r g

1

2g r


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Chos Comparator

The M1R and M2R added to set the comparator threshold.

Vth=W

RWi . V+R

M2RM1R

Vi+

Vi-

M7 M8M5 M6

M1

Q+

Q-

M2

M9 M10

M4M3

VR-

VR+

thRR

thii

2

thRR

thii

1

VVL

WVV

L

WkG

VV

L

WVV

L

WkG


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REFERENCES

Philip E. Allen and Douglas R. Holberg, CMOS Analog CircuitDesign, 2nd ed. New York, NY: Oxford, 2002.

B. Razavi, Design of Analog CMOS Integrated Circuits,McGraw-Hill,2001.

B. Razavi and B. A. Wooley, Design techniques for high-speedhigh resolution comparators, IEEE J. Solid-State Circuits, vol.27, no. 6, pp. 19161926, Dec. 1992.

The Design of a Two-Stage Comaprator, [Online]. Availablehttp://people.rit.edu/ssm8867/pdf/analogbody.pdf

W. Sansen, Analog Design Essentials, Springer-Verlag, 2006.
http://people.rit.edu/ssm8867/pdf/analogbody.pdfhttp://people.rit.edu/ssm8867/pdf/analogbody.pdfhttp://people.rit.edu/ssm8867/pdf/analogbody.pdf

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