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library ieee; use ieee.std_logic_1164.all; entity top_level_entity is port ( SW: in std_logic_vector (17 downto 0); LEDR: out std_logic_vector (17 downto 0); SRAM_ADDR: out std_logic_vector (19 downto 0); SRAM_DQ: inout std_logic_vector (15 downto 0); SRAM_CE_N: out std_logic; SRAM_OE_N: out std_logic; SRAM_WE_N: out std_logic; SRAM_UB_N: out std_logic; SRAM_LB_N: out std_logic ) ; end top_level_entity; architecture inside_top_level_entity of top_level_entity is signal address: std_logic_vector (1 downto 0); signal data: std_logic_vector (14 downto 0); signal output: std_logic_vector (14 downto 0); signal we: std_logic; begin SRAM_WE_N <= not SW (15); SRAM_CE_N <= '0 '; SRAM_OE_N <= '0 '; SRAM_UB_N <= '0 '; SRAM_LB_N <= '0 '; address <= SW (17 downto 16); SRAM_ADDR (19 downto 2) <= (others => '0 '); SRAM_ADDR (1 downto 0) <= address; data <= SW (14 downto 0) when SW (15) = '1 'else (others =>' Z '); SRAM_DQ (15) <= '0 '; SRAM_DQ (14 downto 0) <= data; output <= SRAM_DQ (14 downto 0); LEDR (14 downto 0) <= output;

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library ieee; use ieee.std_logic_1164.all;

entity top_level_entity is port ( SW: in std_logic_vector (17 downto 0); LEDR: out std_logic_vector (17 downto 0);

SRAM_ADDR: out std_logic_vector (19 downto 0); SRAM_DQ: inout std_logic_vector (15 downto 0); SRAM_CE_N: out std_logic; SRAM_OE_N: out std_logic; SRAM_WE_N: out std_logic; SRAM_UB_N: out std_logic; SRAM_LB_N: out std_logic ) ; end top_level_entity;

architecture inside_top_level_entity of top_level_entity is

signal address: std_logic_vector (1 downto 0); signal data: std_logic_vector (14 downto 0); signal output: std_logic_vector (14 downto 0); signal we: std_logic;

begin

SRAM_WE_N


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