collaborative research on emer ging technologies...

Collaborative research on emerging technologies and designAndrew R. Neureuther1, Juliet Rubinstein1, Marshal Miller1, Kenji Yamazoe2, Eric Chin1,Cooper Levy1, Lynn Wang1, Nuo Xu1, Costas Spanos1, Kun Qian1, Kameshwar Poolla3,

Justin Ghan3, Anand Subramanian3, Tsu-Jae King Liu1, Xin Sun1, Kwangok Jeong4, Puneet Gupta5, Abde Kaqalwalla5, Rani Ghaida5, Tuck-Boon Chan5

1 EECS, UC Berkeley (US); 2 Visiting Industrial Fellow, UC Berkeley from Canon (Japan)3 ME, UC Berkeley (US); 4 ECE, UC San Diego (US); 5 EE, UC Los Angeles (US)

Dept EECS, 231 Cory Hall, University of california, Berkeley, CA, 94720, USPhone: +1-510-504-3972 FAX:+ 1-510-642-2739 e-mail: [email protected]

ABSTRACTTechniques for identifying and mitigating effects of process variation on the electrical performance of integrated circuits are described. These results are from multi-discipline, collaborative university-industry research and emphasize anticipating sources of variation up-stream early in the circuit design phase. The lithography physics research includes design and testing electronic monitors in silicon at 45 nm and fast-CAD tools to identify systematic variations for entirechip layouts. The device research includes the use of a spacer (sidewall transfer) gate fabrication process to suppressrandom variability components. The Design-for-Manufacturing research includes double pattern decomposition in the presence of bimodal CD behavior, process-aware reticle inspection, tool-aware dose trade-off between leakage and speed, the extension of timing analysis methodology to capture across process-window effects and electrical process-window characterization.

Keywords: image, variability, process-window, electrical process-window, process-aware design, mask floorplan,compact timing models

1. INTRODUCTIONAn important resource for enabling semiconductor manufacturing is collaboration between industry technologists anduniversity researchers. Interest from industry can help focus campus science to make fundamental and practicalcontributions to the lives of others. Universities can provide ‘fresh looks’ by ‘fresh talent’ across diverse fields of expertise and apply new instrumentation, physical understanding, mathematics and computer sciences. Universities are well suited for complementing industry with fundamental measurements, physical modeling, novel algorithms, and even new paradigms for managing the complexity of manufacturing.

One example of a multi-disciplinary collaborative program with industry is the Integrated Modeling, Process, And Computation for Technology (IMPACT) program in the State of California1. This program typically involves 20companies supporting 20 students working for 14 faculty on 3 campuses of the University of California. Research historically sponsored by the Semiconductor Research Corporation (SRC) interacts synergistically. It has provided tools such as software for lithography simulation and pattern matching. The IMPACT research has, in turn, developed physical models for a new process-aware EDA concepts in SRC research. The IMPACT program has evolved over 10 years from work on unit process for Lithography, Etch, CMP and Metrology to also include process-aware EDA.Additional joint collaboration with the Berkeley Wireless Research Center and ST Micro has also allowed students to design and test ideas in silicon at 45 nm.

The anticipation of process variation during design stage requires new paradigms for coping with the variation of features and devices before they are physically instantiated. The importance of making the feature exposure-focusprocess window trees overlap was pointed out many years ago by Burn Lin2. Today for DfM the task is basically the same except that DfM must now guarantee that each set of circuit linked features and their layout contexts will combine to produce overlapped timing windows before they are physically instantiated. To compensate for process effects Optical Proximity Correction (OPC) can be applied but only after an initial layout has been made. Thus, new paradigms are needed that move consideration of process issues higher up into the design flow. Recent strategies attempt to reduce the level of variation such as the introduction of regularity in design rules3 and the use of only pre-characterized regular layouts4. But even with these strategies designers need more informative guidance on likely electrical variations both

Photomask and Next-Generation Lithography Mask Technology XVIII, edited by Toshio Konishi,Proc. of SPIE Vol. 8081, 80810N · © 2011 SPIE · CCC code: 0277-786X/11/$18 · doi: 10.1117/12.899394

Proc. of SPIE Vol. 8081 80810N-1

during initial design and during re-spin for production. Anticipating these remaining process-aware challenges during design requires invention of EDA tools that are first-cut accurate and many orders of magnitude faster than either image or circuit simulation.

2. OBSERVATIONS FROM ELECTRONIC TESTINGThrough the Berkeley Wireless Research Center and collaboration with ST Micro Lynn Wang designed 13-stage process-specific ring-oscillators for 5 physical effects at 45nm5. The design consisted of 32 layouts with 12 replications per block and 3 blocks on a 2mm2 area die that was then placed among other die in a scanner field. The design included a scan chain selection of an individual ring-oscillator, a divide by N circuit and an output pad driver for external frequency measurement.

Twenty die were received and the frequency of every one of the 1296 RO on each die was measured6. Figure 1 shows normalized data on typical within die effects. The range of variation within dies for an individual 13-stage RO frequency is 5% and is much larger than the block to block variation within die. The distribution of frequencies for this control RO is Gaussian in shape. When the standard deviation of the normalized RO frequency is plotted versus the inverse of gate area for a variety of width and length devices a nearly straight line is obtained that is consistent with a Pelgrom threshold variation model with slope of 2.3 mV/um7. To explore the source of random noise further each RO on one typical die was measured at 5 combinations of 3 voltages and 3 temperatures. This altered the expected dependence dependence on LER, Tox and channel doping. Principle Component Analysis based on SPICE model sensitivities to these parametersshowed that the range in variation of channel doping as about 6% while the ranges for LER and Tox were at most 1% and perhaps merely noise. The across-wafer variation range in the average for the 36 RO in a typical layout was about 10% and appeared to indicate a10% and appeared to indicate a bull’s eye pattern.

The design of the RO monitors is based on using layout to program various levels of physics-based lateral interactions.The focus and alignment RO monitors induce spillover from adjacent features for poly and corner rounding for active through an H-shaped active region as shown in Figure 2. These layouts met design rules but at the last minute were required to be OPC’ed and were only about half as sensitive afterward. The measured sensitivity to alignment shown in Figure 2 has the expected parabolic shaped versus 5 steps of programmed misalignment. These parameter-specific‘canary’ like concepts for focus and alignment monitors clearly work and their sensitivities can be improved up to 8 fold with a factor of two each for 1) no-OPC, 2) relaxing from design rules to mask making rules, and 3) adding 90 degree phase-shifting mask features.

The etch structures with regular and single and dual dummy gates showed very little difference. Stress monitors based on changing the active layer length of the source and drain showed a RO increased by 5.3% for a 1.8 x increase in the length of both source and/or drain. An increase in the source dimension as compared to an increase in the drain dimension was 3X more effective. The frequency increase with active width appears to indicate an increase in both the injection velocity as well as the channel mobility8.

Figure 1. The measured normalized RO frequency for 36 RO instantiations for one typical chip, that of Chip 8.

Figure 2. Use of corner rounding with focus on active and programmed gate misalignments to monitor both focus and overlay.


A companion study was carried out by Kun Qian looking at spatial process variation using 45nm ring oscillator arrays and SRAM cell performance9. A hierarchical variability model is introduce to reveal interesting systematic patterns, and in separating them from native random variability. The across-wafer variation is confirmed to be a gentle parabolic effect. A novel statistical compact device modeling procedure is used to extract the systematic and random variation of device parameters across wafer and within die. Statistical SPICE simulation is then performed based on the extracted variation model of device parameters. The results compare well with actual ring oscillator and SRAM measurements, in that the characteristic systematic, spatial and random patterns have been captured for circuit-level simulation.

3. PATTERN MATCHING FAST-CADIn collaborative research we have developed novel techniques for quickly examining layouts to determine their sensitivities to process variations. This includes theoretical concepts, practical approximations, extensions for mask edge effects and ultra-fast clustering algorithms. Juliet Rubinstein answered an interesting conceptual question by expanding the lateral spillover from a point source due to the lens pupil at the wafer image plane as an additive sum of electric fields10,11. In this formulation each lateral spillover term is contributed by the Fourier transform of a separate Zerniketerm in the expansion of the Optical Path Difference (OPD). Hence the spillover due to focus FT[jZ3] is orthogonal tothe spillover due to proximity FT[Z0] and has its biggest effects at entirely different location on a feature as shown in Figure 3. Because a Rayleigh unit of defocus is not a small aberration a quadratic expansion of the OPD is needed and this requires also matching with FT[(jZ3)2] = -FT[1/3Z0+2/3Z8]. Thus only one-third of this second spillover effect can be mitigated by reducing the proximity effect. However, wherever OPC can increase edge slope the impact of an intensity change on edge placement is further reduced. These theoretical results have an important practical impact in double patterning because the focus sensitivity of proposed pattern splits can be assessed real-time by pattern matching with a single complex pattern.

A further practical question is whether a parabolic model is sufficiently accurate to predict through-focus behavior for all possible patterns over a full Rayleigh unit of defocus. Kenji Yamazoe examined this question by expanding the Transmission-Cross-Coefficient and identifying pattern independent and pattern dependent terms12. Four pattern independent terms were identified and then calibrated by using the image of a contact hole. The pattern dependent terms were then determined by using three images at different focus settings (near focus, and 0.7RU defocus in the plus and minus directions). This procedure results in an accuracy better than 1% for all points throughout a diverse test layout containing many features types. This generalized method shows that even in the presence non-0 or 180 mask transmission including mask edge effects even with typical aberrations that through-focus behavior for a 2 Rayleigh unit total focus range settings can be obtained to an accuracy of <1% with only 3 images.

The extension of the Pattern Matching techniques to the environment of the simultaneous presence of electromagnetic mask edge effects, aberrations and off-axis pixilated sources was developed by Marshal Miller13,14. Each of these physical phenomena produces additional lateral spillover of complex phasor electric fields. Each of these contributions

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Figure 4. Intensity change with defocus versus the Pattern Match Factor for positive (red) and negative (blue) defocus levels for a test pattern with EM edge effects with an optimized source for a MoSi SRAM mask and the presence of lens aberrations.

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can be summed together into a single complex lateral spillover function. Further this function and its linear and parabolic behavior with focus can be determined automatically from any simulator that produces the OPD in the pupil. Marshal has also shown that the key to improving accuracy for high off-axis sources is to divide the source points into 7 to 12 localized clusters and incoherently add their images. The high accuracy of this composite approach is illustrated in Figure 4 for an SMO source for a MoSi mask. Here the intensity change from best focus from full image simulation on the vertical axis is plotted against the Pattern Matching Factor (PMF). Including mask edge effects extends the range of intensity changes owing to the tilt through focus produced by out of phase phasor fields generated from the mask edges.The PMF which can be evaluated in 40 �s is a first-cut accurate estimator of these through focus effects. Thus full chip layouts can be checked in tens of minutes, standard cells can be checked for compatibility with SMO sources in seconds, and SMO algorithms can contain real-time cost functions for mask edge EM effects that can be evaluated in �s.

Ultra-fast cluster algorithms can also be used to check designs for problematic layouts as developed by Justin Ghan15.Here clusters involving many layouts are efficiently identified by first developing an optimal weighting metric that expresses lateral influence. A canonical layout clip is then determined to represent the cluster and there by replace the need for calculating the distance between all pairs of clips. New patterns similar to clusters that print well can be confirmed quickly and new patterns similar to problematic clusters can be tagged for in-depth analysis. This technique is 20X faster if there are few clusters.

4. DEVICES AND DESIGN FOR MANUFACTURINGThe collaborative research also includes exploration of new device concepts and Design-for-Manufacturing. As transistor gate lengths are scaled down, gate line edge roughness (LER) is not reduced commensurately16. At the same time, thermal process budgets are reduced to achieve shallower and more abrupt source/drain junctions, so that the effects of gate LER become increasingly significant. Thus, gate LER will be the dominant source of variability for gate lengths below 25 nm and LER is even expected to be coupled with the manner in which random doping affects devices. Under IMPACT, Xin Sun assessed the benefit of using a spacer (sidewall transfer) gate lithography process to mitigate the effect of LER, via full three-dimensional device simulations17. The simulation results indicate that spacer gate lithography can dramatically reduce LER-induced variation in transistor performance and that variability can be well suppressed with gate-length scaling even if LER does not scale.

There are a number of promising technologies for double patterning and each technology interacts differently with variations in linewidth and alignment. Assessing circuit level performance from the effects of these variations willrequire a chip-level DfM framework for circuit analysis and optimization. One such framework has been developed under IMPACT by Kwangok Jeong18. Mechanisms of space and linewidth variation arising from overlay in various double patterning lithography option are resized and shifted for electrical analysis as depicted in Figure 5. A foundation of both TCAD-based and chiplevel methods, along with an effective design of experiments, was then developed to assess electrical impacts of BEOL variations. An assessment was then made of relative viabilities of DPL technology options under a range of process control scenarios. This methodology can guide technology developers toward DPL technology options that will have least variability impact on circuit performance.

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Figure 5. Framework for assessing BOTL electrical performance variation in double patterning.

Figure 6. Framework for linking design information with mask inspection.


The effect of double patterning on interconnect delay and the possible use of a shift-trim printing strategy have been explored by Rani Ghandi on IMPACT Support19, 20. The effects of overlay errors along typical metal paths were shown to introduce naturally averaging and thus help mitigate variations. A novel shift-trim double patterning approach was also introduced that saves mask costs by utilizing a single critical mask in a nominal and half-period shift position followed by trimming with a less critical trim mask. This significantly reduced overlay and bimodality with straight forward decomposition with area penalty <0.3%.

Linking reticle inspection with design is being investigated by Abde Ali Kagalwalla21. As shown in Figure 6 this includes communicating design-aware concerns to inspection to adjust pixel size and/or sensitivity. Up to 90% of false defects can be reduced to improve defect review overhead and first-pass yield. Work is also proceeding on smart floor planning of EUV reticles in the presence buried defects22. A floorplanning algorithm was developed that takes into account the defect density, the defect size its through-focus impact as well as the number of die. The advantages of shifting and reorienting die shown in Figure 7 indicate that mask yield increased substantially, from around 53% to 94% for a 40-defect mask. Adding design information, which essentially allows assigning different CD tolerances to different shapes, can result in further improvements in mask yield, up to 99%.

The flexibility in today’s lithography tools also provides opportunities for improving circuit performance. For example, as explored by Kwangok Jeong23 the optimization of across-chip dose might be utilized to provide desired trade-offs in speed and power in various areas of a chip. Critical timing paths might be slightly overexposed to gain speed while noncritical paths might be slightly underexposed to reduce leakage and power.

A new methodology for predicting timing errors due systematic process variations in focus, exposure and alignment in the presence of random device effects has been explored by Eric Chin and Cooper Levy24, 25. Systematic focus-exposure simulation of inverter timing in the 45 nm free-PDK kit from North Carolina State26 revealed that the delay versus focus and exposure has a behavior similar to a Bossong like focus-exposure of linewidth. This physics-based Bossong like behavior also occurs for multiple stage circuits and standard-cell layouts of more complicated logic functions as shown in Figure 8. The detailed shape is captured to an accuracy of better than 1% in an additive compact delay model consisting of a 9-term expansion in focus and dose. Off-line pre-characterization can be used to calibrate the compact model coefficients for a given rise-time and capacitive load. This additive compact model is then linked to the timing table cell entry indexed by rise time and capacitive load. By also tagging the netlist with field and wafer position the expected change in timing can then be determined for a given map of across field and across chip process variations.

When examining electrical performance variation, Abde Ali Kagalwalla and Tuck-Boon Chan showed that measuring the lithographic process window purely geometrically can be very pessimistic27. Practical methods to compute electricalprocess window (EPW) were proposed that included delay, static noise margin and power leakage. These methods showed an improvement of 1.5X to 6X in acceptable process window when compared to conventional geometric measures of CD control. They also showed that EPW can be optimized by layout transparent methods like gate length biasing and Vth push during manufacturing.

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Figure 7. Benefits of reticle floorplanning averaged over three 22nm benchmark circuits. The wafer scribe overhead is less than 0.03% in all cases.

Figure 8. Example library cell with its layout, Bossong like timing sensitivity to focus-dose, and sensitivity to alignment.


5. CONCLUSIONA variety of techniques for identifying and mitigating effects of process variation on the electrical performance of integrated circuits have been described. This collaborative university-research is a win-win-win-win for Industry, Students, Faculty and Visiting Industrial Fellows. The research on lithography physics includes electronic monitors and fast-CAD tools to mitigate systematic variations in lithography such as those associated with focus, lens, mask edge effects, and illumination. Access to silicon has provided eye-opening insight for faculty and students into measurement and data analysis challenges quantifying dominant sources of residual variations in electrical performance including thedevelopment of Parameter-Specific Ring-Oscillator monitors. Improvements in theory and practice of through-focus effects have made Pattern Matching suitable for guiding decomposition in double patterning and lithography nonidealities in SMO including electromagnetic edge effects, high off-axis pixels and lens aberrations. Ultra-fast pattern sub-regional classification clustering algorithms can be developed by first developing optimal weighting metrics that expresses lateral influence and then determining canonical layout clips.

The use of spacer defined gates has been shown to suppress random variability in devices. Design for Manufacturing techniques have been described for addressing double pattering coloring, compensation for bimodal CD behavior and reticle non-uniformity and locally programming trade-offs in leakage and speed. Ongoing efforts have shown significant improvements in mask yield by leveraging design intent, even for EUV masks in the presence of defects. A quantitative Bossong curve like model and associated methodology have been developed for predicting path level propagation delay variability during design to an accuracy below 1% without the need for process simulation or circuit simulation. The electrical process window for circuit performance appears to be 1.5 to 6X larger than that predicted from the conventional geometric measures of CD control.

References

[1] IMPACT, Accessed, Mar 2011. http://impact.berkeley.edu/[2] B. J. Lin, “The exposure defocus forest,” Japanese Journal of Applied Physics, 33(12B): 6756-6764, 1994.[3] L. Liebmann, “Layout impact of Resolution Enhancement Techniques: Impediment or opportunity?,” ISPD 2003, Monterey, CA, USA.[4] Tejas Jhaveri, et. al, “Maximization of layout printability/manufacturability by extreme layout regularity,” Journal of Micro/Nanolithography, MEMS and MOEMS, 6(3):031011, 2007.[5] L. T.-N. Wang, L. T.-N. Wang, L.-T. Pang, A. R. Neureuther, and B. Nikolic, “Parameter-Specific Ring Oscillators for quantifying sources of electronic variability,” SPIE 2009[6] Lynn T.-N. Wang, “Design and measurement of Parameter-Specific Ring Oscillators,” Ph.D. Dissertation, University of California, Berkeley, 2010.[7] M.J.M. Pelgrom, A.C.J. Duinmaijer, and A.P.G. Welbers. “Matching properties of MOS Transistors,” Solid-State Circuits, IEEE Journal of, 24(5):1433 - 1439, October 1989.[8] N. Xu, X. Sun, L. Wang, A. Neureuther, T. J. King Liu: SISPAD Tech. Dig. 2009.[9] K. Qian, C. Spanos, and B. Nikolic, “Hierarchical modeling of spatial variability with a 45nm example,” Proc. SPIE 7275, pp. 727505-1- 727505-12, 2009.[10] Juliet Rubinstein and Andrew R. Neureuther, “Post-decomposition assessment of double patterning layouts,”volume 6924, page 69240O. SPIE, 2008.[11] Juliet A. Rubinstein, “Pattern matching for advanced lithographic technologies,” Ph.D. Dissertation, University of California, Berkeley, 2010.[12] Kenji Yamazoe and Andrew R. Neureuther, “Modeling of aerial image through defocus with aberration and imaginary mask effects in lithography simulation,” submitted to Applied Optics.[13] Marshal A. Miller, Kenji Yamazoe, and Andrew R. Neureuther, “Automatic numerical determination of lateral influence functions for fast-cad,” volume 7640, page 764031, SPIE, 2010.[14] Marshal A. Miller, “Mask edge effects in optical lithography and chip level modeling methods,” Ph.D. Dissertation, University of California, Berkeley, 2010.[15] Justin Ghan, “Distance metrics and clustering algorithms for detection and classification of process sensitive patterns,” Ph.D. Dissertation, University of California, Berkeley, 2010.[16] A. Asenov, “Simulation of statistical variability in nano MOSFETs,” Symposium on VLSI Technology Conference Digest, pp. 86-87, 2007.[17] X. Sun and T.-J. King Liu, “Spacer gate lithography for reduced variability due to line edge roughness,” IEEE Transactions on Semiconductor Manufacturing, Vol. 23, No. 2, pp. 311-315, 2010.


[18] Kwangok Jeong et. al, “Assessing chip-level impact of double patterning lithography,” Proc. International Symposium on Quality Electronic Design, Mar. 2010[19] Rani S. Ghaida and Puneet Gupta, “Within-layer overlay impact for design in metal double patterning IEEE Transactions on Semiconductor Manufacturing,” Aug. 2010.[20] Rani S. Ghaida, George Torres, and Puneet Gupta, “Single-mask double-patterning lithography for reduced cost and improved overlay control,” IEEE Transactions on Semiconductor Manufacturing, Nov. 2010.[21] Abde Ali Kagalwalla, Puneet Gupta, Chris Progler and Steve McDonald, “Design-aware mask inspection”,IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2010.[22] A. A. Kagalwalla, P. Gupta, D.-H. Hur, and C.-H. Park, “Defect-aware reticle floorplanning for EUV masks,” in SPIE Advanced Lithography, March 2011.[23] K. Jeong, A. B. Kahng, C.-H. Park and H. Yao, "Dose map and pacement co-optimization for timing yield enhancement and leakage power reduction", Proc. ACM/IEEE Design Automation Conference, 2008, pp. 516-521.[24] Eric Y. Chin, Cooper S. Levy, and Andrew R. Neureuther. “Variability aware timing models at the standard cell level,” volume 7641, page 76410H. SPIE, 2010.[25] Eric Y. Chin, “Compensation for lithography induced process variations during physical design,” Ph.D. Dissertation, University of California, Berkeley, 2010.[26] North Carolina State University. Freepdk45 design kit, http://www.eda.ncsu.edu/ wiki/FreePDK45:Contents. Accessed December 2010.[27] T. Chan, A. Kagalwalla, and P. Gupta, “Measurement and optimization of electrical process window,” SPIE Journal of Micro/Nanolithography, MEMS and MOEMS (JM3), 2011.

Acknowledgements

This research is supported by SRC grant 1443, the UC Discovery Grant ele07-10283 under the IMPACT program, and Intel. Access to student designed silicon chips was provided by ST Micro through a collaboration with the Berkeley Wireless Research Center. Aerial image simulations were performed using Caliber from mentor Graphic, EM-Suite from Panoramic Technology Inc.


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