computer architecture: a quantitative approach - cap4 - section 3
TRANSCRIPT
Multiprocessors and Thread-Level Parallelism
Performance of SSM Multiprocessors
“The overall cache performance is a combination of the behavior of uniprocessor
cache miss traffic and the traffic caused by communication, which results in invalidations
and subsequent cache misses.”
Hennessy and Patterson
True sharing miss X False sharing miss
A Commercial Workload
AlphaServer 4100
300MHz, 3 level caches
3 Benchmarks
Performance of the Commercial Workload
Performance of the Commercial Workload
Performance of the Commercial Workload
Performance of the Commercial Workload
Performance of the Commercial Workload
A Multiprogramming and OS Workload
2 level caches
2 copies of Andrew benchmark
Execution time is broken into 4 components: Idle, User, Synchronization and Kernel
Performance of the Multiprog. And OS Workload
Performance of the Multiprog. And OS Workload
Performance of the Multiprog. And OS Workload
Performance of the Multiprog. And OS Workload
Thank you!
Author: Prof. Sergio Takeo, Marcelo Arbore.
Bibliography: Patterson, D. A.; Hennessy, J. L. Computer Architecture: A quantitative Approach, 4th Ed. Morgan Kaufmann Publishers.
“The overall cache performance is a combination of the behavior of uniprocessor
cache miss traffic and the traffic caused by communication, which results in invalidations
and subsequent cache misses.”
Hennessy and Patterson