computer fundamentals lecture 3 dr robert harle · pdf file · 2013-11-08input...
TRANSCRIPT
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Computer FundamentalsLecture 3
Dr Robert Harle
Michaelmas 2013
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Today's Topics
Motherboards, buses, peripherals
Memory hierarchy
(S)RAM cells
Spinning HDDs
Flash and SSDs
Graphics Cards and GPUs
RISC and CISC architectures
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Our Simple Model So Far
2
Memory
Program &Data
1
CPU
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More on the CPU
Core technology is a transistor
C
E
B
PN N
Ctrl
Oxide
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More on the CPU
Core technology is a transistor
C
E
B
PN N
Ctrl
Oxide
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Transistor Counts
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Transistor Size
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Communications
A useful computer needs peripherals Input (mouse, keyboard, etc) Output (printer, display) Network adapter, etc
Peripherals connect to buses in order to communicate with the core system A bus is just a set of wires that can be used by
multiple peripherals.
Mouse
Printer
Keyboard
Flashdrive
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“Bus” from Power Busbar
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Typical Desktop Architecture
USB
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The Motherboard
An evolution of the circuitry between the CPU and memory to include general purpose buses (and later to integrate some peripherals directly)
Internal Buses ISA, PCI, PCIe, SATA, AGP
External buses USB,Firewire,
eSATA, PC card
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Typical Memories
RegistersCPU Cache Main Memory
System Cache
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Caches
Put frequently-accessed data in a fast cache to speed things up
CacheQuery
Retrieve
Cache hit: it's in the cache (fast)
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Caches
Put frequently-accessed data in a fast cache to speed things up
Cache
Main Memory
Query
Retrieve
Cache miss: get from memory (slower)
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Cache the Cache!
L1
L2
L3
Main Memory
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SRAM
DRAM
Flash
Magnetic
Peripherals
Motherboard
CPU
Memory Hierarchy (Typical)
Registers
CPU cache
Main memory
SD cards, SSDs...
Hard discs, tapes
System cache
Speed Size
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Typical Memory Capacities
Registers Cache RAM SSD HDD
1
10
100
1000
10000
100000
1000000
10000000
Typic
al Siz
es
(MB
– L
OG
SC
ALE! )
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Register Size Limits Memory
Each slot in memory has a unique address
The address must fit inside a register
32 bits → 232 slots 232 bytes → 4 GB (64 bits → 18
quintillion bytes ~ 1019 bytes)
Registers
63
PC
X
Y
Z
ALU
CPU
MAU
2
IB
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Register Size Limits Memory
Each slot in memory has a unique address
The address must fit inside a register
32 bits → 232 slots 232 bytes → 4 GB
Registers
63
PC
X
Y
Z
ALU
CPU
MAU
2
IB
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Register Sizes
Registers are fixed size, super-fast on-chip memory usually made from SRAM.
When we build the CPU we have to decide how big to make them Bigger registers
Allow the CPU to do more per cycle Mean we can have more main RAM (longer
addresses can be supported) Too big and we might never use the whole length
(waste of electronics) Smaller registers
Less electronics (smaller, cooler CPUs) Too small and it takes more cycles to complete
simple operations
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Random Access Memory (DRAM) Capacitor + transistor = memory cell
Capacitor charged → 1, discharged → 0
Matrix of cells → transistors allow us to 'activate' cells
Hence we can randomly jump around in the data (random access)
This is Dynamic RAM (DRAM), cheap and simple
BUT: capacitors leak charge over time, so a “1” becomes a “0”. Therefore we must refresh the capacitor regularly and this slows everything down plus it drains power...
Memory cell(transistor+capacitor)
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Static RAM (SRAM) We can avoid the need to refresh by using Static RAM
(SRAM) cells. These use more electronics (typically 6 transistors per cell) to effectively self-refresh.
This is 8-16x faster than DRAM
But each cell costs more and takes more space so it's also about 8-16x more costly!
And both DRAM and SRAM are volatile (lose power = lose data)
SRAM Memory Cell
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Magnetic Media (Hard Discs)
Lots of tiny magnetic patches on a series of spinning discs
Similar to an old cassette tape only more advanced
Read and write heads move above each disc, reading or writing data as it goes by
Remarkable pieces of engineering that can store terabytes (TB, 1,000,000MB) or more.
Cheap mass storage
Non-volatile (the data's still there when you next turn it on)
But much slower than RAM (→ SAM)
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Flash and SSDs Toshiba came up with Flash memory in the 1980s as a
non-volatile storage without moving parts
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Flash and SSDs Toshiba came up with Flash memory in the 1980s as a
non-volatile storage without moving parts
Floating gate MOSFET
PN N
Oxide
Oxide
Ctrl
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Graphics Cards
Started life as simple Digital to Analogue Convertors (DACs) that took in a digital signal and spat out a voltage that could be used for a cathode ray screen
Have become powerful computing devices of their own, transforming the input signal to provide fast, rich graphics.
Todays GCs are based around GPUs with lots of tiny processors (cores) sharing some memory. The notion is one of SIMD – Single Instruction Multiple Data Every instruction is copied to each core, which
applies it to a different (set of) pixel(s) Thus we get parallel computation → fast Very useful for scientific computing CPUs better for serial tasks
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GPUs and SIMD
So called vector processing: apply one instruction to a vector of data
Add 5 4
2
3
1
4
ALU 1
ALU 2
ALU 3
ALU 4
ALU 5
9
7
8
6
9
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RISC
The simplest way to create a CPU is to have a small number of simple instructions that allow you to do very small unit tasks E.g. load a value to a register, add two
registers If you want more complicated things to
happen (e.g. multiplication) you use just use multiple instructions
This is a RISC approach (Reduced Instruction Set arChitecture) and we see it in the ARM CPUs
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CISC
Actually, two problems emerged People were coding at a low level and got sick
of having to repeatedly write multiple lines for common tasks
Programs were large with all the tiny instructions. But memory was limited...
Obvious soln: add “composite” instructions to the CPU that carry out multiple RISC instructions for us This is a CISC (Complex Instruction Set
arChitecture) and we see it in the Intel chips Instructions can even be variable length
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RISC vs CISC
Every instruction takes one cycle
Smaller, simpler CPUs
Lower power consumption
Fixed length instructions
Multiple cycles per instruction
Smaller programs
Hotter, complex CPUs
Variable length instructions
RISC CISC
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RISC vs CISC
CISC has traditionally dominated (for backwards compatibility and political reasons) e.g. Intel PCs
RISC was the route taken by Acorn, and resulted in the ARM processors e.g. smartphones
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Next Week
The roles of the O/S (kernel, timeslicing)
The notion of threads
Multi-core processors
[Virtual machines]