computer organization department of information technology, · pdf fileoperations computer ......

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University of Pune S.E. I.T. Subject code: 214442 Part 16: Micro-operations Computer Organization UNIT III Tushar B. Kute, Department of Information Technology, Sandip Institute of Technology & Research Centre, Nashik. Micro-operations Instruction cycle is divided into three major phases: Fetch cycle Decode cycle Execute cycle To perform these CPU unit has to perform a set of operations are known as micro- operations.

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Uni

vers

ity o

f Pun

e S.

E. I.

T.

Subj

ect c

ode:

214

442

Part

16:

Mic

ro-o

pera

tions

Com

pute

r Org

aniz

atio

n

UN

IT

III

Tush

ar B

. Kut

e,

Dep

artm

ent o

f Inf

orm

atio

n Te

chno

logy

, Sa

ndip

Inst

itute

of T

echn

olog

y &

Res

earc

h Ce

ntre

, Nas

hik.

Mic

ro-o

pera

tions

Inst

ruct

ion

cycl

e is

divi

ded

into

thre

e m

ajor

ph

ases

: Fe

tch

cycl

e De

code

cyc

le

Exec

ute

cycl

e

To p

erfo

rm th

ese

CPU

uni

t has

to p

erfo

rm a

se

t of o

pera

tions

are

kno

wn

as m

icro

-op

erat

ions

.

Mic

ro-o

pera

tions

Four

cat

egor

ies o

f mic

ro-o

pera

tions

in d

igita

l com

pute

rs:

1. R

egist

er tr

ansf

er m

icro

oper

atio

ns tr

ansf

er b

inar

y in

form

atio

n fr

om o

ne re

gist

er to

ano

ther

. 2.

Arit

hmet

ic m

icro

oper

atio

ns p

erfo

rm a

rithm

etic

ope

ratio

ns o

n nu

mbe

rs st

ored

in re

gist

ers.

3.

Log

ic m

icro

oper

atio

ns p

erfo

rm b

it m

anip

ulat

ion

oper

atio

ns o

n no

n-nu

mer

ic d

ata

stor

ed in

regi

ster

s.

4. S

hift

mic

roop

erat

ions

per

form

shift

ope

ratio

ns o

n co

nten

ts o

f re

gist

ers.

2nd,

3rd

, and

4th

cat

egor

ies c

hang

e th

e co

nten

ts o

f reg

ister

s.

Basic

arit

hmet

ic m

icro

oper

atio

ns:

Addi

tion,

subt

ract

ion,

incr

emen

t,dec

rem

ent,

and

shift

. Ha

rdw

are

impl

emen

tatio

n of

an

arith

met

ic R

TO

1: R1

R

1 +

R2

1: R1

Logi

c M

icro

oper

atio

ns

Exam

ple

T 1 + T

2: R1

R

2 +

R3 ,

R4

R2

V R6

AN

D M

icro

oper

atio

n It

is us

ed fo

r cle

anin

g to

0 a

bit

or a

sele

cted

gro

up o

f bits

in a

re

gist

er.

Exam

ple

R1:

10

1011

01 1

0101

011

R2

:

0000

0000

101

0101

1 R1

R

2 R

2:

0000

0000

101

0101

1

OR

mic

roop

erat

ion

It is

used

to se

t to

1 a

bit o

r a se

lect

ed g

roup

of b

its

in a

regi

ster

. Ex

ampl

e R1

:

10

1011

01 1

0101

011

R2:

1111

1111

000

0000

0 R1

R

1 V

R2:

1111

1111

101

0101

1

Excl

usiv

e O

R (X

OR)

mic

roop

erat

ion

It is

used

to co

mpl

emen

t a b

it or

a g

roup

of b

its in

a

regi

ster

. (

,

)

Ex

ampl

e R1

: 10

1011

01 1

0101

011

R2:

1111

1111

000

0000

0

: 0

1010

010

1010

1011

Shift

mic

roop

erat

ions

Sh

ift m

icro

oper

atio

ns a

re u

sed

for s

eria

l tra

nsfe

r of

data

. The

y ar

e al

so u

sed

in a

rithm

etic

, log

ic a

nd co

ntro

l op

erat

ions

. Lo

gica

l shi

ft a

nd ro

tate

Lo

gica

l shi

ft rig

ht

Logi

cal s

hift

left

Ro

tate

righ

t

Rota

te le

ft

Arith

met

ic sh

ift

An a

rithm

etic

shift

is a

mic

roop

erat

ion

that

shift

s a

signe

d bi

nary

num

ber t

o th

e le

ft or

righ

t. It

mus

t hav

e th

e sig

n bi

t un

chan

ged.

An

arit

hmet

ic sh

ift le

ft m

ultip

lies

a sig

ned

bina

ry n

umbe

r by

2.

An a

rithm

etic

shift

righ

t div

ides

a si

gned

bin

ary

num

ber b

y 2.

Regi

ster

Tra

nsfe

r

Regi

ster

to re

gist

er tr

ansf

er:

For e

ach

regi

ster

Ri,

two

cont

rol s

igna

ls:

Riin

use

d to

load

the

data

on

the

bus i

nto

the

regi

ster

. Ri

out

Exam

ple:

To tr

ansf

er co

nten

ts o

f R1

to R

4:

Set R

1 out

to 1

. Thi

s pla

ces c

onte

nts o

f R1

on th

e bu

s.

Set R

4 in t

o 1.

Thi

s loa

ds d

ata

from

the

proc

esso

r bus

into

R4.

Regi

ster

Tra

nsfe

r (2)

Y

Inte

rnal

pr

oces

sor

bus

Z

MU

X

A

ALU

B

Con

stan

t 4

Sel

ect

Ri

X

Ri in

X

Ri ou

t

Yin

X

X

Zin

Z out

X

Arith

met

ic/L

ogic

Ope

ratio

n

ALU

: Per

form

s ar

ithm

etic

and

logi

c op

erat

ions

on

its A

an

d B

inpu

ts.

To p

erfo

rm

R3

[R1]

+ [R

2]:

1.R1

out,

Y in

2.R2

out,

Sele

ctY,

Add,

Z in

3.Z o

ut, R

3 in

Y

Inte

rnal

pr

oces

sor

bus

Z

MU

X

A

ALU

B

Con

stan

t 4

Sel

ect

Ri

X

Ri in

X

Ri ou

t

Yin

X

X

Zin

Z out

X

Arith

met

ic/L

ogic

Ope

ratio

n (2

)

If th

ere

are n

oper

atio

ns, d

o w

e ne

ed n

ALU

co

ntro

l lin

es?

We

coul

d us

e en

codi

ng, w

hich

requ

ires l

og2 n

co

ntro

l lin

es fo

r n o

pera

tions

. How

ever

, thi

s w

ill in

crea

se c

ompl

exity

and

har

dwar

e (a

dditi

onal

dec

oder

nee

ded)

.

A

ALU

B

A

dd

Sub

XO

R :

ALU

co

ntro

l lin

es

Car

ry-in

Read

ing

a W

ord

from

Mem

ory

Mov

e (R

1), R

2 /*

R2

[[R1

]] 1.

MAR

[R

1]

2.St

art a

Rea

d op

erat

ion

on th

e m

emor

y bu

s 3.

Wai

t for

the

MFC

resp

onse

from

the

mem

ory

4.Lo

ad M

DR fr

om th

e m

emor

y bu

s 5.

R2

[MDR

] M

DR h

as fo

ur c

ontr

ol si

gnal

s: M

DRin

, MDR

out,

MDR

inE a

nd

MDR

outE

. M

emor

y-bu

s da

ta li

nes

MD

R

X

MD

Rin

E X

MD

Rou

tE

Inte

rnal

pr

oces

sor

bus

X

MD

Rin

X

MD

Rou

t

Read

ing

a W

ord

from

Mem

ory

(2)

Mov

e (R

1), R

2 /*

R2

[[R1

]] Se

quen

ce o

f con

trol

step

s:

1.R1

out,

MAR

in, R

ead

2.M

DRin

E, W

MFC

3.

MDR

out,

R2in

WM

FC: W

ait f

or a

rriv

al o

f MFC

(Mem

ory-

Func

tion-

Com

plet

ed) s

igna

l. M

FC: T

o ac

com

mod

ate

varia

bilit

y in

resp

onse

tim

e, th

e pr

oces

sor w

aits

unt

il it

rece

ives

an

indi

catio

n th

at th

e Re

ad/W

rite

oper

atio

n ha

s bee

n co

mpl

eted

. The

add

ress

ed

devi

ce se

ts M

FC to

1 to

indi

cate

this.

Stor

ing

a W

ord

in M

emor

y

Mov

e R2

, (R1

) /*

[R1]

[R

2]

Sequ

ence

of c

ontr

ol st

eps:

1.

R1ou

t, M

ARin

2.

R2ou

t, M

DRin

, Writ

e 3.

MDR

outE

, WM

FC

Exec

utin

g a

Com

plet

e In

stru

ctio

n

Add

(R3)

, R1

/* R

1 [R

1] +

[[R3

]] Ad

ds th

e co

nten

ts o

f a m

emor

y lo

catio

n po

inte

d to

by

R3

to re

gist

er R

1.

Sequ

ence

of c

ontr

ol st

eps:

1.

PCou

t, M

ARin

, Rea

d, S

elec

t4, A

dd, Z

in

2.Z o

ut, P

C in,

Y in, W

MFC

3.

MDR

out,

IRin

4.

R3ou

t, M

ARin

, Rea

d 5.

R1ou

t, Y in

, WM

FC

6.M

DRou

t, Se

lect

Y, Ad

d, Z

in

7.Z o

ut, R

1 in,

End

Ste

ps 1

3

: In

stru

ctio

n fe

tch

Bran

ch In

stru

ctio

ns

Sequ

ence

of c

ontr

ol st

eps:

1.

PCou

t, M

ARin

, Rea

d, S

elec

t4, A

dd, Z

in

2.Z o

ut, P

C in,

Y in, W

MFC

3.

MDR

out,

IRin

4.O

ffset

_fie

ld_o

f_IR

out,

Sele

ctY,

Add,

Zin

5.

Z out

, PC i

n, En

d

Mul

tiple

-Bus

Org

aniza

tion

Sing

le-b

us st

ruct

ure:

Con

trol

sequ

ence

s are

long

as o

nly

one

data

item

can

be tr

ansf

erre

d ov

er th

e bu

s in

a cl

ock

cycl

e.

Figu

re o

n ne

xt sl

ide

show

s a th

ree-

bus s

truc

ture

. Al

l reg

ister

s are

com

bine

d in

to a

sing

le b

lock

cal

led

regi

ster

file

with

thre

e po

rts:

2 o

utpu

ts a

llow

ing

2 re

gist

ers t

o be

acc

esse

d sim

ulta

neou

sly a

nd h

ave

thei

r co

nten

ts p

ut o

n bu

ses A

and

B, a

nd 1

inpu

t allo

win

g da

ta

on b

us C

to b

e lo

aded

into

a th

ird re

gist

er.

Buse

s A a

nd B

are

use

d to

tran

sfer

sour

ce o

pera

nds t

o th

e A

and

B in

puts

of A

LU, a

nd re

sult

tran

sfer

red

to

dest

inat

ion

over

bus

C.

Mul

tiple

-Bus

Org

aniza

tion

(2)

Bus

C

Con

stan

t 4

Bus

A

Bus

B

PC

Reg

iste

r fil

e

MUX Incr

emen

ter

A A

LU

B

R

Add

ress

lin

e M

emor

y bu

s da

ta li

nes

Bus

C

Bus

A

Bus

B

MA

R

MD

R

IR

Inst

ruct

ion

deco

der

Mul

tiple

-Bus

Org

aniza

tion

(3)

For t

he A

LU, R

=A (o

r R=B

) mea

ns th

at it

s A (o

r B) i

nput

is

pass

ed u

nmod

ified

to b

us C

. Ad

d R4

, R5,

R6

/* R

6 [R

4] +

[R5]

Ad

ds th

e co

nten

ts o

f R4

and

R5 to

R6.

Sequ

ence

of c

ontr

ol st

eps:

1.

PCou

t, R=

B, M

ARin

, Rea

d, In

cPC

2.W

MFC

3.

MDR

outB

, R=B

, IR i

n 4.

R4ou

tA, R

5 out

B, Se

lect

A, A

dd, R

6 in,

End