The Von Neumann Architecture

History

1943: ENIACPresper Eckert and John Mauchly -- first general electronic computer.(or was it John V. Atanasoff in 1939?)Hard-wired program -- settings of dials and switches.1944: Beginnings of EDVACamong other improvements, includes program stored in memory1945: John von Neumannwrote a report on the stored program concept, known as the First Draft of a Report on EDVAC The basic structure proposed in the draft became knownas the “von Neumann machine” (or model).a memory, containing instructions and dataa processing unit, for performing arithmetic and logical operationsa control unit, for interpreting instructions

The Von neumann architecture

Important components

● MEMORY2k x m array of stored bits

Address: unique (k-bit) identifier of location

Contents : m-bit value stored in location

Basic Operations:

LOAD: read a value from a memory location

STORE: write a value to a memory location

● Processing Unit

ALU = Arithmetic and Logic Unit

could have many functional units.some of them special-purpose(multiply, square root, …)

LC-3 performs ADD, AND, NOT

(conit.)

Instruction Register (IR) contains the current instruction

Program Counter (PC) contains the addressof the next instruction to be executed.

Control unit:● Reads an instruction from memory

● the instruction’s address is in the PC

● interprets the instruction, generating signals that tell the other components what to do

● an instruction may take many machine cycles to complete

Instruction Processing Cycle

Disadvantage

● The shared bus between the program memory and data memory leads to the von Neumann bottleneck, the limited throughput (data transfer rate) between the central processing unit (CPU) and memory compared to the amount of memory. Because the single bus can only access one of the two classes of memory at a time, throughput is lower than the rate at which the CPU can work. This seriously limits the effective processing speed when the CPU is required to perform minimal processing on large amounts of data.

The Harvard Architecture

Mitigations

● There are several known methods for mitigating the Von Neumann performance bottleneck. For example, the following all can improve performance:

● Providing a cache between the CPU and the main memory

● providing separate caches or separate access paths for data and instructions (the so-called Modified Harvard architecture)

● using branch predictor algorithms and logic

● providing a limited CPU stack or other on-chip scratchpad memory to reduce memory access

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