computer system architecture -john d carpinelli

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SOLUTIONS MANUAL

Computer Systems Organizationand Architecture

John D. Carpinelli

Copyright 2001, Addison Wesley Longman - All Rights Reserved


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Computer Systems Organization and Architecture - Solutions Manual

Copyright 2001 Addison Wesley - All Rights Reserved Page ii

Table of Contents

Chapter 1 ....................................................................................................................................1

Chapter 2 ....................................................................................................................................8Chapter 3 ..................................................................................................................................18

Chapter 4 ..................................................................................................................................21Chapter 5 ..................................................................................................................................33

Chapter 6 ..................................................................................................................................45Chapter 7 ..................................................................................................................................59

Chapter 8 ..................................................................................................................................80Chapter 9 ..................................................................................................................................92

Chapter 10 ..............................................................................................................................100Chapter 11 ..............................................................................................................................106

Chapter 12 ..............................................................................................................................116


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Copyright 2001 Addison Wesley - All Rights Reserved Page 1

Chapter 1

1. x y z x + y y + z (x + y)(y + z) xy xz yz xy+ xz+ yz

0 0 0 1 0 0 0 0 0 0

0 0 1 1 1 1 0 0 1 10 1 0 0 1 0 0 0 0 00 1 1 0 1 0 0 0 0 0

1 0 0 1 0 0 0 0 0 0

1 0 1 1 1 1 0 1 1 1

1 1 0 1 1 1 1 0 0 1

1 1 1 1 1 1 1 1 0 1

2. a) w x y z wx xz y wx+ xz+ y b) w x y z w+ x + y+ z

0 0 0 0 0 0 1 1 0 0 0 0 0

0 0 0 1 0 0 1 1 0 0 0 1 1

0 0 1 0 0 0 0 0 0 0 1 0 1

0 0 1 1 0 0 0 0 0 0 1 1 1

0 1 0 0 0 0 1 1 0 1 0 0 10 1 0 1 0 1 1 1 0 1 0 1 10 1 1 0 0 0 0 0 0 1 1 0 1

0 1 1 1 0 1 0 1 0 1 1 1 1

1 0 0 0 0 0 1 1 1 0 0 0 1

1 0 0 1 0 0 1 1 1 0 0 1 1

1 0 1 0 0 0 0 0 1 0 1 0 1

1 0 1 1 0 0 0 0 1 0 1 1 1

1 1 0 0 1 0 1 1 1 1 0 0 1

1 1 0 1 1 1 1 1 1 1 0 1 1

1 1 1 0 1 0 0 1 1 1 1 0 11 1 1 1 1 1 0 1 1 1 1 1 1

c) w x y z wxyz wxyz wxyz wxyz wxyz + wxyz+ wxyz+ wxyz0 0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 0 00 0 1 0 0 0 1 0 1

0 0 1 1 1 0 0 0 1

0 1 0 0 0 0 0 0 0

0 1 0 1 0 0 0 0 0

0 1 1 0 0 0 0 1 1

0 1 1 1 0 1 0 0 1

1 0 0 0 0 0 0 0 0

1 0 0 1 0 0 0 0 01 0 1 0 0 0 0 0 0

1 0 1 1 0 0 0 0 0

1 1 0 0 0 0 0 0 01 1 0 1 0 0 0 0 0

1 1 1 0 0 0 0 0 0

1 1 1 1 0 0 0 0 0


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3. a b ab (ab) a b a + b a b a+ b (a+ b) a b ab

0 0 0 1 1 1 1 0 0 0 1 1 1 1

0 1 0 1 1 0 1 0 1 1 0 1 0 01 0 0 1 0 1 1 1 0 1 0 0 1 0

1 1 1 0 0 0 0 1 1 1 0 0 0 0

4. a) w'+ x'+ y'+ z'b) w'+ x'+ y'zc) (w'+ x') + (w'+ y') + (w'+ z') + (x'+ y') + (x'+ z') + (y'+ z') = w'+ x'+ y'+ z'

5. a) wx\yz 00 01 11 10 b) wx\yz 00 01 11 10

00 1 1 0 0 00 1 1 0 1

01 0 1 1 0 01 1 1 1 0

11 0 0 1 1 11 1 1 1 0

10 1 0 0 1 10 1 0 0 1

wxy+ wxz+ wxy+ wxz xz+ wy+ xz+ xy

or orxyz+ wyz+ xyz+ wyz xz+ wy+ xz+ yz

6. a) wx\yz 00 01 11 10 b) wx\yz 00 01 11 10

00 1 0 0 1 00 X 1 1 X

01 1 X 1 1 01 0 X X 0

11 0 1 X 0 11 0 0 X 0

10 0 X X 0 10 X X X X

wz+ xy x

7. a) wx\yz 00 01 11 10 b) wx\yz 00 01 11 10 c) wx\yz 00 01 11 10

00 0 1 0 0 00 1 0 0 0 00 0 1 0 101 0 1 1 0 01 1 1 0 0 01 1 0 1 0

11 1 1 1 1 11 1 1 0 1 11 0 1 0 1

10 0 0 0 0 10 1 0 0 1 10 1 0 1 0

wx+ xz+ wyz yz+ xy+ wz Already minimal

8. a) b) c)

9. wxy+ wxz+ wxy+ xyz: wx\yz 00 01 11 10

00 0 0 0 0

01 0 0 1 1

11 1 1 1 1

10 0 0 0 0

wx+ xy


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10. a) b)

11. Change the AND gates to NAND gates. The rest of the circuit is unchanged.

12. Remove the tri-state buffers and do one of the following:a) Change each 2-input AND gate to a 3-input AND gate. Each gates' inputs should be its two originalinputs andE, or

b) Have each AND gate's output serve as an input to another 2-input AND gate, one gate for each originalAND gate. The second input to the new 2-input AND gates isE.

13.

14.


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15. Set up Karnaugh maps for each output, then develop minimal logic expressions and design the appropriatelogic circuits.

X > Y: X1X0\Y1Y0 00 01 11 10 X = Y: X1X0\Y1Y0 00 01 11 10 X < Y: X1X0\Y1Y0 00 01 11 10

00 0 0 0 0 00 1 0 0 0 00 0 1 1 1

01 1 0 0 0 01 0 1 0 0 01 0 0 1 1

11 1 1 0 1 11 0 0 1 0 11 0 0 0 010 1 1 0 0 10 0 0 0 1 10 0 0 1 0

(X > Y) =X1Y1'+ X0Y1'Y0'+ X1X0Y0'

(X = Y) =X1'X0'Y1'Y0'+ X1'X0Y1'Y0 + X1X0'Y1Y0'+ X1X0Y1Y0 = (X1 Y1)'(X0 Y0)'(X < Y) =X1'Y1 + X1'X0'Y0+ X0'Y1Y0

16. C3 = X2Y2 + (X2 Y2)(X1Y1+ (X1 Y1)(X0Y0+ (X0 Y0)C0))C4 = X3Y3 + (X3 Y3)(X2Y2+ (X2 Y2)(X1Y1+ (X1 Y1)(X0Y0+ (X0 Y0)C0)))

17.


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18 X3X2\X1X0 00 01 11 10 X3X2\X1X0 00 01 11 10

00 1 0 1 1 00 1 0 0 1

01 0 1 0 1 01 0 0 0 1

11 X X X X 11 X X X X

10 1 0 X X 10 1 0 X X

d= X2'X0'+ X2'X1+ X1X0'+ X2X1'X0 e= X2'X0'+ X1X0'

X3X2\X1X0 00 01 11 10 X3X2\X1X0 00 01 11 10

00 1 0 0 0 00 0 0 1 1

01 1 1 0 1 01 1 1 0 1

11 X X X X 11 X X X X

10 1 1 X X 10 1 1 X X

f= X3 + X2X0'+ X2X1'+ X1'X0' g= X3 + X2X0'+ X1X0'+ X2'X1

19. X3 X2 X1 X0 a b c d e f g

0 0 0 0 0 0 0 0 0 0 1

0 0 0 1 1 0 0 1 1 1 10 0 1 0 0 0 1 0 0 1 0

0 0 1 1 0 0 0 0 1 1 0

0 1 0 0 1 0 0 1 1 0 0

0 1 0 1 0 1 0 0 1 0 00 1 1 0 0 1 0 0 0 0 0

0 1 1 1 0 0 0 1 1 1 1

1 0 0 0 0 0 0 0 0 0 01 0 0 1 0 0 0 1 1 0 0

a: X3X2\X1X0 00 01 11 10 b: X3X2\X1X0 00 01 11 10 c: X3X2\X1X0 00 01 11 10

00 0 1 0 0 00 0 0 0 0 00 0 0 0 1

01 1 0 0 0 01 0 1 0 1 01 0 0 0 0

11 X X X X 11 X X X X 11 X X X X10 0 0 X X 10 0 0 X X 10 0 0 X X

a = X3'X2'X1'X0+ X2X1'X0' b= X2X1'X0+ X2X1X0' c= X2'X1X0'

d: X3X2\X1X0 00 01 11 10 e: X3X2\X1X0 00 01 11 10 f: X3X2\X1X0 00 01 11 10

00 0 1 0 0 00 0 1 1 0 00 0 1 1 1

01 1 0 1 0 01 1 1 1 0 01 0 0 1 0

11 X X X X 11 X X X X 11 X X X X

10 0 1 X X 10 0 1 X X 10 0 0 X X

d= X2X1'X0'+ X2'X1'X0+ X2X1X0 e= X2X1'+ X0 f= X1X0+ X3'X2'X0+ X2'X1

g: X3X2\X1X0 00 01 11 10

00 1 1 0 0

01 0 0 1 0

11 X X X X

10 0 0 X X

g= X3'X2'X1'+ X2X1X0


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20. The four inputs can be in one of 24 (= 4!) possible orders. Since each sorter has two possible states (MAX=XMIN = Y, or MAX = YMIN = X), nsorters can have up to 2 nstates. Four sorters can have only 2 4 = 16

states, not enough to sort all 24 possible input orders. Five sorters have 25 = 32 states, which could besufficient. (This argument establishes a lower bound; it does not guarantee the existence of a 5-sorter

network that can sort four inputs. Since the sorting network of Figure 1.24(b) matches this bound, it is a

minimal network.)

21. a) b)

22. A flip-flop is clocked if the increment signal and clock are asserted, and all flip-flops to its right are 1.

23. Each clock is driven by Qof the flip-flop to its right instead of Q'. The clock of the rightmost flip-flop isunchanged. All other signals are unchanged.

24. X2 X1 X0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

0 0 0 0 0 1 0 X 0 X 1 X0 0 1 0 1 1 0 X 1 X X 00 1 0 1 1 0 1 X X 0 0 X0 1 1 0 1 0 0 X X 0 X 11 0 0 0 0 0 X 1 0 X 0 X

1 0 1 1 0 0 X 0 0 X X 1

1 1 0 1 1 1 X 0 X 0 1 X

1 1 1 1 0 1 X 0 X 1 X 0

J2: X2\X1X0 00 01 11 10 J1: X2\X1X0 00 01 11 10 J0: X2\X1X0 00 01 11 10

0 0 0 0 1 0 0 1 X X 0 1 X X 0

1 X X X X 1 0 0 X X 1 0 X X 1

J2= X1X0' J1= X2'X0 J0= X2'X1'+ X2X1

K2: X2\X1X0 00 01 11 10 K1: X2\X1X0 00 01 11 10 K0: X2\X1X0 00 01 11 10

0 X X X X 0 X X 0 0 0 X 0 1 X

1 1 0 0 0 1 X X 1 0 1 X 1 0 X

K2 = X1'X0' K1= X2X0 K0 = X2'X1+ X2X1'


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25. a) b)

26. a) b)

27.


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Chapter 2

1. a) Present State D Next State

0 0 00 1 11 0 0

1 1 1

b) Present State T Next State

0 0 0

0 1 11 0 1

1 1 0

2. Present State S R Next State

0 0 0 00 0 1 0

0 1 0 1

0 1 1 U

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 U

U 0 0 U

U 0 1 0

U 1 0 1

U 1 1 U

3. Add the following states to the state table. Since all additions are self-loops, it is not necessary to changethe state diagram.

Present State C I1 I0 Next State R G A

SNOCAR 0 0 1 SNOCAR 1 0 0



SPAID 1 0 1 SPAID 0 1 0



SCHEAT 0 0 1 SCHEAT 1 0 1




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4.


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5.

6. Address Data (Mealy) Data (Moore)

0000 0000 0000

0001 0010 0010

0010 0100 01000011 0110 0110

0100 1000 1000

0101 1010 1010

0110 1101 1100

0111 1110 1110

1000 0000 0000

1001 0010 0010

1010 0100 0100

1011 0110 0110

1100 1000 1001

1101 1010 1011

1110 1101 1100

1111 1110 1110

7. Present State I Next State M

00 0 00 0

00 1 01 0

01 0 00 0

01 1 10 0

10 0 11 0

10 1 10 0

11 0 00 1

11 1 01 1

N1= P1'P0I + P1P0'

N0= P1'P0'I + P1P0'I' + P1P0IM = P1P0


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8.

9. Address Data (Mealy) Data (Moore)

000 000 000

001 010 010

010 000 000

011 100 100100 111 110

101 100 100

110 000 001

111 010 011

10. State value assignments (P3- P0): S0= 0000 S5= 0001 S10= 0010 S15= 0011 S20= 0100S25= 0101 S30= 0110 SPAID= 0111 SNOCAR= 1000 SCHEAT= 1001

N3 = C '

N2 = P3'CI1I0 + P3'(P2 + P1)CI1I0'+ P3'(P2+ P1P0)CI1'I0+ P2CI1'I0'

N1 = P3'(P2 + P1+ P0)CI1I0+ P3'(P2+ P1')CI1I0'+ P3'(P1'P0 + P1P0'+ P2P1P0)CI1'I0 + P1P0CI1'I0'

N0 = P3'(P2 + P1+ P0')CI1I0 + P3'(P0+ P2P1)CI1I0'+ P3'(P0'+ P2P1)CI1'I0+ P3'P0CI1'I0'+ P3P0C

+P3'(P2'+ P1'+ P0')C'R = SPAID'

G = SPAIDA = SCHEAT

11. State value assignments (P3- P0): S0= 0000 S5= 0001 S10= 0010 S15= 0011 S20= 0100S25= 0101 S30= 0110 SPAID= 0111 SNOCAR= 1000 SCHEAT= 1001

N3 = C'




+P3'(P2'+ P1'+ P0')C'

R = G'G =P3'(P2+ P1)CI1I0+ P3'P2P0CI1 + P3'P2P1C(I1 + I0) +P3'P2P1P0C

A =P3'(P2 + P1+ P0)C'


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12. Address Data

0000XXX 1001101 1001101 1001101 1001101 0000100 0001100 0010100 0101100

0001XXX 1001101 1001101 1001101 1001101 0001100 0010100 0011100 0110100

0010XXX 1001101 1001101 1001101 1001101 0010100 0011100 0100100 0111010

0011XXX 1001101 1001101 1001101 1001101 0011100 0100100 0101100 0111010

0100XXX 1001101 1001101 1001101 1001101 0100100 0101100 0110100 01110100101XXX 1001101 1001101 1001101 1001101 0101100 0110100 0111010 0111010

0110XXX 1001101 1001101 1001101 1001101 0110100 0111010 0111010 0111010

0111XXX 1000100 1000100 1000100 1000100 0111010 0111010 0111010 0111010

1000XXX 1000100 1000100 1000100 1000100 0000100 0000100 0000100 0000100

1001XXX 1001101 1001101 1001101 1001101 0000100 0000100 0000100 0000100

1010XXX 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100

1011XXX 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100

1100XXX 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100

1101XXX 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100

1110XXX 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100

1111XXX 1000100 1000100 1000100 1000100 1000100 1000100 1000100 1000100

13. N2: P2P1\P0U 00 01 11 10 N1: P2P1\P0U 00 01 11 10 N2: P2P1\P0U 00 01 11 10

00 0 0 0 0 00 0 0 1 0 00 0 1 0 1

01 0 0 1 0 01 1 1 0 1 01 0 1 0 1

11 0 0 0 0 11 0 0 0 0 11 0 0 0 0

10 1 1 0 1 10 0 0 0 0 10 0 1 0 1

14. The next state logic is the same as for the Moore machine.N2 = P2P0'+ P2U'+ P1P0U

N1 = P1P0'+ P1U'+ P2'P1'P0U

N0 = P0'U+ P0U'

C= P2'P1'P0'U'+ P2P1'P0UV2 = P2'P1P0U+ P2P1'P0'+ P2P1'P0U'

V1 = P2'P1'P0U+ P2'P1P0'+ P2'P1P0U'V0 = (P2'+ P1')P0'U+ (P2'+ P1)P0U'

15. All possible next state values are already used.


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16. State value assignments (P3- P0): S0= 0000 S5= 0001 S10= 0010 S15= 0011 S20= 0100S25= 0101 S30= 0110 SPAID= 0111 SNOCAR= 1000 SCHEAT= 1001 SA = 1010

SB = 1011 SC= 1100 SD= 1101 SE= 1110 SF= 1111

Add to state table: Present State C I1 I0 Next State R G A

1010 X X X 1000 0 0 0

1011 X X X 1000 0 0 01100 X X X 1000 0 0 0

1101 X X X 1000 0 0 0

1110 X X X 1000 0 0 0

1111 X X X 1000 0 0 0

Add to state diagram:

N3 = C'+ P3(P2+ P1)




+P3'(P2'+ P1'+ P0')C'

R = SPAID'

G = SPAIDA = SCHEAT

17. N3 = P2P1P0U'+ P3(P2'+ P1'+ P0'+ U)N2 = P3P2(P0 + U) +P2P1+ P3'P1P0'U'

N1 = P3'(P2+ P1)U'+ P2P1P0U'+ P1U

N0 = (P3'+ P2)P1'U+ P3'P2U+ P0U'C= P2'P1'P0'

V2= P3P1'P0 + P3P2P0'

V1= P3'P1P0'+ P2P1P0V0= P3'P2'P0 + P2P1P0+ P3P1'P0


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18.

19.


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20. States are of the formABCYZ, whereA|B|C= 0 if a player may signal, or 1 if the player may not signal. YZrepresents the player answering the question (01 = player 1, 10 = player 2, 11 = player 3, 00 = no player).

Although not shown in the diagram, there is an arc from every state back to state 00000 with conditionR.

Address Data Address Data Address Data

XXXXX XX1X 00000 000 00110 XX00 00110 010 10010 XX00 10010 010

00000 000X 00000 000 00110 XX01 01100 010 10010 XX01 11000 010

00000 010X 00001 000 01000 X00X 01000 000 10011 XX00 10011 001

00000 100X 00010 000 01000 010X 01001 000 10011 XX01 10100 001

00000 110X 00011 000 01000 110X 01011 000 10100 0X0X 10100 000

00001 XX00 00001 100 01001 XX00 01001 100 10100 100X 10110 000

00001 XX01 10000 100 01001 XX01 11000 100 10100 110X 10100 000

00010 XX00 00010 010 01011 XX00 01011 001 10110 XX00 10110 010

00010 XX01 01000 010 01011 XX01 01100 001 10110 XX01 11100 01000011 XX00 00011 001 01100 000X 01100 000 11000 0X0X 11000 000

00011 XX01 00100 001 01100 010X 01101 000 11000 100X 11000 000

00100 000X 00100 000 01100 1X0X 01100 000 11000 110X 11011 000

00100 010X 00101 000 01101 XX00 01101 100 11011 XX00 11011 001

00100 100X 00110 000 01101 XX01 11100 100 11011 XX01 11100 001

00100 110X 00100 000 10000 0X0X 10000 000 11100 XX0X 11100 000

00101 XX00 00101 100 10000 100X 10010 000 All others 00000 000

00101 XX01 10100 100 10000 110X 10011 000


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21. States are of the formABCYZ, whereA|B|C= 0 if a player may signal, or 1 if the player may not signal. YZrepresents the player answering the question (01 = player 1, 10 = player 2, 11 = player 3, 00 = no player).

Although not shown in the diagram, there is an arc from every state back to state 00000 with conditionR.

Address Data Address Data Address Data

XXXXX XX1X 00000 000 00110 XX00 00110 010 10010 XX00 10010 010

00000 000X 00000 000 00110 XX01 01100 000 10010 XX01 11000 000

00000 010X 00001 100 01000 X00X 01000 000 10011 XX00 10011 001

00000 100X 00010 010 01000 010X 01001 100 10011 XX01 10100 000

00000 110X 00011 001 01000 110X 01011 001 10100 0X0X 10100 000

00001 XX00 00001 100 01001 XX00 01001 100 10100 100X 10110 010

00001 XX01 10000 000 01001 XX01 11000 000 10100 110X 10100 000

00010 XX00 00010 010 01011 XX00 01011 001 10110 XX00 10110 010

00010 XX01 01000 000 01011 XX01 01100 000 10110 XX01 11100 000

00011 XX00 00011 001 01100 000X 01100 000 11000 0X0X 11000 000

00011 XX01 00100 000 01100 010X 01101 100 11000 100X 11000 000

00100 000X 00100 000 01100 1X0X 01100 000 11000 110X 11011 001

00100 010X 00101 100 01101 XX00 01101 100 11011 XX00 11011 001

00100 100X 00110 010 01101 XX01 11100 000 11011 XX01 11100 000

00100 110X 00100 000 10000 0X0X 10000 000 11100 XX0X 11100 000

00101 XX00 00101 100 10000 100X 10010 010 All others 00000 000

00101 XX01 10100 000 10000 110X 10011 001


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22.

23.

24.

25. P1: P0X'Y should beP0XYP0: P0XY'should be P0X'Y'

B: P0 should be P0'

26. CLR: 0XY'should be 1XY' Counter input D0: 0X'Yshould be 0XY

A: 1 should be 0

27. Address Correct Data0011 01110

0100 01011

1011 00111


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14. a) MUL X,B,C b) MOV T,B c) LOAD B d) PUSH A

SUB X,A,X MUL T,C MUL C PUSH B

MUL T,E,F MOV X,A STORE T PUSH C

ADD T,T,D SUB X,T LOAD A MUL

MUL X,X,T MOV T,E SUB T SUB

MUL T,F STORE X PUSH DADD T,D LOAD E PUSH E

MUL X,T MUL F PUSH F

ADD D MULMUL X ADD

STORE X MUL

POP X

15. Processor Time per instruction # Instructions Total time

0 35 ns 4 140 ns

1 50 ns 3 150 ns

2 70 ns 2 140 ns

3 100 ns 1 100 ns fastest


0 35 ns 8 280 ns


2 70 ns 4 280 ns

3 100 ns 3 300 ns



1 50 ns 9 450 ns2 70 ns 7 490 ns

3 100 ns 5 500 ns



1 50 ns 11 550 ns

2 70 ns 8 560 ns

3 100 ns 5 500 ns

19. LDAC 1001HMVAC

LDAC 1002H

ADD

MVAC

LDAC 1003H

ADDMVACLDAC 1004H

ADD

MVAC

LDAC 1005HADD

MVAC

LDAC 1006H

ADD

MVAC

LDAC 1007H

ADD

MVAC

LDAC 1008HADDMVAC

LDAC 1009H

ADD

MVACLDAC 100AH

ADD

STAC 1000H


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Chapter 4

1.

2.


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3.

4.


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5.

6.


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7.

8.


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9.

10. a.) CE= A7'A6'A5'A4' ( MIO / )' OE= RD

b.) CE= A7'A6'A5'A4 ( MIO / )' OE= RDc.) CE= A7A6A5A4 ( MIO / )' OE= RD

11. Big Endian Little Endian

a) 22 12H23 34H24 56H

25 78H

22 78H23 56H24 34H

25 12H

b) 22 09H23 27H

22 27H23 09H

c) 22 05H23 55H

24 12H

25 12H

22 12H23 12H

24 55H

25 05H


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12. Start each value at location 4X, whereX I 0, 20 for example.

13.

14. This is the same as the previous problem, except MIO / is not included.

15.



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17.



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19.


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20.


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21.


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22. Memory subsystem:


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22 (continued). I/O subsystem:


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6. a) b)

c)

7.


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8. a) 0011 0010 0000 0100

b) 0100 1100 1000 0001c) 0011 0010 0000 0101

d) 0100 1100 1000 0001e) 1011 0010 0000 0100

f) 1100 1100 1000 0001g) 1001 0000 0010 0000

h) 0000 1001 1001 0000

9. a) 0000 0111 0010 1010

b) 0100 0001 1100 1010c) 0000 0111 0010 1011

d) 1100 0001 1100 1010e) 1000 0111 0010 1010

f) 1100 0001 1100 1010g) 0011 1001 0101 0000

h) 0000 1000 0011 1001

10. a) 1011 0010 1111 0000

b) 0010 1100 1011 1100c) 1011 0010 1111 0000

d) 0010 1100 1011 1100e) 0011 0010 1111 0000

f) 0010 1100 1011 1100g) 1001 0111 1000 0000

h) 0000 0101 1001 0111


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11.a)

b)

c)

d)


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12.a)

b)

c) d)

13. a) X 0,X[(n-2)-1]b) X X[(n-2)-0,( n-1)]c) X X[0,(n-1)-1]d) X[(n-2)-0] X[(n-3)-0],0e) X[(n-2)-0] X[(n-1)-1]f) X X[(n-5)-0],0000g) X 0000,X[(n-1)-4]


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18. library IEEE;use IEEE.std_logic_1164.all;

entity string_checker isport(

I,clk: in std_logic;

M: out std_logic);end string_checker;

architecture a_string_checker of string_checker istype states is (S0, S1, S2, S3);

signal present_state, next_state: states;

beginstate_check_string: process(present_state,I)

begin

case present_state iswhen S0 => M


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X1,X0: buffer std_logic;M: out std_logic);

end string_checker;

architecture a_string_checker of string_checker is

begincct_string_checker: process(X1,X0,I,clk)

beginif rising_edge(clk) then

X1


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X2,X1,X0: buffer std_logic; M: out std_logic);

end string_checker;

architecture a_string_checker of string_checker is

begincct_string_checker: process(X1,X0,I,clk)

beginif rising_edge(clk) then

X2


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when S10 => R


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Chapter 6

1. JMP11: PC ARJMP12: PC PC+ 1INC21: AC

AC+ 1

INC22: AC AC+ 1ADD11:DR M,AC AC+ 1ADD12:AC AC+ DRSKIP1: PC PC+ 1

2. Instruction Instruction Code Operation

ADDADD 00AAAAAA AC AC+ M[AAAAAA] + M[AAAAAA + 1]ANDSKIP 01AAAAAA AC AC^ M[AAAAAA], PC PC+ 1INCAND 1XAAAAAA AC (AC+ 1) ^ M[AAAAAA]

3. This is one of many possible solutions.

4.


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5. Change the input to the counter toX,X', Y,X Y.ChangeINCinput IA3 to IA2.

Change CLRinput IA2 to IA3.

6. (IR must have 3 bits instead of 2.)

FETCH3: IR DR[7..5],AR DR[5..0]CLEAR1: AC 0

7. i) IR must have 3 bits instead of 2. It receives bus bits 7..5 as its inputs. During FETCH3, bit 5 of DRissent to bothIRand AR.

ii) ACneeds a CLRinput (ACCLRis a new control signal which connects to the new CLRinput.)

8. Arbitrarily assign CLEAR1to decoder output 15.i) New input to counter: 1,IR[2..1],(IR2^ IR1^ IR0).ii) Add CLEAR1to the inputs of the OR gate driving counter CLR.

iii) New control signalACCLR= CLEAR1.

9. Test program: 0: CLEAR

Instruction State Operations performed Next state

CLEAR FETCH1 AR 0 FETCH2FETCH2 DR E0H, PC 1 FETCH3FETCH3 IR 111, AR 20H CLEAR1CLEAR1 AC 0 FETCH1

10. (IR must have 4 bits instead of 2.)

FETCH3: IR DR[7..4],AR DR[5..0]MVAC1: R ACMOVR1: AC R


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11. i.) IR must have 4 bits instead of 2. It receives bus bits 7..4 as its inputs. During FETCH3, bit DR[5..4] issent to bothIRand AR. This is shown below.

ii) RegisterRis added to the CPU. It receives data from the bus and sends data to the bus through tri-state

buffers. It requires only aLDsignal. This is shown below.iii) The ALU is modified as shown below.

12. Arbitrarily assignMVAC1and MOVR1to decoder outputs 6 and 7, respectively.

i) New input to counter: (IR3^ IR2^ IR1)',IR[3..2],(IR3 ^ IR2^ IR1^ IR0.).

ii) AddMVAC1and MOVR1 to the inputs of the OR gate driving counter CLR.

iii) New control signalsRLOAD= MVAC1 and RBUS= MOVR1.

iv) AddMOVR1to the inputs of the OR gate generating ACLOAD.

13. Test program: 0: MVAC1: MOVR


MVAC FETCH1 AR 0 FETCH2FETCH2 DR E0H, PC 1 FETCH3FETCH3 IR 1110, AR 20H MVAC1MVAC1 R 1 FETCH1

MOVR FETCH1 AR 1 FETCH2FETCH2 DR F0H, PC 2 FETCH3FETCH3 IR 1111, AR 30H MOVR1MOVR1 AC1 FETCH1


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14. All operations except AND are performed by the parallel adder.

Micro-operation Adder inputs

ADD1 AC+ BUS+ 0shl AC+ AC+ 0

neg 0 +BUS'+ 0

ad1 AC+ BUS+ 1

15. PCLOAD=JUMP3 JMPZY3 JPNZY3PCINC=FETCH2 LDAC1 LDAC2 STAC1 STAC2 JMPZN1 JMPZN2 JPNZN1

JPNZN2

DRLOAD=FETCH2

LDAC1

LDAC2

LDAC4

STAC1

STAC2

STAC4

JUMP1

JUMP2

JMPZY1 JMPZY2 JPNZY1 JPNZY2TRLOAD=LDAC2 STAC2 JUMP2 JMPZY2 JPNZY2IRLOAD=FETCH3

16. RLOAD=MVAC1ACLOAD=LDAC5 MOVR1 ADD1 SUB1 INAC1 CLAC1 AND1 OR1 XOR1 NOT1

ZLOAD=ADD1 SUB1 INAC1 CLAC1 AND1 OR1 XOR1 NOT1

17. State ALUS[1..7]

LDAC5 0 0 1 0 X X 0

MOVR1 0 0 1 0 X X 0 ALUS1= ADD1 SUB1 INAC1ADD1 1 0 1 0 X X 0 ALUS2= SUB1

SUB1 1 1 0 0 X X 0 ALUS3= LDAC5 MOVR1 ADD1INAC1 1 0 0 1 X X 0 ALUS4= SUB1 INAC1CLAC1 0 0 0 0 X X 0 ALUS5= XOR1 NOT1

AND1 X X X X 0 0 1 ALUS6= OR1 NOT1OR1 X X X X 0 1 1 ALUS7= AND1 OR1 XOR1 NOT1

XOR1 X X X X 1 0 1

NOT1 X X X X 1 1 1


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18. The student can execute the following program using the Relatively Simple CPU simulator to verify thateach instruction performs properly.

0: LDAC 0000 (AC 1)NOP

MVAC (R 1)

ADD (AC 2, Z 0)INAC (AC 3, Z 0)XOR (AC 2, Z 0)AND (AC 0, Z 1)

9: JMPZ 000D (jump is taken)

NOP (skipped by JMPZ 000D)D: JPNZ 0009 (jump is not taken)

NOT (AC FF, Z 0)JMPZ 0009 (jump is not taken)

JPNZ 0018 (jump is taken)

NOP (skipped by JMPZ 0018)

18: CLAC (AC 0, Z 1)OR (AC 1, Z 0)

SUB (AC 0, Z 1)MOVR (AC 1)STAC 0030 (M[30] 1)AND (AC 1, Z 0)JUMP 0000 (start again)

19. SETR1: R 0SETR2: R R- 1

20. R needs two additional inputs: CLR, driven by new control signalRCLR, andDCR, driven by new controlsignalRDCR.

21. i.) Add hardware to generateISETR= I7'^ I6'^ I5'^ I4 ^ I3'^ I2'^ I1'^ I0', SETR1 = ISETR^ T3, andSETR2 = ISETR^ T4.

ii) Add SETR1to the OR gate driving INCof the time counter and SETR2 to the OR gate driving CLRof

the time counter.

iii) New control signalsRCLR= SETR1and RDCR= SETR2.

22. Test program: 0: SETR


SETR FETCH1 AR 0 FETCH2FETCH2 DR 11H, PC 1 FETCH3FETCH3 IR 11, AR 1 SETR1SETR1 R 0 SETR2SETR2 R FF FETCH1


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23.

ADDB1: AC AC+ BSUBB1: AC AC- BANDB1: AC AC^ BORB1: AC AC BXORB1: AC AC B

24. i.) No ALU changes are needed!ii) RegisterBis added to the CPU. It sends data to the bus through tri-state buffers but does not receive

data from the bus (since it is never loaded). This is shown below.

25. i.) Add the hardware shown below to generateIADDB,ISUBB,IANDB,IORB, andIXORB, and addhardware to generateADDB1= IADDB^ T3, SUBB1= ISUBB^ T3,ANDB1= IANDB^ T3,

ORB1= IORB^ T3, andXORB1= IXORB^ T3.ii) OR togetherADDB1, SUBB1,ANDB1, ORB1, andXORB1to generate BBUS.

iii) Add the same five signals to the OR gate driving CLRof the counter.

iv) ChangeALUS[1..7] such thatADD1is replaced by ADD1 ADDB1, and so on for SUB1,AND1,OR1, andXOR1, yielding:

ALUS1= ADD1 ADDB1 SUB1 SUBB1 INAC1ALUS2= SUB1 SUBB1ALUS3= LDAC5 MOVR1 ADD1ADDB1ALUS4= SUB1 SUBB1INAC1ALUS5= XOR1 XORB1 NOT1ALUS6= OR1 ORB1 NOT1ALUS7= AND1 ANDB1 OR1 ORB1 XOR1 XORB1 NOT1


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26. InitiallyAC= 1 and B = 2. Fetch cycles not shown.

Instruction State Operations performed

ORB ORB1 AC 1 2 = 3ADDB ADDB1 AC 3 + 2 = 5ANDB ANDB1 AC 5 ^ 2 = 0XORB XORB1 AC 0 2 = 2SUBB SUBB1 AC 2 - 2 = 0

27. i.) Remove CLAC1 and INAC1as inputs to the OR gate which generates ACLOAD.ii) Add control inputs to AC: CLR = CLAC1, andINC= INAC1.

iii) Change the input toZas shown below. ZLOADis unchanged.

28. State diagram and RTL code:FETCH1: AR PCFETCH2: DR M,PC PC+ 1FETCH3: IR DR[7..6],AR DR[5..0]COM1: AC AC'JREL1: DR MJREL2: PC PC+ DR[5..0]

OR1: DR MOR2: AC AC DRSUB11: DR MSUB12: AC AC+ DR'

The register section is the same as Figure 6.6, except for the data input toPC, shown below.


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Control signals: ARLOAD= FETCH1 FETCH3PCLOAD= JREL2

PCINC=FETCH2

PCBUS= FETCH1

DRLOAD= MEMBUS= READ=FETCH2 JREL1 OR1 SUB11DRBUS= FETCH3 JREL2 OR2 SUB12

ACLOAD= COM1 OR2 SUB12IRLOAD=FETCH3

ALU:

Control unit:


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29. State diagram and RTL code:

FETCH1: AR PC ADD1: DR M,PC PC+ 1FETCH2: DR M,PC PC+ 1 ADD2: AC AC+ DRFETCH3: IR DR[7..5],AR PC OR1: DR M,PC PC+ 1LDI1: DR M,PC PC+ 1 OR2: AC AC DRLDI2: AC DR JUMP1:DR MSTO1: DR M,PC PC+ 1 JUMP2: PC DRSTO2: AR DR JREL1: PC PC+ 000DR[4..0]STO3: DR AC SKIP1: PC PC+ 1STO4: M DR RST1: PC 0, AC 0

Control signals: ARLOAD= FETCH1 FETCH3 STO2PCLOAD= JUMP2 JREL2

PCINC= FETCH2 LDI1 STO1 ADD1 OR1 SKIP1PCCLR= RST1

PCBUS = FETCH1 FETCH3PCMUX = JUMP2

DRLOAD= FETCH2 LDI1 STO1 STO3 ADD1 OR1 JUMP1DRBUS= FETCH3 LDI2 STO2 STO4 ADD2 OR2 JUMP2 JREL1

ACLOAD= LDI2 ADD2 OR2ACCLR= RST1

ACBUS= STO3

IRLOAD=FETCH3

MEMBUS= READ= FETCH2 LDI1 STO1 ADD1 OR1 JUMP1BUSMEM= WRITE= STO4


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Control unit:

FETCH1= T0 ADD1 = IADD^ T3

FETCH2= T1 ADD2= IADD^ T4

FETCH3= T2 OR1= IOR^ T3LDI1= ILDI^ T3 OR2= IOR^ T4

LDI2= ILDI^ T4 JUMP1= IJUMP^ T3STO1 = ISTO^ T3 JUMP2= IJUMP^ T4

STO2 = ISTO^ T4 JREL1= IJREL^ T3

STO3 = ISTO^ T5 JREL2= IJREL^ T4

STO4 = ISTO^ T6 SKIP1= ISKIP^ T3

RST1= IRST^ T3

30. Modified state diagram:


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New control signals:

ARDEC= CALL5SPLOAD = LDSP3

SPINC= RET2 RET3 POPAC2 POPR2SPDEC= CALL3 CALL5 PUSHAC1 PUSHR1

SPBUS= CALL4 RET1 PUSHAC2 POPAC1 PUSHR2 POPR1DRSEL= CALL3TR2LOAD = CALL3

TR2BUS= CALL8

Modified control signals:

ARLOAD= (original value) CALL4 RET1 PUSHAC2 POPAC1 PUSHR2 POPR1

ARINC= (original value) LDSP1 CALL1 RET2PCLOAD= (original value) CALL8 RET4

PCINC= (original value) LDSP1 LDSP2 CALL1 CALL2PCBUS= (original value) CALL3 CALL6

DRLOAD= (original value) LDSP1 LDSP2 CALL1 CALL2 CALL3 CALL6 RET2 RET3 PUSHAC1 POPAC2 PUSHR1 POPR2

DRHBUS= (original value) LDSP3 RET4DRLBUS= (original value) CALL5 CALL7 PUSHAC3 POPAC3

PUSHR3 POPR3TRLOAD = (original value) LDSP2 CALL2 RET3

TRBUS= (original value) LDSP3 CALL8 RET4RLOAD= (original value) POPR3

RBUS= (original value) PUSHR1ACLOAD= (original value) POPAC3

ACBUS= (original value) PUSHAC1ALUS1= (original value) POPAC3

MEMBUS= (original value) LDSP1 LDSP2 CALL1 CALL2 RET2 RET3 POPAC2 POPR2

BUSMEM= (original value) CALL5 CALL7 PUSHAC3 PUSHR3WRITE= (original value) CALL5 CALL7 PUSHAC3 PUSHR3


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Chapter 7

1. IR MAP

00 0011

01 0101MAP =IR1 ^IR0,IR1 IR0, IR0',(IR1 ^IR0)'10 0111

11 1000

2. State Address SE

L

A

R

P

C

A

I

D

R

P

C

I

N

P

C

D

R

D

R

M

P

L

U

S

A

N

D

A

C

I

N

ADDR

FETCH1 0000 (0) 0 1 0 0 0 0 0 0 0 0001

FETCH2 0001 (1) 0 0 0 1 0 1 0 0 0 0010

FETCH3 0010 (2) 1 0 1 0 0 0 0 0 0 XXXX

ADD1 0011 (3) 0 0 0 0 0 1 0 0 0 0100

ADD2 0100 (4) 0 0 0 0 0 0 1 0 0 0000AND1 0101 (5) 0 0 0 0 0 1 0 0 0 0110

AND2 0110 (6) 0 0 0 0 0 0 0 1 0 0000

JMP1 0111 (7) 0 0 0 0 1 0 0 0 0 0000

INC1 1000 (8) 0 0 0 0 0 0 0 0 1 0000

3. M1 M2

NOP NOP Required

DR M PC PC+ 1 Micro-operations in these two rows must beAC AC' AC AC+ 1 allocated the same relative to each other

DR DR+ 1 PC PC+ DR[5..0] The remaining operations are assignedAR PC arbitrarily

IR,AR DRAC AC DR

M DR


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4. Test program: 0: ADD 41: AND 5

2: INC

3: JMP 04: 27H

5: 39H

Instruction State Address Micro-operations Operations performed Next Address

ADD 4 FETCH1 0000 ARPC AR 0 0001FETCH2 0001 DRM, PCIN DR 04H, PC 1 0010FETCH3 0010 AIDR IR 00, AR 04H 1000ADD1 1000 DRM DR 27H 1001ADD2 1001 PLUS AC 0 + 27H = 27H 0000

AND 5 FETCH1 0000 ARPC AR 1 0001FETCH2 0001 DRM, PCIN DR 45H, PC 2 0010FETCH3 0010 AIDR IR 01, AR 05H 1010AND1 1010 DRM DR 39H 1011AND2 1011 AND AC 27H ^ 39H = 31H 0000

INC FETCH1 0000 ARPC AR 2 0001FETCH2 0001 DRM, PCIN DR C0H, PC 3 0010FETCH3 0010 AIDR IR 11, AR 00H 1110INC1 1110 ACIN AC 21H + 1 = 22H 0000

JMP 0 FETCH1 0000 ARPC AR 3 0001FETCH2 0001 DRM, PCIN DR 80H, PC 4 0010FETCH3 0010 AIDR IR 10, AR 00H 1100JMP1 1100 PCDR PC 0 0000

5. Use the same test program as in problem 4.

Instruction State Address M1 M2 Operations performed Next Address

ADD 4 FETCH1 0000 ARPC NOP AR 0 0001FETCH2 0001 DRM PCIN DR 04H, PC 1 0010FETCH3 0010 AIDR NOP IR 00, AR 04H 1000ADD1 1000 DRM NOP DR 27H 1001ADD2 1001 PLUS NOP AC 0 + 27H = 27H 0000

AND 5 FETCH1 0000 ARPC NOP AR 1 0001FETCH2 0001 DRM PCIN DR 45H, PC 2 0010FETCH3 0010 AIDR NOP IR 01, AR 05H 1010AND1 1010 DRM NOP DR 39H 1011AND2 1011 AND NOP AC 27H ^ 39H = 31H 0000

INC FETCH1 0000 ARPC NOP AR 2 0001FETCH2 0001 DRM PCIN DR C0H, PC 3 0010FETCH3 0010 AIDR NOP IR 11, AR 00H 1110INC1 1110 ACIN NOP AC 21H + 1 = 22H 0000

JMP 0 FETCH1 0000 ARPC NOP AR 3 0001FETCH2 0001 DRM PCIN DR 80H, PC 4 0010FETCH3 0010 AIDR NOP IR 10, AR 00H 1100JMP1 1100 PCDR NOP PC 0 0000


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6. Use the same test program as in problem 4.

Instruction State Address Control Signals Operations performed Next Address

ADD 4 FETCH1 0000 PCBUS, ARLOAD AR 0 0001FETCH2 0001 READ, MEMBUS,

DRLOAD, PCINCDR 04H, PC 1 0010

FETCH3 0010 DRBUS, ARLOAD,IRLOAD

IR 00, AR 04H 1000

ADD1 1000 READ, MEMBUS,DRLOAD

DR 27H 1001

ADD2 1001 DRBUS, ACLOAD AC 0 + 27H = 27H 0000AND 5 FETCH1 0000 PCBUS, ARLOAD AR 1 0001

FETCH2 0001 READ, MEMBUS,

DRLOAD, PCINCDR 45H, PC 2 0010

FETCH3 0010 DRBUS, ARLOAD,IRLOAD

IR 01, AR 05H 1010

AND1 1010 READ, MEMBUS,

DRLOADDR 39H 1011

AND2 1011 DRBUS, ALUSEL,

ACLOADAC 27H ^ 39H = 31H 0000

INC FETCH1 0000 PCBUS, ARLOAD AR 2 0001FETCH2 0001 READ, MEMBUS,

DRLOAD, PCINCDR C0H, PC 3 0010

FETCH3 0010 DRBUS, ARLOAD,

IRLOADIR 11, AR 00H 1110

INC1 1110 ACINC AC 21H + 1 = 22H 0000JMP 0 FETCH1 0000 PCBUS, ARLOAD AR 3 0001

FETCH2 0001 READ, MEMBUS,DRLOAD, PCINC

DR 80H, PC 4 0010

FETCH3 0010 DRBUS, ARLOAD,

IRLOADIR 10, AR 00H 1100

JMP1 1100 DRBUS, PCLOAD PC 0 0000


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10. Modified state diagram: (same as for problem 6.10)

(IR must have 4 bits instead of 2.)

Modified RTL code: (same as for problem 6.10)

FETCH3: IR DR[7..4],AR DR[5..0]MVAC1: R

AC

MOVR1: AC R

Microsequencer modifications:

i) Change the mapping hardware so that its inputs areIR[3..0] and its outputs are

(IR3^ IR2^ IR1),IR[3..2],(IR3 ^ IR2^ IR1^ IR0).

ii) Add micro-operationRAC(R AC); connect it to an OR gate that generatesACBUSand have itdirectly driveRLOAD.

iii) Add micro-operationACR(AC R); connect it to directly toRBUSand connect it to an OR gatethat generatesACLOAD.

Register and ALU modifications: (same as for problem 6.11)

i.) IR must have 4 bits instead of 2. It receives bus bits 7..4 as its inputs. During FETCH3, bit DR[5..4] is

sent to bothIRand AR. This is shown below.

ii) RegisterRis added to the CPU. It receives data from the bus and sends data to the bus through tri-state

buffers. It requires only aLDsignal. This is shown below.

iii) The ALU is modified as shown below.


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Microcode modifications:

Add the following to microcode memory. Set theRACand ACRfields to 0 for all other microinstructions.

State Address SE

L

AR

PC

AI

DR

PC

IN

PC

DR

DR

M

PL

US

AN

D

AC

IN

RA

C

AC

R

ADDR

MVAC1 0110 (6) 0 0 0 0 0 0 0 0 0 1 0 0000

MOVR1 0111 (7) 0 0 0 0 0 0 0 0 0 0 1 0000

Verification: Test program: 0: MVAC (InitiallyAC= 1)

1: MOVR

Instruction State Address Micro-operations Operations performed Next Address

MVAC FETCH1 0000 ARPC AR 0 0001FETCH2 0001 DRM, PCIN DR E0H, PC 1 0010FETCH3 0010 AIDR IR 1110, AR 20H 0110MVAC1 0110 RAC R 01H 0000

MOVR FETCH1 0000 ARPC AR 1 0001FETCH2 0001 DRM, PCIN DR F0H, PC 2 0010FETCH3 0010 AIDR IR 1111, AR 30H 0111MOVR1 0111 ACR AC 01H 0000

11. The modifications are the same as in problem 10 with the following exceptions.

i) Add micro-operationsRAC(R AC) andACR(AC R) to M2 with the following assignments.

M2 Micro-operation

00 NOP

01 PCIN

10 RAC

11 ACR

ii) Use a 2-to-4 decoder to generate the control signals for M2.

iii) Modify the existing microinstructions to accommodate the new values for M2 (0 00, 1 01).iv) Add the following to microcode memory.

State Address SEL M1 M2 ADDR

MVAC1 0110 0 000 10 0000

MOVR1 0111 0 000 11 0000

Verification: Test program: 0: MVAC (InitiallyAC= 1)

1: MOVR

Instruction State Address M1 M2 Operations performed Next AddressMVAC FETCH1 0000 ARPC NOP AR 0 0001FETCH2 0001 DRM PCIN DR E0H, PC 1 0010FETCH3 0010 AIDR NOP IR 1110, AR 20H 0110MVAC1 0110 NOP RAC R 01H 0000

MOVR FETCH1 0000 ARPC NOP AR 1 0001FETCH2 0001 DRM PCIN DR F0H, PC 2 0010FETCH3 0010 AIDR NOP IR 1111, AR 30H 0111MOVR1 0111 NOP ACR AC 01H 0000


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14. Modified state diagram and RTL code: (same as for problem 6.19)

SETR1: R 0SETR2: R R- 1

Register and ALU modifications: (same as for problem 6.20)

R needs two additional inputs: CLR, driven by new control signalRCLR, andDCR, driven by new control

signalRDCR. There are no ALU modifications.

Microcode and microsequencer modifications:

i) Add micro-operations CLRR(R 0) and DECR(R R - 1) to the microcode. These fields are set tozero for all existing microinstructions.

ii) Change the mapping function to (IR4 IR3),(IR4 IR2),(IR4 IR1), (IR4 IR0),IR4,0.iii) Add the following microinstructions to the microprogram.

State Address Condition BT All other micro-operations CLRR DECR ADDR

SETR1 62 1 J 0 1 0 63

SETR2 63 1 J 0 0 1 1

Verification: Test program: 0: SETR

Instruction State Active signals Operations performed Next state

SETR FETCH1 PCBUS, ARLOAD AR 0 FETCH2FETCH2 READ, MEMBUS,

DRLOAD, PCINCDR 10H, PC 1 FETCH3

FETCH3 DRBUS, ARLOAD,

IRLOADIR 10H, AR 01H SETR1

SETR1 CLRR R 00H SETR2SETR2 DECR R FFH FETCH1


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iv) Add the following microinstructions to the microprogram.

State Address Cond. BT All other

-ops

BPLU BMIN BAND BOR BXOR ADDR

ADDB1 33 1 J 0 1 0 0 0 0 1

SUBB1 37 1 J 0 0 1 0 0 0 1

ANDB1 49 1 J 0 0 0 1 0 0 1ORB1 53 1 J 0 0 0 0 1 0 1

XORB1 57 1 J 0 0 0 0 0 1 1

Verification: Test program shown below. Fetch cycles not shown

Instruction State Micro-operations Operations performed

ORB ORB1 BOR AC 1 2 = 3ADDB ADDB1 BPLU AC 3 + 2 = 5ANDB ANDB1 BAND AC 5 ^ 2 = 0XORB XORB1 BXOR AC 0 2 = 2SUBB SUBB1 BMIN AC 2 - 2 = 0

16. PCLOAD = PCDT RBUS= ACR PLUS MINU AND OR XORTRLOAD = TRDR ALUS1= PLUS MINU ACIN

PCBUS = ARPC ALUS2 = MINU

DRHBUS= ARDT PCDT ALUS3= ACDR ACR PLUSDRLBUS= ACDR MDR ALUS4= MINU ACIN

ACBUS= DRAC RAC ALUS5= XOR NOTREAD = DRM ALUS6= OR NOT

WRITE = MDR ALUS7= AND OR XOR NOTMEMBUS

BUSMEM

= DRM

= MDR

ACLOAD= ACDR ACR PLUS MINU ACIN ACZO AND OR XOR NOT

17. The subroutine now consists only of its last two instructions:

State A

d

dr

e

s

s

C

o

nd

i

t

i

o

n

B

T

A

R

PC

A

R

IN

A

R

DT

P

C

IN

P

C

DT

D

R

M

D

R

AC

I

R

DR

R

A

C

Z

A

LU

T

R

DR

A

C

DR

A

C

R

P

L

US

M

I

NU

A

C

IN

A

C

ZO

A

N

D

O

R

X

O

R

N

O

T

M

D

R

A

D

DR

SUB1 61 1 J 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 62

SUB2 62 1 R 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X


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18. i) The microsequencer is the same as shown in Figure 7.8, except the micro-operations fields are input todecoders which generate the micro-operations. ii) From the microcode of Table 7.17, the following groups of micro-operations must occursimultaneously at least once, and therefore must be located in different fields:

PCIN, DRM, and ARIN ARPC, and IRDR PCIN, DRM, and TRDR ZALU, and each of the arithmetic and logic micro-operations (PLUS, MINU, ACIN, ACZO,

AND, OR, XOR, and NOT)

iii) Since some microinstructions (such as NOP1) perform no micro-operations, each field requires a NOP.

One possible partitioning of the micro-operations, and its resultant microcode, are shown below.

M1 M2 M3

NOP PLUS NOP NOP

TRDR MINU PCIN DRM

ARIN ACIN IRDR

ARPC ACZO ZALUARDT AND ACDR

PCDT OR ACR

DRAC XOR MDR

RAC NOT

State Address

Conditio

n

BT

M1 M2 M3 ADDR

State Address

Conditio

n

BT

M1 M2 M3 ADDR

FETCH1 1 1 J ARPC NOP NOP 2 JMPZ1 24 Z J NOP NOP NOP 41

FETCH2 2 1 J NOP PCIN DRM 3 JMPZY1 25 1 J ARIN NOP DRM 26

FETCH3 3 X M ARPC IRDR NOP X JMPZY2 26 1 J TRDR NOP DRM 27

NOP1 0 1 J NOP NOP NOP 1 JMPZY3 27 1 J PCDT NOP NOP 1

LDAC1 4 1 J ARIN PCIN DRM 5 JMPZN1 41 1 J NOP PCIN NOP 42

LDAC2 5 1 J TRDR PCIN DRM 6 JMPZN2 42 1 J NOP PCIN NOP 1

LDAC3 6 1 J ARDT NOP NOP 7 JPNZ1 28 Z J NOP NOP NOP 45

LDAC4 7 1 J NOP NOP DRM 33 JPNZY1 29 1 J ARIN NOP DRM 30

LDAC5 33 1 J NOP ACRD NOP 1 JPNZY2 30 1 J TRDR NOP DRM 31

STAC1 8 1 J ARIN PCIN DRM 9 JPNZY3 31 1 J PCDT NOP NOP 1

STAC2 9 1 J TRDR PCIN DRM 10 JPNZN1 45 1 J NOP PCIN NOP 46

STAC3 10 1 J ARDT NOP NOP 11 JPNZN2 46 1 J NOP PCIN NOP 1

STAC4 11 1 J DRAC NOP NOP 34 ADD1 32 1 J PLUS ZALU NOP 1

STAC5 34 1 J NOP MDR NOP 1 SUB1 36 1 J MINU ZALU NOP 1MVAC1 12 1 J NOP NOP NOP 1 INAC1 40 1 J ACIN ZALU NOP 1

MOVR1 16 1 J NOP NOP NOP 1 CLAC1 44 1 J ACCL ZALU NOP 1

JUMP1 20 1 J ARIN NOP DRM 21 AND1 48 1 J AND ZALU NOP 1

JUMP2 21 1 J TRDR NOP DRM 22 OR1 52 1 J OR ZALU NOP 1

JUMP3 22 1 J PCDT NOP NOP 1 XOR1 56 1 J XOR ZALU NOP 1

NOT1 60 1 J NOT ZALU NOP 1


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Control signals: ARLOAD= FETCH1 FETCH3PCLOAD= JREL2

PCINC=FETCH2

PCBUS= FETCH1

DRLOAD= MEMBUS= READ=FETCH2 JREL1 OR1 SUB11DRBUS= FETCH3 JREL2 OR2 SUB12

ACLOAD= COM1 OR2 SUB12IRLOAD=FETCH3

ALU:

The microsequencer hardware is the same as shown in Figures 7.3 and 7.4, except the micro-operations are

replaced by control signals.

Microcode:

State Address S

E

L

A

R

L

O

AD

P

C

L

O

AD

P

C

I

N

C

P

C

B

U

S

D

M

R

D

R

B

U

S

A

C

L

O

AD

I

R

L

O

AD

A

L

U

S

1

A

L

U

S

2

ADDR

FETCH1 0000 (0) 0 1 0 0 1 0 0 0 0 0 0 0001

FETCH2 0001 (1) 0 0 0 1 0 1 0 0 0 0 0 0010

FETCH3 0010 (2) 1 1 0 0 0 0 1 0 1 0 0 XXXX

COM1 1000 (8) 0 0 0 0 0 0 0 1 0 0 0 0000

JREL1 1010 (10) 0 0 0 0 0 1 0 0 0 0 0 1011

JREL2 1011 (11) 0 0 1 0 0 0 1 0 0 0 0 0000

OR1 1100 (12) 0 0 0 0 0 1 0 0 0 0 0 1101

OR2 1101 (13) 0 0 0 0 0 0 1 1 0 1 0 0000

SUB11 1110 (14) 0 0 0 0 0 1 0 0 0 0 0 1111

SUB12 1111 (15) 0 0 0 0 0 0 1 1 0 0 1 0000


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Register section:

ALU:


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The microsequencer hardware is the same as shown in Figures 7.3 and 7.4, except the micro-operations are

output to decoders to generate the actual micro-operation signals, and the mapping function is 1,IR[2..0],0.

Micro-operation field assignments:

M1 M2

0 NOP 0 NOP

1 AR PC 1 IR DR[7..5]2 DR M 2 PC PC+ 13 AC DR 3 PC 04 AR DR 4 PC DR5 DR AC 5 PC PC+ 000DR[4..0]6 M DR 6 AC A C+ DR7 AC 0 7 AC AC DR

Microcode:

State Address SEL M1 M2 ADDR

FETCH1 00000 0 001 000 00001

FETCH2 00001 0 101 010 00010FETCH3 00010 1 001 001 XXXX

STO3 00100 0 101 000 00101

STO4 00101 0 110 000 00000

LDI1 10000 0 010 010 10001

LDI2 10001 0 011 000 00000

STO1 10010 0 010 010 10011

STO2 10011 0 100 000 00100

ADD1 10100 0 010 010 10101

ADD2 10101 0 000 110 00000

OR1 10110 0 010 010 10111

OR2 10111 0 000 111 00000

JUMP1 11000 0 010 000 11001

JUMP2 11001 0 000 100 00000

JREL1 11010 0 000 101 00000

SKIP1 11100 0 000 010 00000

RST1 11110 0 111 011 00000


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23. The state diagram, RTL code, and register section are the same as in Problem 6.30.

Modified state diagram:

Modified RTL code:

LDSP1: DR M,AR AR+ 1, PC PC+ 1 PUSHAC1: SP SP- 1, DR ACLDSP2: TR DR,DR M,PC PC+ 1 PUSHAC2: AR SPLDSP3: SP DR,TR PUSHAC3: M DRCALL1:DR M,AR AR+ 1, PC PC+ 1 POPAC1: AR SPCALL2: TR DR,DR M,PC PC+ 1 POPAC2: DR M, SP SP+ 1CALL3: TR2 DR,DR PC[15..8], SP SP- 1 POPAC3: AC DRCALL4:AR SP PUSHR1: SP SP- 1, DR RCALL5:M

DR,AR

AR- 1, SP

SP- 1 PUSHR2: AR

SP

CALL6:DR PC[7..0] PUSHR3: M DRCALL7:M DR POPR1: AR SPCALL8:PC TR2,DR POPR2: DR M, SP SP+ 1RET1: AR SP POPR3: R DRRET2: DR M, SP SP+ 1, AR AR+ 1RET3: TR DR,DR M, SP SP+ 1RET4: PC DR,TR

Modified register section: (shown below)

New registers: SP(with LD,DEC,INC), TR2(with LD, receives data directly fromDR) New control signal:ARadds a DECsignal New data path:DRcan receive data from BUS[15..8] orBUS[7..0] All other connections remain the same as shown in Figure 6.15.


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14. 11:CU U+ X+ 112:U U+ X, OVERFLOWC

C12:FINISH 12:Y 0, i n3:shl CUV, shl Y, i i 1

C41:U U+ X+ 1C41:CU U+ X+ 1C42:Y0 1

C42:U U+ XZ 42:FINISH 1Z42:goto 3

(Only 12, and 2, and the OVERFLOW hardware are changed; the rest is the same as in the chapter.)

15. 10:NU Un-1,NX Xn-1Un-110:UV ( UV)'+ 1Xn-110:X X'+ 1

G1:FINISH 1, OVERFLOW 1NUG1:UV ( UV)'+ 1NXG1:X X'+ 1

2:Y 0, C 0, OVERFLOW 0, i n3:shl CUV, shl Y, i i 1

(C+ G)4:Y0 1, U CU+ X+ 1Z4:goto 3

(NUNX)5:Y Y'+ 1, U U'+ 1NX5:X X'+ 1

5:FINISH 1

16. 10:NU Un-1,NX Xn-1Un-110:UV ( UV)'+ 1Xn-110:X X'+ 1

11:CU U+ X+ 112:U U+ X

C12:FINISH 1, OVERFLOW 1NUC12:UV ( UV)'+ 1NXC12:X X'+ 1

2:Y 0, C 0, OVERFLOW 0, i n3:shl CUV, shl Y, i i 1

C41:U U+ X+ 1C41:CU U+ X+ 1C42:Y0 1

C42:U U+ XZ42:goto 3

(NUNX)5:Y Y'+ 1, U U'+ 1NX5:X X'+ 1

5:FINISH 1


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Yd0 Yd0 1, goto 2ZY0 2 CdU CdU+ X,

Yd0 Yd0 1, goto 22 27 00 1

ZY02 i i 1 0 13,Z3 dshr(CdUV), dshr(Y),

FINISH 122 72 1

Result: +71-32 = -2272

c) Conditions Micro-operations i Cd U V Y Z Y0 Z FINISH

START x x xx xx 10 0 0

1 Us 0, Vs 0,U 00, i 2, Cd 0

2 0 00 0

ZY02 i i 1 1 03,Z3 dshr(CdUV), dshr(Y), goto 2 0 00 0x 01

ZY0 2 CdU CdU+ X,Yd0 Yd0 1, goto 2

0 39 00 1

ZY02 i i 1 0 1

3,Z3 dshr(CdUV), dshr(Y),FINISH 1

0 03 90 1

Result: -39-10 = +390

25.


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26. G'1:Us Us Xs, Ys Us XsG1:FINISH 1, OVERFLOW 12:Y 0, Cd 0, OVERFLOW 0, i n3:dshl CdUV, dshl Y, i i 1

(Z'cd+ G)4:Y0 Y0 + 1, CdU CdU+ X+ 1, goto 4ZcdG'Z'4:goto 3

ZcdG'Z4:FINISH 1

27. 11:CdU CdU+ X+ 1 (Note: X+ 1 = 967, not 67)12:U U+ X

Z'cd12:FINISH 1, OVERFLOW 1Zcd12:Us Us Xs, Ys Us Xs

2:Y 0, OVERFLOW 0, i n3:dshl CdUV, dshl Y, i i 141:CCdU CdU+ X+ 1

C42:Y0 Y0 + 1, CdU CdU+ X+ 1, goto 42C'42:CdU CdU+ X

Z'C'42:goto 3ZC'42:FINISH

1

28. a) 20 ns

b) 220

1510151 =++

==k

T

TS

c) n * 40 > 20 * (n + 2), which yields n> 2

d) 5.1)2(2

40*=

+n

n, which yields n = 6

29. Addresses xxx000 xxx001 xxx010 xxx011 xxx100 xxx101 xxx110 xxx111

0-7 0 0 0 0 0 0 0 0

8-15 0 1 2 3 4 5 6 716-23 0 2 4 6 8 10 12 14

24-31 0 3 6 9 12 15 18 21

32-39 0 4 8 12 16 20 24 28

40-47 0 5 10 15 20 25 30 35

48-55 0 6 12 18 24 30 36 42

56-63 0 7 14 21 28 35 42 49


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32.


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6. Only changes shown

Instruction Address bits Data 1 Data 2 Valid Comments

LDAC 4234 000 0000 0000 0000

000 0000 0000 0001

010 0001 0001 1010

01

42

55

34

0B

29

1

1

1

CLAC No changes Cache hitJMPZ 000A 000 0000 0000 0010

000 0000 0000 0011

06

00

0A

05

1

1

INAC 000 0000 0000 0101 0A 03 1

MVAC No changes Cache hit

ADD 000 0000 0000 0110 08 02 1

STAC 0927

000 0000 0000 0111000 0100 1001 0011

29--

0902

11

Cache hit

(opcode)

JUMP 0000 000 0000 0000 1000

000 0000 0000 1001

05

00

00

--

1

1


Instruction Address b its Tag Data Valid Dirty Comments

LDAC 4234 01

2

4

000000

000

423

0134

42

55

11

1

1

00

0

0

CLAC 3 000 0B 1 0

JMPZ 000A 45

6

000000

000

060A

00

11

1

00

0

Replace data

INAC A 000 0A 1 0

MVAC B 000 03 1 0

ADD C 000 08 1 0

STAC 0927 DE

F

7

000000

000

092

0227

09

02

11

1

1

00

0

1

JUMP 0000 0

1

2

001

001

001

05

00

00

1

1

1

1

1

1

Replace data

Replace data

Replace data


Instruction Address bits Tag Data 0 Data 1 Data 2 Data 3 Valid Dirty Comments

LDAC 4234 0

1

000

423

01

55

34

29

42

--

0B

--

1

1

0

0

CLAC No changes Cache hit

JMPZ 000A 1 000 06 0A 00 05 1 0 Replace data

INAC 2 000 00 00 0A 03 1 0

MVAC No changes Cache hit

ADD 3 000 08 02 27 09 1 0

STAC 0927

1 092 -- -- -- 02 1 1

Cache hit (instr)

Replace data

JUMP 0000 0 001 05 00 00 -- 1 0 Replace data


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Instruction Address bits Tag 1 Data 1 Valid 1 Dirty 1 Tag 2 Data 2 Valid 2 Dirty 2 Comments

LDAC 4234 0

1

2

4

000

000

000

423

01

34

42

55

1

1

1

1

0

0

0

0CLAC 3 000 0B 1 0

JMPZ 000A 4

5

6

423

000

000

55

0A

00

1

1

1

0

0

0

000 06 1 0

INAC A 000 0A 1 0

MVAC B 000 03 1 0

ADD C 000 08 1 0

STAC 0927 D

E

F

7

000

000

000

092

02

27

09

02

1

1

1

1

0

0

0

1

JUMP 0000 0

12

000

000000

01

3442

1

11

0

00

001

001001

05

0000

1

11

0

00


Instruction Address bits Tag 1 Data 1 Valid 1 Dirty 1 Tag 2 Data 2 Valid 2 Dirty 2 Comments

LDAC 4234 0

1

2

000

000

423

01/34

42/0B

55/29

1

1

1

0

0

0

CLAC No change Cache hit

JMPZ 000A 2

3

423

000

55/29

00/05

1

1

0

0

000 06/0A 1 0

INAC 5 000 0A/03 1 0

MVAC No change Cache hitADD 6 000 08/02 1 0

STAC 0927

7

3

000

000

27/09

00/05

1

1

0

0 092 --/02 1 1

Hit (instr)

JUMP 0000 0

1

000

000

01/34

42/0B

1

1

0

0

001

001

05/00

00/--

1

1

0

0

11. Only changes shown Note: Both LRU and FIFO replacement policies replace thesame values for this program.

Instruction Address Tag1 Data1 Valid1 Dirty1 Tag2 Data2 Valid2 Dirty2 Comments

LDAC 4234 0

1

000

423

01/34/42/0B

55/29/--/--

1

1

0

0CLAC No change Cache hit

JMPZ 000A 1 423 55/29/--/-- 1 0 000 06/0A/00/05 1 0

INAC 2 000 00/00/0A/03 1 0

MVAC No change Cache hit

ADD 3 000 08/02/27/09 1 0

STAC 0927

1

423 55/29/--/-- 1 0

092

--/--/--/02

1 1

Hit (instr)

Replace

JUMP 0000 0 000 01/34/42/0B 1 0 001 05/00/00/-- 1 0


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14. Hit ratio = 4.5%

Instruction Address Tag Data Valid Dirty Comments

LDAC 4234 0

1

2

4

000

000

000

423

01

34

42

55

1

1

1

1

0

0

0

0STAC 4235 3

45

5

000

000000

423

0B

3542

55

1

11

1

0

00

1

Replaces data

Replaces data

MVAC 6 000 03 1 0

INAC 7 000 0A 1 0

ADD 8 000 08 1 0

JPNZ 0020 9

A

B

000

000

000

07

20

00

1

1

1

0

0

0

LDAC 4235 0

1

2

002

002

002

01

35

42

1

1

1

0

0

0

Replaces data

Replaces data

Replaces dataHit (read from 4235)

JUMP 0029 3

4

5

002

002

002

05

29

00

1

1

1

0

0

0

Replaces data

Replaces data

Replaces data

AND 9 002 0C 1 0 Replaces data

15. Hits in italics Hit ratio = 50.0%

Instruction Address Tag Data Valid Dirty Comments

LDAC 4234 0

12

000

000423

01/34

42/0B55/--

1

11

0

00

Hit (34)

STAC 42352

2

000

423

35/42

55/55

1

1

0

1

Hit (STAC)Hit (42) - Replaces data

Hit (4235) Replaces data

MVAC 3 000 03/0A 1 0

INAC Hit (INAC)

ADD 4 000 08/07 1 0

JPNZ 0020

5 000 20/00 1 0

Hit (STAC)

Hit (00)

LDAC 4235 0

1

002

002

01/35

42/05

1

1

0

0

Hit (35) - Replaces data

Replaces data

Hit (4235)

JUMP 0029

2 002 29/00 1 0

Hit (JUMP)

Hit (00) - Replaces data

AND 4 002 00/0C 1 0 Replaces data


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23. (Only changes shown)Address Frame Valid Comments

LDAC 4234 0 0 1

4 1 1

JUMP 1000 No changes

STAC 4235 1 2 1 4235 already in memory


JUMP 0010 2 3 1


JUMP 0100 3 0 1

0 0 0

JUMP 1100 0 1 0

24. LDAC 4234JUMP 1000

STAC 4235

JUMP 2000

JUMP 0010 JUMP 3000 JUMP 0100 JUMP 1100

P F V P F V P F V P F V P F V P F V

0 0 1 1 2 1 1 2 1 0 0 1 3 0 1 3 0 1

4 1 1 4 1 1 2 3 1 2 3 1 2 3 1 0 1 1

25. LDAC 4234JUMP 1000

STAC 4235

JUMP 2000

JUMP 0010 JUMP 3000 JUMP 0100 JUMP 1100

P F V P F V P F V P F V P F V P F V

0 0 1 1 2 1 1 2 1 0 0 1 3 0 1 3 0 1

4 1 1 4 1 1 2 3 1 2 3 1 2 3 1 0 1 1

26. a) 1554Hb) 2000H

c) Fault

27. a) F231H

b) Faultc) 4401H

28. a) 1C35H

b) 0A38Hc) Fault

29. a) C543Hb) 4077H

c) 8401H

30. a) 2000H

b) 0D61Hc) 3FFFH


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31. a) 9512H

b) 3456Hc) 63EDH

32. a) 2 C 1

b) 9 6 1

c) E A 1


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Chapter 10

1.

2.

3.

OTPT1:DR M,PC PC+ 1, AR AR+ 1OTPT2: TR DR,DR M,PC PC+ 1OTPT3:AR DR,TROTPT4:DR ACOTPT5: Output port DR

3. Add the following connections using the same decoder used to generate the states of the INPT executeroutine. The rest of the circuit is unchanged.


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5. MEMBUS = (old value of MEMBUS) INPT1 INPT2 INPT4PCINC = (old value of PCINC) INPT1 INPT2TRLOAD = (old value of TRLOAD) INPT2ARLOAD = (old value of ARLOAD) INPT3DRHBUS = (old value of DRHBUS) INPT3TRBUS = (old value of TRBUS) INPT3DRLBUS = (old value of DRLBUS) INPT5

6. The control unit changes are the same as for Problem 10.4. The control signal changes are as follows.

ARINC = (old value of ARINC) OTPT1MEMBUS = (old value of MEMBUS) OTPT1 OTPT2BUSMEM = (old value of BUSMEM) OTPT5PCINC = (old value of PCINC) OTPT1 OTPT2TRLOAD = (old value of TRLOAD) OTPT2ARLOAD = (old value of ARLOAD) OTPT3DRHBUS = (old value of DRHBUS) OTPT3TRBUS = (old value of TRBUS) OTPT3

DRLBUS = (old value of DRLBUS) OTPT5

7. i) Modify the mapping function to map instruction code 0010 0000 to microcode address 100 0000.ii) Add microcode signalIO, which is 1 only for the microinstruction at address 67.iii) Add the following microinstructions to memory. (Only active control signals are shown.)

64: DRLOAD, MEMBUS, PCINC, ARINC U J 6565: TRLOAD, DRLOAD, MEMBUS, PCINC U J 66

66: ARLOAD, DRHBUS, TRBUS U J 67

67: DRLOAD, MEMBUS U J 68

68: ACLOAD, DRLBUS U J 01

8. i) Modify the mapping function to map instruction code 0010 0001 to microcode address 100 1000.

ii) Add microcode signalIO, which is 1 for the microinstruction at address 76.iii) Add the following microinstructions to memory. (Only active control signals are shown.)

72: DRLOAD, MEMBUS, PCINC, ARINC U J 73

73: TRLOAD, DRLOAD, MEMBUS, PCINC U J 74

74: ARLOAD, DRHBUS, TRBUS U J 75

75: DRLOAD, ACBUS U J 76

76: BUSMEM, DRLBUS U J 01

9. Time (ns) 0 10 20 40 45 60 80 85 90 100Routine MAIN IRQ1 IRQ2 IRQ1 IRQ3 IRQ4 IRQ3 IRQ1 MAIN

10. Time (ns) 0 10 30 50 70 90 100

Routine MAIN IRQ6 IRQ5 IRQ4 IRQ3 MAIN

11. Time (ns) 0 10 20 40 50 60 80 90 100

Routine MAIN IRQ4 IRQ6 IRQ4 IRQ1 IRQ3 IRQ1 MAIN

12. Daisy chaining is easier to modify when it is necessary to add peripherals to a computer system. It alsorequires fewer pins on the CPU. Other points may also be considered for this question.


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18. i) Add the following hardware to implementINT.

ii) Change the following state signals:

FETCH1 = T0^ (IP' IE')FETCH2 = T1^ INT'

FETCH3 = T2^ INT'

iii) Add hardware to generate the following new state signals:

INT1 = T0^ (IP^ IE)

INT2 = T1^ INT

INT3 = T2^ INT

INT4 = T3^ INT

INT5 = T4^ INT

INT6 = T5^ INTINT7 = T6^ INT

iv) Modify the following internal control unit signals:

Decoder enable = (Old value of Decoder Enable) INT'Time counter CLR = (Old value of Time counter CLR) ^INT7

19. Replace state FETCH1 and its input and output arcs with the following.

20. IE^ IP^ FETCH1:AR SP(IE' IP') ^FETCH1:AR PCINT2 - INT7 are the same as in the chapter text.


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21. ARLOAD = (Original value ofARLOAD) INT1ARDEC= (Original value ofARDEC) INT3SPBUF= (Original value of SPBUF)INT1SPDEC= (Original value of SPDEC)INT2 INT3

DRLOAD= (Original value ofDRLOAD)INT2 INT4 INT6DRLBUS= (Original value ofDRLBUS) INT3 INT5 INT7PCHBUS= (Original value ofPCHBUS)INT2PCLBUS= (Original value ofPCLBUS)INT4PCLOAD= (Original value ofPCLOAD) INT7BUSMEM= (Original value ofBUSMEM) INT3 INT5

WRITE= (Original value of WRITE)INT3 INT5MEMBUS= (Original value ofMEMBUS) INT6

IACK= INT5 INT6

22.

23. LDAC 2000OTPT 8000

LDAC 2001

OTPT 8001

LDAC 2002

OTPT 8002

24. Replace the FETCH1 input to the OR gate which drives the INC signal of the Time Counter withFETCH1 ^BR'.

25. No changes are required, since the CPU does not interact with the data bus while a DMA transfer is active.

26. i) COH 10H 00H 00H 20H 99H 00Hii) C1H 11H 00H 08H 28H 99H 01H

iii) C0H 10H 80H 00H 01H 99H 02H

27. a) 1 start + 0 parity + 1 stop bits = 2 bits overhead; 2 (2 + 8) = 23.8%.b) 1 start + 1 parity + 2 stop bits = 4 bits overhead; 4 (4 + 7) = 36.4%.c) 1 start + 1 parity + 1 stop bits = 3 bits overhead; 3 (3 + 5) = 37.5%.

28. a) Asynchronous: 2 (2 + 8) = 20.0%; HDLC: 48 (48 + 96) = 33.3%; Asynchronous has less overheadb) Asynchronous: 2 (2 + 7) = 26.3%; HDLC: 48 (48 + 168) = 22.2%; HDLC has less overheadc) Asynchronous: 2 (2 + 8) = 20.0%; HDLC: 48 (48 + 192) = 20.0%; Both have the same overhead.

29. LDAC 1111OTPT 9800H

LDAC 1112HOTPT 9801H


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30. a) Token packet: 24 bitsData packet: 6168 bits

Handshaking packet: 8 bits

TOTAL: 6200 bits

b) 56 6200 = 0.90%c) 1536 (1 start bit + 8 data bits + 1 stop bit) = 15,360 bits


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Chapter 11

1. a) 25 ns 100% vs. (24 ns 99%) + (24 ns 4 instructions 1%) average time25 ns vs. 23.76 ns + 0.96 ns25 ns > 24.72 ns, therefore the second CPU has better performance

b) 25 ns 100% = (24 ns (100 - x)%) + (96 ns x%); x = 1.389%c) 25 ns 100% = (24 ns 99%) + (24 ns x instructions 1%); x = 5.167 instructionsd) x ns 100% = (24 ns 99%) + (96 ns 1%); x = 24.72 nse) 25 ns 100% = (x ns 99%) + (4x ns 1%); x = 24.272 ns

2. a) 15 ns 100% vs. (12 ns 98%) + (12 ns 6 instructions 2%) average time15 ns > 13.2 ns, therefore the second CPU has better performance

b) 15 ns 100% = (12 ns (100 - x)%) + (72 ns x%); x = 5%c) 15 ns 100% = (12 ns 98%) + (12 ns x instructions 2%); x = 13.5 instructionsd) x ns 100% = (12 ns 98%) + (72 ns 2%); x = 13.2 nse) 15 ns 100% = (x ns 98%) + (6x ns 2%); x = 13.636 ns

3. a) 18 ns 100% vs. (16 ns 96%) + (16 ns 5 instructions 4%) average time18 ns > 18.56 ns, therefore the first CPU has better performance

b) 18 ns 100% = (16 ns (100 - x)%) + (80 ns x%); x = 3.125%c) 18 ns 100% = (16 ns 96%) + (16 ns x instructions 4%); x = 4.125 instructionsd) x ns 100% = (16 ns 96%) + (80 ns 4%); x = 18.56 nse) 18 ns 100% = (x ns 96%) + (5x ns 4%); x = 15.517 ns

4. a) Clock period = 80 nsSteady state speedup = (40 + 80 + 50)/80 = 2.125

b) 160/80 = 2

5. a) Clock period = 60 nsSteady state speedup = (30 + 25 + 60 + 40)/60 = 2.583

b) 150/60 = 2.5

6. a) Clock period = 70 nsSteady state speedup = (20 + 25 + 20 + 70 + 40)/70 = 2.5

b) 160/70 = 2.286

7. a) Clock period = 50 nsSteady state speedup = (40 + 45 + 35 + 50)/50 = 3.4

b) 160/50 = 3.2

8. a) Clock period = 40 nsSteady state speedup = (30 + 25 + 20 + 40 + 40)/40 = 3.875

b) 150/40 = 3.75

9. a) Clock period = 45 nsSteady state speedup = (20 + 25 + 20 + 25 + 45 + 40)/45 = 3.889

b) 160/45 = 3.556

c) Combine stages 1 and 2, and combine stages 3 and 4


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16. a) 1:R1 R2+ R3 Stage\Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15N1:No-op 1 1 N1 N2 2 N3 N4 3 4 5 N5 N6 6

N2:No-op 2 - 1 N1 N2 2 N3 N4 3 4 5 N5 N6 6

2:R4 R1+ R2 3 - - 1 N1 N2 2 N3 N4 3 4 5 N5 N6 6N3:No-op 4 - - - 1 N1 N2 2 N3 N4 3 4 5 N5 N6 6

N4:No-op

3:R3 R1+ R44:R5 R2+ R65:R6 R1+ R2

N5:No-op

N6:No-op

6:R7 R5+ R6

b) 1:R1 R2+ R3 Stage\Cycle 1 2 3 4 5 6 7 8 9 10 114:R5 R2+ R6 1 1 4 N1 2 5 N2 3 6

N1:No-op 2 - 1 4 N1 2 5 N2 3 6

2:R4 R1+ R2 3 - - 1 4 N1 2 5 N2 3 65:R6 R1+ R2 4 - - - 1 4 N1 2 5 N2 3 6

N2:No-op3:R3 R1+ R46:R7 R5+ R6

c) 1:R1 R2+ R3 Stage\Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 152:R4 R1+ R2 1 1 S S 2 S S 3 4 5 S S 63:R3 R1+ R4 2 - 1 S S 2 S S 3 4 5 S S 64:R5 R2+ R6 3 - - 1 S S 2 S S 3 4 5 S S 65:R6 R1+ R2 4 - - - 1 S S 2 S S 3 4 5 S S 66:R7 R5+ R6

d) 1:R1 R2+ R3 Stage\Cycle 1 2 3 4 5 6 7 8 92:

R4 R1+ R21 1 2 3 4 5 6

3:R3 R1+ R4 2 - 1 2 3 4 5 64:R5 R2+ R6 3 - - 1 2 3 4 5 65:R6 R1+ R2 4 - - - 1 2 3 4 5 66:R7 R5+ R6


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17. a) 1:R1 R2+ R3 Stage\Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16N1:No-op 1 1 N1 N2 2 N3 N4 3 4 5 N5 N6 6

N2:No-op 2 - 1 N1 N2 2 N3 N4 3 4 5 N5 N6 6

2:R4 R1+ R2 3 - - 1 N1 N2 2 N3 N4 3 4 5 N5 N6 6N3:No-op 4 - - - 1 N1 N2 2 N3 N4 3 4 5 N5 N6 6

N4:No-op 5 - - - - 1 N1 N2 2 N3 N4 3 4 5 N5 N6 6

3:R3 R1+ R44:R5 R2+ R65:R6 R1+ R2

N5:No-op

N6:No-op

6:R7 R5+ R6

b) 1:R1 R2+ R3 Stage\Cycle 1 2 3 4 5 6 7 8 9 10 11 124:R5 R2+ R6 1 1 4 N1 2 5 N2 3 6

N1:No-op 2 - 1 4 N1 2 5 N2 3 6

2:R4 R1+ R2 3 - - 1 4 N1 2 5 N2 3 65:R6 R1+ R2 4 - - - 1 4 N1 2 5 N2 3 6

N2:No-op 5 - - - - 1 4 N1 2 5 N2 3 63:R3 R1+ R46:R7 R5+ R6

c) 1:R1 R2+ R3 Stage\Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 162:R4 R1+ R2 1 1 S S 2 S S 3 4 5 S S 63:R3 R1+ R4 2 - 1 S S 2 S S 3 4 5 S S 64:R5 R2+ R6 3 - - 1 S S 2 S S 3 4 5 S S 65:R6 R1+ R2 4 - - - 1 S S 2 S S 3 4 5 S S 66:R7 R5+ R6 5 - - - - 1 S S 2 S S 3 4 5 S S 6

d) 1:R1 R2+ R3 Stage\Cycle 1 2 3 4 5 6 7 8 9 10

2:R4 R1+ R2 1 1 2 3 4 5 63:R3 R1+ R4 2 - 1 2 3 4 5 64:R5 R2+ R6 3 - - 1 2 3 4 5 65:R6 R1+ R2 4 - - - 1 2 3 4 5 66:R7 R5+ R6 5 - - - - 1 2 3 4 5 6


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18. a) 1:R1 R2+ R3 Stage\Cycle 1 2 3 4 5 6 7 8 9 10N1:No-op 1 1 N1 2 3 4 N2 5 6

2:R1 R1+ R2 2 - 1 N1 2 3 4 N2 5 63:R2 R3+ R4 3 - - 1 N1 2 3 4 N2 5 64:R5 R6+ R7

N2:No-op

5:R5 R5+ R76:R6 R1+ R2

b) 1:R1 R2+ R3 Stage\Cycle 1 2 3 4 5 6 7 83:R2 R3+ R4 1 1 3 4 2 5 64:R5 R6+ R7 2 - 1 3 4 2 5 62:R1 R1+ R2 3 - - 1 3 4 2 5 65:R5 R5+ R76:R6 R1+ R2

c) 1:R1 R2+ R3 Stage\Cycle 1 2 3 4 5 6 7 8 9 102:R1 R1+ R2 1 1 2 3 S 4 5 S 63:R2 R3+ R4 2 - 1 2 3 S 4 5 S 64:R5 R6+ R7 3 - - 1 2 3 S 4 5 S 65:R5 R5+ R76:R6 R1+ R2

d) 1:R1 R2+ R3 Stage\Cycle 1 2 3 4 5 6 7 82:R1 R1+ R2 1 1 2 3 4 5 63:R2 R3+ R4 2 - 1 2 3 4 5 64:R5 R6+ R7 3 - - 1 2 3 4 5 65:R5 R5+ R7

6:R6 R1+ R2


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19. a) 1:R1 R2+ R3 Stage\Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13N1:No-op 1 1 N1 N2 2 3 4 N3 N4 5 6

N2:No-op 2 - 1 N1 N2 2 3 4 N3 N4 5 6

2:R1 R1+ R2 3 - - 1 N1 N2 2 3 4 N3 N4 5 63:R2 R3+ R4 4 - - - 1 N1 N2 2 3 4 N3 N4 5 64:R5 R6+ R7

N3:No-opN4:No-op

5:R5 R5+ R76:R6 R1+ R2

b) 1:R1 R2+ R3 Stage\Cycle 1 2 3 4 5 6 7 8 9 10 113:R2 R3+ R4 1 1 3 4 N1 2 5 N2 64:R5 R6+ R7 2 - 1 3 4 N1 2 5 N2 6

N1:No-op 3 - - 1 3 4 N1 2 5 N2 6

2:R1 R1+ R2 4 - - - 1 3 4 N1 2 5 N2 65:R5 R5+ R7

N2:No-op

6:R6 R1+ R2

c) 1:R1 R2+ R3 Stage\Cycle 1 2 3 4 5 6 7 8 9 10 11 12 132:R1 R1+ R2 1 1 2 S S 3 4 S S 5 63:R2 R3+ R4 2 - 1 2 S S 3 4 S S 5 64:R5 R6+ R7 3 - - 1 2 S S 3 4 S S 5 65:R5 R5+ R7 4 - - - 1 2 S S 3 4 S S 5 66:R6 R1+ R2

d) 1:R1 R2+ R3 Stage\Cycle 1 2 3 4 5 6 7 8 92:R1 R1+ R2 1 1 2 3 4 5 63:R2 R3+ R4 2 - 1 2 3 4 5 6

4:R5 R6+ R7 3 - - 1 2 3 4 5 65:R5 R5+ R7 4 - - - 1 2 3 4 5 66:R6 R1+ R2


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20. a) 1:R1 R2+ R3 Stage\Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14N1:No-op 1 1 N1 N2 2 3 4 N3 N4 5 6

N2:No-op 2 - 1 N1 N2 2 3 4 N3 N4 5 6

2:R1 R1+ R2 3 - - 1 N1 N2 2 3 4 N3 N4 5 63:R2 R3+ R4 4 - - - 1 N1 N2 2 3 4 N3 N4 5 64:R5 R6+ R7 5

computer system architecture -john d carpinelli

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