conceptual llrf design for 1.3ghz superconducting cavity
DESCRIPTION
Conceptual LLRF design for 1.3GHz superconducting cavity. Qiu Feng ( PH.D Student ) LLRF members : Wang Guang wei, Sun YI Liu Rong, Zeng Ri hua, Qiu Feng Lin Hai ying, Wang Qun yao Mini-workshop of 1.3GHz/9cell superconducting cavity IHEP Dec. 2 2009. Content. - PowerPoint PPT PresentationTRANSCRIPT
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Conceptual LLRF design for1.3GHz superconducting cavity
Qiu Feng ( PH.D Student )LLRF members :
Wang Guang wei, Sun YI Liu Rong, Zeng Ri hua, Qiu Feng Lin Hai ying, Wang Qun yao
Mini-workshop of 1.3GHz/9cell superconducting cavity
IHEP Dec. 2 2009
![Page 2: Conceptual LLRF design for 1.3GHz superconducting cavity](https://reader033.vdocument.in/reader033/viewer/2022061603/568134f4550346895d9c3c0f/html5/thumbnails/2.jpg)
• 1. Target and the whole Block Diagram
• 2. Signal and Clock
• 3. RF Down-Conversion and Up-Conversion
• 4. Algorithm
Content
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• 1. Requirements on field stability (approximately RMS requirements)
0.1% for Amplitude and 0.1° for Phase
• 2. Chain secure
• 3. Take fully advantages of DSP technology
1. Target and the whole Block Diagram
![Page 4: Conceptual LLRF design for 1.3GHz superconducting cavity](https://reader033.vdocument.in/reader033/viewer/2022061603/568134f4550346895d9c3c0f/html5/thumbnails/4.jpg)
1. Target and the whole Block Diagram
LO
Vref
IF
DA
1
Am
p&P
hase
NC
O1
outp
ut
NC
O2
outp
ut
RF
LO
Sample
1300MHz
10M
Hz
refe
renc
e
1301MHz
240MHz
FPGA
NET ROMUSB
PC
ADC
ADC
ADC
ADC
120MHz
Vcav_in-
Vcav_in+
Sample
Down Conversion
Signal & Clock
Amp&Phase ModulatorRF
LO
Clock
1
2
3
4ADC ClockDAC Clock
120MHz
Cal
ibra
tio
n
Digital Board
Monitor
MotorDriver
M
RF Interlock
Piezo Driver
FeedForward Table
A&P_Set Table
Beam Table Test Table
Interlock Interface
Motor Control
Piezo Control
Vload+
Vload-
Klystron
Vkly-Vkly+
Monitor
ADC
ADC
ADC
ADC
Vcav_in-
Vcav_in+
Vload+
Vload-
Vkly-
Vkly+
Vcav_out
Vcav_out
Vref
Monitor
Monitor
Monitor
Monitor
Monitor
Monitor
Monitor
Monitor
Cavity Model&Tuner
LLRF Switch
30MHz
1330MHz 1300MHz
30MHz 30MHz
1MHz
1MHz
1MHz
Klystron
DA
1
DA
1
5
6
7
8
1
2
3
4
5
6
7
8
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• 1. Super-Sampling
• LO: 1301MHz
• Sampling Clock: 100MHz
• 2. RF signal and Sampling Clock
• RF signal source: 8663A
• (0.1MHz~2560MHz).
• Sampling Clock: 33220A
• Reference signal : 10MHz
2. Signal and Clock
![Page 6: Conceptual LLRF design for 1.3GHz superconducting cavity](https://reader033.vdocument.in/reader033/viewer/2022061603/568134f4550346895d9c3c0f/html5/thumbnails/6.jpg)
2. Signal and Clock
• How to generate the Local Frequency?
• The AD9858 can generate the 101MHz signal with its Clock(1300MHz RF signal).
• After twice frequency Mixing, we can get the 1301MHz Local signal, then we can obtain the 1MHz IF signal by mixing the RF and LO.
![Page 7: Conceptual LLRF design for 1.3GHz superconducting cavity](https://reader033.vdocument.in/reader033/viewer/2022061603/568134f4550346895d9c3c0f/html5/thumbnails/7.jpg)
2. Signal and Clock
The overall diagram of Clock structure
8663A
33220A
AD9858
RF
LO
Sample/ADC Clock
1300MHz
10MHz
10M
Hz
refe
renc
e
101MHz
1301MHz
1300MH
z
100MH
z
33220A12MHz
240MHz
120MHz DAC Clock
120MHz
TA1077A(1420M)
TA0840A(1300M)
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3. RF down conversion and up conversion
• Analog down conversion
ADC
ADC
ADC
ADC
Monitor
ADC
ADC
ADC
ADC
Vcav_in-
Vcav_in+
Vload+
Vload-
Vkly-
Vkly+
Vcav_out
Vref
Monitor
Monitor
Monitor
Monitor
Monitor
Monitor
Monitor
Monitor
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3. RF receiver
• Analog up conversion
DA
1
DA
2
RF RF
Amp Control
Phase Control
NCO1 output
NCO2 output
30M(BLP30+) 30M(BLP30+)
1330M(TA0375A)
SAW SAW
1300M(TA0840A)
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4. Algorithm
• Digital down conversion
• How to generate IQ?
• Scheme1(experienced)
![Page 11: Conceptual LLRF design for 1.3GHz superconducting cavity](https://reader033.vdocument.in/reader033/viewer/2022061603/568134f4550346895d9c3c0f/html5/thumbnails/11.jpg)
4. Algorithm
• Feedback Algorithm
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4. Algorithm
Simulink of 500MHz experiment
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4. Algorithm
• Feedforward Compensation
• The feed forward can supplement the feedback. it can suppress the known repetitive error.
![Page 14: Conceptual LLRF design for 1.3GHz superconducting cavity](https://reader033.vdocument.in/reader033/viewer/2022061603/568134f4550346895d9c3c0f/html5/thumbnails/14.jpg)
4. Algorithm
• Digital up Conversion
• Scheme1(experienced)
Cordic
NCO1
NCO2
Amp Word
Pha Word
DA1
DA2
I
Q
PI
PI
![Page 15: Conceptual LLRF design for 1.3GHz superconducting cavity](https://reader033.vdocument.in/reader033/viewer/2022061603/568134f4550346895d9c3c0f/html5/thumbnails/15.jpg)
4. Algorithm
• Digital up Conversion
• Scheme2
DA1
PI
PI
NCO1IF
![Page 16: Conceptual LLRF design for 1.3GHz superconducting cavity](https://reader033.vdocument.in/reader033/viewer/2022061603/568134f4550346895d9c3c0f/html5/thumbnails/16.jpg)
4. Algorithm
• Tuner control
Error Source speed solution
Micro-Phonics
slow feedback
Beam Loading
slow feed forward + feedback
Lorentz De-tuning
fast feedback
The cause of de-tuning
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4. Algorithm
• Tuner control
• For CW working mode , the diagram above is appropriate , for pulse working mode, the table test need to be done in the near future.