Continuous-Time Digital Signal Processing Based

Controller for High-Frequency DC-DC ConvertersZhenyu Zhao, Vadim Smolyakov and Aleksandar Prodic

ECE Department, University of Toronto10 King's College Road, Toronto, ON, M5S 3G4, CANADA

E-mail: Zhenyu@ power.utoronto.ca, vsmolyakov@ hotmail.com, prodic @power.utoronto.ca

Abstract- This paper introduces a digital dual-modecontroller for low-power high-frequency dc-dc switch-mode power supplies (SMPS) suitable for on-chipimplementation. In steady state the controller behaves as aconventional digital PWM controller, and during transientsit utilizes continuous-time digital signal processing toachieve very fast transient response. The continuous timeDSP is triggered by a sudden change of output voltage.Then it performs a charge-balance based algorithm toachieve voltage recovery through a single on-off action ofthe power switch. The effectiveness of the method isdemonstrated on an experimental 5 V-to- 2V, 400 kHz,2.5 W buck converter that recovers voltage in the timeequivalent to 3 PWM switching cycles, approachingconverter physical limitations.

I. INTRODUCTION

Low power consumption and fast transient response areamong the most common requirements in low-power switched-mode dc-dc power supplies (SMPS) for handheld devices. Inanalog controller implementations such characteristics areachievable with various types of designs [1]-[2]. On the otherhand, even though advantages of digital control have beenrecognized (flexibility, design portability, simpleimplementation of power management techniques), they havenot been widely adopted in low-power systems. Most of theexisting low-power digital controllers still use simpleproportional-integral-derivative (PID) compensators with verylimited bandwidth. The bandwidth limitation is mostly causedby sampling effects and various delays introduced by thevoltage loop. As shown in [3] higher sampling frequencyallows limited expansion of the controller bandwidth, but at thesame time puts a requirement for a power hungrier analog-to-digital converter (ADC).

In analog implementations, nonlinear strategies, such ashysteresis control [1]-[2] show faster responses than linear PIDcompensators. However, in conventional hystereticimplementations the switching times are not optimized and insome cases, large overshoots and sags in output voltage due toa large amount of accumulated current in inductor could occur[4]. As a result the power stage components go through anextra stress and overdesign of the system is often required. In[4], an enhanced version of hysteresis control is proposedwhere optimal power switch on/off time is calculated fromcapacitor charge balance to prevent large overshoots. Itachieves steady state in one single switching cycle but still

requires costly and power consuming current sensing. Thismethod still suffers from the most common drawbacks ofanalog hysteresis control. The converter operates at a variableswitching frequency causing additional stress on componentsand undesirable noise.

Fast transient response can also be obtained with methodspresented in [5]-[6], which implement charge balance basedalgorithms. The presented systems are targeted for medium andhigher power applications, where complex calculations indigital domain are performed. The systems are based on amodification of digital current-mode PWM controller. Thesecontrollers result in very fast load transient responses, but alsorequire real-time inductor current sensing and a high-resolutionADC. The complexity of hardware requirements makes thisimplementation less suitable for low-power applications,operating at high switching frequencies.

In this paper, we introduce a digital controller that achievesvery fast transient responses without the need of currentsensing and can be implemented with fairly simplepower-efficient hardware. The controller, shown in Fig. 1,achieves low power consumption in steady state by using aPID compensator that does not change its states frequently.During transients, a novel continuous-time digital signal

Fig. 1 Digitally controlled SMPS with a dual mode controller usingcontinuous-time digital signal processing technique.

1-4244-0714-1/07/$20.00 C 2007 IEEE. 882

processor (CT-DSP) is used, to achieve very fastresponses. The CT-DSP instantaneously identiquantities needed for capacitor charge-balance calsuch as peak/valley voltage values and the time pointsthey occur. The capacitor charge-balance calculatioperformed with the assistance of look-up tables to (

the optimal on and off switching time for the controlleThe following section gives a brief review of the co

time digital signal processing concept and explains thof applying it to SMPS. In Section III we descrilcharge-balance based control algorithm utilizing thito improve controller responding speed while elimirneed of current sensing. The experimental setup atare presented in Section IV. Section V concludes the

II. CONTINUOUS-TIME DIGITAL SIGNAL PROCES

Continuous-time DSP concept, introduced by[7]-[9], is a means of performing digital signal pwithout conventional time sampling. Having nomakes the output of CT-DSP a function of continuThe typical setup of CT-DSP requires an asynchronor quantizer as its input port and a set of delay cellscontinuous input signal x(t) is quantized by the asyrADC with quantization levels qi, i=1,2...k, as shownthe output data b(t) has discrete amplitude valuesfunction of continuous time [8]. The signals are theninstantly with combinational logic.As an example, Fig.3 shows a typical block di

CT-DSP for a one-bit FIR filtering application. Analx(t) is quantized by an array of asynchronous compaia flash ADC. The digital output of each comparator:trigger a string of adjustable continuous-time delay cedelayed binary data is fed to combinational logic recFIR filter. The details of CT-DSP implementation canin [9].

It.

bk11(t)t

dynamicifies theLculations,s at which)n is thendetermine.d SMPS.)ntinuous-ie benefitsbe a news conceptlating thend resultspaper.

CT single-bit CT digital CT digitalDelay line multipliers adder

Fig. 3 A typical FIR filter structure realized by CT-DSP

In the context of SMPS control, the main advantage of non-;SING clocked CT-DSP is ability to instantaneously detect outputTsividis voltage changes and its values during transition period. The

Trocssing detection can be performed without aliasing and quantizationrocesslng errors [7] and it can be followed by immediate data processingsamptimg in digital domain. The quantization step in CT-DSP as well asous ADC propagation times of delay cells are chosen by the designer andouAOUS the continuous-time analog signal can be reconstructed from

,.rWhen a the states of delay cells. In addition, with the utilization of~chronousin Fig. 2, asynchronous comparators as quantizers it can be made veryn is. 2a power efficient. This is because asynchronous comparators canbut is be designed to consume power only during state transitions

processed [11]. In steady state the CT-DSP is practically inactive and

-agram ofconsumes no power.

log signal Because of the abovementioned advantages of CT-DSP, thelators,i.e.responding speed of SMPS controllers can be improvedraor'e significantly. For example, in a traditional PID compensator,

is used to output voltage change is detected with a certain delay, uponlls T. The periodic sample of the output is taken. In addition to that

ilibzg and processing of the sample takes certain amount of time and astrong reaction of the compensator is usually delayed byseveral switching cycles. On contrary, the CT-DSP basedcontroller detects the transient upon the triggering of any of itscomparators. Practically, at the point of triggering the exactoutput voltage is sensed without quantization error (i.e. it is thesame as the threshold of the comparator) and is processedinstantly by combinational logic so that accordance controlactions can be taken immediately. In addition, the processingof quantized signals in the digital domain preserves all the

_ t benefits of digital control.The implementation of CT-DSP has matured significantly

since it was first introduced. On-chip implementation and

t results have been reported in [9]. In this paper we show thatlow-power SMPS can also benefit from the utilization of thisnovel concept. As it will be shown soon, transients response

_ t limited by the size of output filtering components only can beut bits of achieved without paying a significant penalties in hardware(t). complexity and power consumption.

883

Fig. 2 Waveforms for analog input signal x(t) and two outpiasynchronous ADC as well as quantized input signal q

Li

III. DUAL-MODE CONTROLLER ARCHITECTURE

A. System Operation Overview

In this section, we present a dual-mode controller for effectiveand fast control of load transients. The controller consists of aslow PID compensator and CT-DSP structure. Fig. 1 shows theoverview of controller architecture. In steady-state the PIDcompensator, which is designed to be very power efficient [8],regulates the voltage. During transients, the CT-DSP on-offcontroller takes over and provides very fast responses. Basedon the error signal mode selection module determines the modeof operation.The PID compensator operates only when the error, e[n] iswithin ±3, while the on-off controller is in action when thatrange is exceeded. The PID law generates the duty cyclecontrol variable d[n] by summing the previously sampled errorvalues, e[n-1] and e[n-2] with the past output value d[n-1] [8]:

d[n] = d[n -1] + Ae[n] + Be[n -1] + Ce[n - 2] (1)where, A, B, and C are compensator coefficients.

The operation of the on-off CT-DSP controller is based onsimple capacitor charge-balance principle. It can be explainedby observing arbitrary heavy-to-light load transient waveformsof output voltage and inductor current, shown in Figs. 4 and 5.The controller response is divided into two phases. In the firstphase, upon the load transient, the CT-DSP turns the mainswitch M1 on (see Fig. 1) to accommodate the change in outputload. The first period is limited by the valley point, as shown inFig.4. At that time instant, local minimum is reached and theload current and inductor current are the same. In the secondphase the controller makes up for the charge lost in outputcapacitor. It calculates ton and toff sequence needed for thefastest possible compensation of the lost capacitor charge and

vout, V

2

1 05

40 5 5'1 5-2time (s)

53 54

x io4-

1n

176

1.4-

12

08

006

0-4

0-2

0

-0 -2 IJ5 5.O5 5.1 515 5.2 5-25

time (s) x 10-4

Fig. 5 A typical inductor current waveform of a light-to-heavy loadtransient response of the CT-DSP

delivers a smooth transition from the transient to steady-state.As soon as the second phase ends, the conventional PIDcompensator again takes over the control and ensures stableoperation. Similarly off-on sequence is used to controlheavy-to-light load change.

B. Charge-balance based Algorithm for Optimal On-OffTime Sequence Calculation

It has been shown in [5]-[6] that SMPS converters recoversfrom load variation in optimum time by employing a singlepower switch on-off (or off-on) action. In the presented papersa current measurement based computations are used. In here,we show how the calculations of the optimal time can be donewithout current sensing.The tonitoff sequence is calculated under the assumption that

the voltage dip during the transient is relatively smallcompared to regulated dc value (less than 10 %). The loadtransient triggers min/max module (Fig. 1), which finds thevalley and peak points (local minimum or maximum) of theoutput voltage. For the waveform of Fig.4, the valley is foundby examining the sign of the error signal and the change inslope of the output voltage reconstructed in CT-DSP delaylines. Once the valley is found, the amount of the lost/gainedcharge in output capacitor is obtained by:

Q=CAV (2)

40 5 5.1timhe (s)

5-2 5i3 54

:x lo-

Fig. 4 A typical light-to-heavy load transient response of the CT-DSPcontroller (output voltage).

where AV is the voltage deviation at the peak/valley point.

During "ton time" (see Fig.5) iL = iC + iload the change of IL XAiL equals approximately the change of capacitor current ic,Aic .

It should be noted that CT-DSP automatically detects thelocal minimum/maximum, as a mid-time point at which thelargest excitation of the output voltage has been detected.

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.(V9=V>

AV .:,,'allej)pointI t'IT.-; i .r

r' r 17~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

_ T rf

!I ........!...y

I u

Gctle dPlVe si al':

A..j .Lau.u .L&Lj. Lj.u.

. I

Thus, the amount of charge transferred to the capacduring ton and toff intervals can be described with the followequations:

Qt on

Qt off =

L'1

out dtdrL

itoring

(3)

(4)

where Vg and V0,t are input voltage and dc value of the outputvoltage, respectively.As demonstrated in Fig.5 the relation between to, and toff can beobtained geometrically, by knowing the input voltage value(we assume that the output voltage is known as the referencevoltage):

ton Qt- on vout (5)toff Qt offt VgVout

By combining (2), (3) and (4) we obtain the followingcondition for the charge balance.

Qt on + Qt off = Q = AVC (6)

or

to = LCVVOUt (7)n g g voutIt can be seen that (5) requires the knowledge of LC product,

Vg, as well as calculation of the radical. Inaccurate knowledgeof LC product value influences the performance of theproposed control algorithm. However, as it is shown in [10] theaccurate knowledge of LC and Vg can easily be obtained byperforming a simple limit-cycle oscillation based power stageidentification test. The calculation of the radical values isperformed using look-up tables.From (5) tof is obtained for each operating point. As soon as

toff interval ends, the control law is switched back to PID. Theinitial conditions for the PID compensator is reset to have allzero values for e[n-1] and e[n-2] and initial duty ratio equal toVou/Vg. Presumably, at this moment, the output voltage andinductor current are at their new steady state values, the smalldiscrepancy of duty ratio from its new steady state value willbe corrected by the PID control law without causing largeoutput deviations. This effect will be observed in next sectionwhere experimental results are shown.

IV. EXPERIMENTAL SYSTEM AND RESULTS

The proposed CT-DSP based high performance SMPScontroller of Fig 1 is implemented with a Cyclone II AlteraDE2 FPGA, and standard high speed comparators. Theprogrammable delay cells in CT-DSP are emulated on theFPGA board although they can also be implemented withsolid-state components. The experimental setup has aswitching frequency of 400 kHz, an output capacitor C = 20uFand an inductor L = lOuH.

First, to verify benefits of this method responses to light-to-heavy step load changes of a conventional PID compensatorand the proposed dual-mode controller are compared. The loadcurrent is stepped up from 0.2A to 1.2A. The output voltageresponses of the controlled buck converter as well as theinductor current waveforms in both cases are shown in Fig. 6and Fig. 7 respectively. It can be seen that the PID takes 60 us

8.......... ........ ...... ....... ....

1)~15m 2>15.OV/ ; 1iW3)VSi2.5OV~ 4) 1 1OA/

i f. .. i._ib[......diL

~ * HiOO~ w 3.16000. 4 0 I 1O

............

Fig. 6 PID controller response to a 0.2A->1.2A load step change. Thewaveforms from top to bottom are: output voltage v,,t(t) (150mV/div),inductor current jL(t) (lA/div), gate drive signal (2.5V/div) and loadchange command signal (5V/div) respectively. X-axis:20us/div.

Fig. 7 CT-DSP controller response to a 0.2A->1.2A load step change.The waveforms from top to bottom are: output voltage v0,t(t)(150mV/div), inductor current jL(t) (lA/div), gate drive signal(2.5V/div) and load change command signal (5V/div) respectively. X-axis:20us/div.

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Fig. 8 Enlarged view of CT-DSP controller response to a 0.2A->1.2Aload step change. X-axis:5us/div.

Fig. 9 PID controller response to a 1.2A->0.2A load step change. Thewaveforms from top to bottom are: output voltage v,,,(t) (15OmV/div),inductor current iL(t) (1A/div), gate drive signal (2.5V/div) and loadchange command signal (5V/div) respectively. X-axis:20us/div.

Fig.10 CT-DSP controller response to a 1.2A->0.2A load step change.The waveforms from top to bottom are: output voltage v,,,(t)(150mV/div), inductor current iL(t) (lA/div), gate drive signal(2.5V/div) and load change signal (5V/div) respectively. X-axis:20us/div.

to settle down and that maxim voltage deviation isapproximately 200 mV. The proposed controller on the otherhand recovers the output voltage in less than 10 us with100 mV voltage deviation. These values are limited only by thesize of LC components in the converter circuit. The currentwaveforms of Fig. 7 also show that at the end of the CT-DSPmode operation both the output voltage and inductor currentreach their steady states in the shortest time possible. After thecontrol is handed back to the PID controller, any imperfectionin the on/off time calculation is corrected without causing largevoltage overshoots. A closer view of the CT-DSP transientresponse is shown in Fig. 8. A single on-off action of thepower switch can be clearly observed.

Figures 9, 10 show load transient responses of the convertersubjected to a 1.2A-to-0.2A step load change with pure PIDcontrol and CT-DSP control respectively. Similarimprovements verifying effectiveness of this method can beobserved.

V. CONCLUSIONS

A new digital controller for low-power high-frequencySMPS suitable for low-power on-chip implementation ispresented. It utilizes continuous-time digital signal processingto obtain a power efficient architecture and very fast dynamicresponse. The controller architecture is successfully tested withan FPGA experimental system and dynamic responseapproaching physical limitations of the power stage is achieved.

REFERENCES

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[4] K. Leung, S. Chung, "Dynamic hysteresis band control of the buckconverter with fast transient response," IEEE Transactions on Circuitsand Systems - II: Express briefs, Vol. 52, No. 7, July 2005.

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[7] Y. Tsividis, "Digital signal processing in continuous time: a possibilityfor avoiding aliasing and reducing quantization error," Proc. In IEEEInternational Conference on Acoustics, Speech and Signal Processing,2004, Vol. 2, 17-21 May 2004, pp. 589-92.

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[9] Y. Tsividis, G. Cowan, Y. W. Li, and K. Shepard, "Continuous-TimeDSPs, Analog/Digital Computers and Other Mixed-Domain Circuits",Proc. ofESSCIRC, Grenoble, France, 2005. pp. 113-116

[10] Z. Zhao, H. Li, A. Feizmohammadi, A. Prodic, "Limit-Cycle BasedAuto-Tuning System for Digitally Controlled Low-Power SMPS", Proc.IEEEAPEC Conf. 2006, 19-23 March 2006, pp. 1143-1147.

[11] A. Tangel and K. Choi, " 'The CMOS Inverter' as a Comparator in ADCDesigns" Analog Integrated Circuits and Signal Processing, Vol. 39, No.2, May, 2004. pp. 147-155.

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