converter performance approaches

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40 www.rfdesign.com April 2007

Software Radio

Converter performance approachessoftware-defined radio requirementsWhile most of the technical bottlenecks to realizing true software-defined radiocan be found in the linear and mixed-signal processing components, recenttrends in ADCs and DACs have moved their levels of performance one stepcloser to achieving that goal.

By Brad Brannon

Until the late 1980s, military requirements tended to drivedata converter markets. Military needs were driven by radar,

communications applications and electromagnetic pulse detection.By 1991, a Mitre scientist, Joseph Mitola, foresaw that the majorityof a radio’s functionality in the not-too-distant future would be in

software rather than hardware, thereby enabling the transceiver to process multiple standards either in sequence or in parallel. By themid-1990s, semiconductor technology had reached the point wherecommercial interests drew these same conclusions and began seekingtechnology specifically for this purpose.

From a business point of view, cellular and other advanced consumer wireless growth further strengthened the demand for software-definedradio (SDR) technology. While there is still a gap in the required levelof performance for a generic SDR platform, many communicationsapplications have been slowly adopting various aspects of SDR. Theseinclude digital functions such as the modem, and usage of Internet protocol (IP) for streaming of real-time communications data. Bothof these can be changed in real time as the requirements dictate.Furthermore, the analog functionality of the transceivers has begunevolving into a structure that can simultaneously process entire bandsor frequency allocations. The result is a transceiver that can change

modulation characteristics without physical hardware changes, poten-tially handling multiple RF signals at the same time. The importanceof this is that as standards evolve, the hardware can remain the same,with only the software being updated. Indeed, the value added ismore often than not in the software, not in the hardware.

The demand for SDR goes beyond military applications to the heartof everyday communications. Standards such as GSM, 3G, WiMAXand future standards, are constantly evolving. This drives a churn of operating equipment at a time when operators are trying to containcapital expenses. Other standards beyond cellular are also changingincluding video (broadcast, cable and satellite) and audio services (AM,FM, HD radio and satellite standards). Equipment that can evolveas the standards do is highly valued at an industrial level as well asa consumer level.

Despite the quiet adoption of key techniques of SDR that wasaccelerated by DSP and FPGA developments, analog performance

gaps prevent full adoption and usage of SDR in many common appli-cations. While exact requirements depend on the application and designassumptions, the key requirements are improved noise performance andhigher intermodulation and spurious performance. While RF and linear devices have improved rapidly in recent years with the introductionof GaAs, SiGe and other advanced processes, mixed-signal devicessuch as ADCs and DACs have not improved quite as fast. For ADCsand DACs alike, the requirements are focused on noise and distortion.While ADCs most often focus on SNR and spurious-free dynamicrange (SFDR), DACs are often specified by noise spectral density(NSD), adjacent-channel leakage ratio (ACLR), or adjacent-channel power ratio (ACPR).

Performance bottlenecksConverter specifications encompass many important dimensions

of performance. In addition to noise and distortion, as previously

outlined, other requirements such as sample rate and bandwidthare important. Sample rates need to adequately match the application bandwidths to satisfy Nyquist. Beyond this, oversampling can beimportant as a way to drive down noise density, but is not strictlynecessary provided Nyquist is satisfied. Current sample rates andadvances in sample rate are on track with demands. Bandwidth, onthe other hand, is always less than required. New systems are alwayslooking for the ability to sample (in the case of the ADC) or synthe-size (in the case of the DAC) higher frequencies—not only for higher IFs, but also for direct-RF sampling and synthesis. Direct-RF samplingmay well be the key to greatly simplified systems and lower cost.

Operating data converters at high analog frequencies comes witha penalty. Noise and distortion performance is predictably worse dueto clock jitter and limited slew rate. Much of the innovation over thelast decade of high-speed converter development has focused onimproving the operation of converters at higher analog frequencies.

So, for example, while SFDR has not improved significantly over the last 10 years[1], input bandwidth has. As a result, converters arenow available that give IF performance that once was available onlyat baseband or low frequencies. Figure 1 shows the combined improve-ment in ADC bandwidth and SFDR. This chart clearly shows how performance for IF-sampling converters continues to improve.

Most high-speed ADCs use a capacitor to sample the input sig-nal. Doing so creates a natural filter composed of a resistor equalto the on resistance of the sample switch, and the sample capacitor.ADC bandwidth is, therefore, limited by the size of the capacitor,as shown in Equation 1. Making the capacitor smaller makes thecircuit easier to drive, increasing the bandwidth and improving

Figure 1. Industry improvements to ADC SFDR-bandwidth products by year.

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the spurious performance.

1

ADC BW

C ∝

eq 1

where BW is the converter bandwidth. This creates an interesting

trade off. In addition to improved spurious performance and a wider input bandwidth, the circuit allows more noise to pass to the samplecapacitor. This results in a lower ADC SNR due to increased inputnoise, as shown in equation 2.

ADC

kT noise

C ∝ eq 2

Despite this, SNR has remained relatively flat while input bandwidthhas increased, until recent years as noted in reference 1. ConvertingSNR to NSD by distributing the noise over the Nyquist bandwidthgenerates a key parameter used by system designers. The NSD of high-speed converters shows consistent improvement over time andresults in a steady growth of about 1 dB/Hz per year. This translatesinto improved receive sensitivity and results in more usable dynamicrange in the SDR design.

Required SFDR performanceWhat is needed from a wideband, high-speed ADC in order to

implement SDR in a general application? This is gated GSM, whichis generally considered to be the most demanding application. Thishappens to be a good reference point because the requirements for GSM are similar to that of a broadcast FM receiver in terms of band-width, sensitivity and rejection of blockers. These two would never be implemented together, but they represent two different applicationsthat possess similar requirements.

From prior analysis[2], NSD for GSM must be on the order of –157 dBm/Hz, or about 86 decibels full scale (dBFS), from atypical high-speed converter. Spurious performance needs to be about –110 dBFS. From Figures 1 and 2, it is apparent that the requiredlevel of performance is not yet available. However, it is clear thatthe trend is in the right direction and that the required performance

should be available in the next generation or so. In the mean time, products such as the AD9461 16-bit, 130 Msps pipelined ADCwill find use in many high-performance applications. In other applications, higher levels of integration are sought. Products suchas the AD6655 IF diversity receiver offer high-performance receiver functions, including ADCs, along with digital tuners and power detection to aid in AGC loop construction. Because of the widedynamic range required for SDR systems, AGC is very critical.On one sample, the input signals may be near the noise floor. Then,within a few samples, the input is driven fast toward the full scaleof the converter. An AGC loop is typically required to maintainthe largest signal possible on the input, yet must also respond to sud-den increases in signal level to prevent clipping of the receiver input.

Devices such as the AD6655 and AD9641 are designed to provide

advance notice so that loops can respond before signal integrity is lostor before the inputs are damaged.

From a DAC perspective, the key requirements are NSD andspurious products, specifically, those for continuous wave (CW), ACPR or ACLR. To meet emissions requirements, spurious products typicallyneed to be about –75 dBFS. Figure 3 shows that this is not a problemfor current-generation DACs. Noise, on the other hand, can be anissue. Because SDR applications tend to be wideband in nature, theoutput of the power amplifier must also be wideband. In addition, if the system employs digital pre-distortion, the output bandwidth must be as wide as the spurious products being corrected. Therefore, anynoise generated in the system will be amplified and presented at theoutput. Excess noise in the DAC would be passed to the antenna andtranslated as excess RF noise. Therefore, system noise, includingthat of the DAC, must be minimal. Current state-of-the art modula-

tors (used in direct launch transmit) have about –156 dBm or better output noise density. Ideally, the DAC should be at this level or belowto prevent a significant increase to overall system noise. From Figure4, DAC noise is clearly below that of modulators and mixers. Basedon current technology, DACs are much less a bottleneck to SDR than are ADCs.

Other improvementsIn addition to these improvements, other factors not only enhance

performance but also improve usability. Integration is playing asignificant factor in standard product converter enhancements.Recent years have seen added digital functions in ADCs andDACs. Not uncommon in converters are digital filters, interpolators,

Figure 2. Industry reductions in ADC noise spectral density by year. Figure 3. While improvements to DAC SFDR have recently tapered,performance is well above the –75 dBFS needed to meet typical emissionsrequirements.

Figure 4. Improvements to DAC noise spectral density have made the DACmuch less of a bottleneck to realizing true SDR than the ADC.

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decimators, numeric-controlled oscillators (NCOs) and other functions that aid in receive and transmit operations. NCOs and digitalfilters aid not only in the channelization of the signals, but facilitate block conversion. For example, NCOs in a DAC, when combinedwith interpolation, allow the original baseband signal to be translatedanywhere in the Nyquist band of the interpolated sample rate insteadof being confined by the original sample rate. New products suchas the AD9736 14-bit, 1200 MHz DAC are available with sample ratesin the gigahertz range, allowing synthesis of very high IF and, in somecases, direct-RF synthesis of transmitted signals. Similar featuresexist on ADCs. An on-chip NCO and demodulator can be usedto translate an arbitrary IF signal to be down-sampled to a digital baseband signal. Because the original signal is IF-sampled anddigitally converted to baseband, no quadrature error or dc-offset error

is introduced.An additional benefit to on-chip decimators on ADCs and interpola-tors on DACs is that the external interface speed can be considerablelowered. This allows slower logic families to be used and reducesswitching speed requirements, resulting in lower overall noise andspurious generated in the data converters and in the layout surround-ing them. The net results are often better performance of the overallsystem.

While a generic SDR solution is not yet available for completetransceivers, many of the aspects are being adopted in new transceiver designs. Despite current bottlenecks, the performance curves showthat converter performance has steadily improved and is within ageneration or two of meeting the required levels. At the same time,

levels of integration of these converters are increasing, not only tosimplify designs, but as a means to improve performance of theconverter as well as in the systems in which they reside. Next-generation converters will close the gap in performance as wellas functionality. RFD

References1. State of the Art in ADCs 2007, www.converter-radio.com.2. Multicarrier GSM Requirements, www.converter-radio.com.

Figure 5. Typical SDR transceiver architecture.

ABOUT THE AUTHOR

Brad Brannon is a systems applications engineer for the High-speedconverters group of Analog Devices. He has been with ADI since1984 and specializes in analog to digital converters and wirelesssystems. He graduated for NC State with a BS in electrical engi-neering in 1983.

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