coolrunner ™ -ii low cost solutions. quick start training introduction coolrunner-ii system level...

CoolRunner™-IILow Cost Solutions

Quick Start Training

Introduction• CoolRunner-II system level solution savings

• Discrete devices vs. CoolRunner-II

• ASIC vs. CoolRunner-II

• CoolRunner-II design tools– CoolRunner Reference Designs

– CoolRunner-II Design Kit

– Software

• Cost summary

CoolRunner-II System Level

Savings

File Number Here


System Integration Advantage


Xilinx CPLD Feature Comparison Feature CoolRunner-II XPLA3 9500XL/XV

Core Voltage 1.8 3.3 3.3/2.5

Low Power FZP plus DataGATE FZP Low power mode

Global Clock 3 4 3

P-Term Inputs 40 40 54

Clock ManagementDivide, DualEDGE &

CoolCLOCK None None

I/O StandardsLVTTL, LVCMOS,

HSTL, SSTLLVTTL, LVCMOS LVTTL, LVCMOS

I/O Banks 1 to 4 1 1 to 4 (XV) , 1 (XL)

Macrocells 32-512 32-512 36-288

tPD / Fmax 3.5 / 333 5 / 200 4.0 / 250

Security Multiple levels 1 level 1 level

Process Technology 0.18u 0.35u 0.35u / 0.25u


System Level Savings• High volume economies of scale

– Single chip for multiple system solutions• Increased volume means reduction in all related costs

• Reference designs– Minimize risk and shorten design cycles

• Lowest cost per I/O• On the Fly (OTF) Reconfiguration

– Two devices for the price of one


High Volume Economy of Scale• Single chip for multiple system solutions

– Speed, low power consumption and voltage translation in a single device

– Reduces the cost for multiple manufacturing flows and mask sets

• Volume discounts on fixed costs (packages and die)– Significantly reduces cost structure due to high run rates

• Single product family allows focused multi site usage model


Lowest Cost Per I/O

• Reduce risk of changing marketing feature requirements– Extra I/O lend helping hand to feature creep

• No need to pay for extra logic– Stay in the device that best fits your design– When all you need is more I/O - why pay for a larger device?


Price per I/O vs. Lattice ispMACH• CoolRunner-II saves you money over the competition

Device 2003 pricing Max I/O Cost per I/O Savings per deviceXC2C32 $ 1.40 33 $ 0.042 1 more I/O x 0.52 = $0.052 or $0.25

IspMACH4032 $ 1.65 32 $ 0.052

XC2C64 $ 3.35 64 $ 0.052 same I/O but save $0.34

IspMACH4064 $ 3.69 64 $ 0.058

XC2C128 $ 8.65 100 $ 0.0865 8 more I/O x 0.155 = $1.24 or $5.56

IspMACH4128 $ 14.30 92 $ 0.155

XC2C256 $ 19.15 184 $ 0.104 24 more I/O x 0.177 = $4.25 or $9.23

IspMACH4256 $ 28.38 160 $ 0.177

XC2C384 $ 47.55 240 $ 0.196 48 more I/O x 0.196 = $9.41

IspMACH4384 $ 37.68 192 $ 0.196

XC2C512 $ 63.20 270 $0.234 62 more I/O x 0.249 = $15.44

IspMACH4512 $ 51.70 208 $ 0.249

For each device density, the slowest speed, least expensive package with max I/O


Price per I/O vs. Altera 7000B• CoolRunner-II saves you money over the competition Device 2003 pricing Max I/O Cost per I/O Savings per device

XC2C32 $ 1.40 33 $ 0.042 1 more I/O x 0.52 = $0.052 or $0.75

EPM7032 $ 2.15 32 $ 0.067

XC2C64 $ 3.35 64 $ 0.052 same I/O but save $4.15

EPM7064 $ 7.50 64 $ 0.117

XC2C128 $ 8.65 100 $ 0.0865 4 more I/O x 0.155 = $0.54 or $4.35

EPM7128 $ 13.00 96 $ 0.135

XC2C256 $ 19.15 184 $ 0.104 24 more I/O x 0.175 = $4.20 or $8.85

EPM7256 $ 28.00 160 $ 0.175

XC2C384 $ 47.55 240 $ 0.196 No Altera competition at 384mc

- - - - -

XC2C512 $ 63.20 270 $0.234 62 more I/O x 0.644 = $39.94 or $70.80

EPM7512 $ 134.00 208 $ 0.644

For each device density, the slowest speed, least expensive package with max I/O


On the Fly (OTF) Reconfiguration

• Two devices for the price of one – On power up, the CPLD performs one function– When system is configured, CPLD performs system functions

• Personality daughter card solution– Use OTF feature to enable multi-function modes on a single daughter

card • After power-up function, re-program for specific personalities

CoolRunner-II vs.

Discrete Cost

File Number Here


Discrete Device Cost vs. CoolRunner-II

• Schmitt inputs– SNJ54LVC14AFK @ $9.50

• Voltage translation– SN74AVCAH164245 @ $2.46

• I/O standard translation– SN74HSTL16918DGGR @ $6.26

• Total cost @ $18.22

• CoolRunner-II 128mc device– With 80 I/O – Schmitt inputs– Voltage translation– I/O translation

• PLUS– Extra Logic– Re-programmable

• Total cost @ $8.00 56% less


Discrete Device Area vs. CoolRunner-II

• Schmitt inputs– SNJ54LVC14AFK @ 8.7 x 8.7 mm

(75.7mm2)

• Voltage translation– SN74ACVAH164245GR @ 12 x

6mm (72mm2)

• I/O standard translation– SN74HSTL16918DGGR @ 12 x

6mm (72mm2)

• Total area @ 220mm2

24mm2 more space

• CoolRunner-II 128mc device– XC2C128-4VQ100C @ 14 x

14mm (196mm2)

• Total area 196mm2


Discrete Device Pin Usage vs. CoolRunner-II

• Schmitt inputs– SNJ54LVC14AFK @ 20 pins with 6

outputs

• Voltage translation– SN74ACVAH164245GR @ 48 pins

with 16 outputs

• I/O standard translation– SN74HSTL16918DGGR @ 48 pins

with 9 outputs

• Total usable pins 31 of 108 (29% usage)

• CoolRunner-II 128mc device– XC2C128-4VQ100C

• Total usable pins 80 of 100 (80% usage)


Discrete Device Power Consumption vs. CoolRunner-II• Schmitt inputs

– SNJ54LVC14AFK @ 0.05mA

• Voltage translation– SN74ACVAH164245GR @

0.1mA

• I/O standard translation– SN74HSTL16918DGGR @ 50-

100mA

• Total power consumption ~ 50mA

• CoolRunner-II 128mc device– With 4 16 bit counters,

schmitt inputs, voltage translation and I/O translation at 50MHz = 6.8mA

– This power calculation is without DataGATE

• Total power consumption ~6.8mA


DataGATE Advantages at No Additional Cost

• Individual input pins can be shut off without powering down the device

• Reduces power– Does not toggle pins in a don’t care state

• Simplifies system or part debug– Helps isolate certain signals or pins at will

• Aids in hot plugging system boards– e.g., into a backplane


DataGATE - Ultimate Low Power Standby

• With DataGATE enabled, current consumption reduced from 3.37mA down to 70uA! (slot machine design example)


Discrete Device Routing & Layout vs. CoolRunner-II

• Multiple devices increase R&D and production costs– R&D costs

• PCB layout is more complex due to more routing– Routing is internal to CPLD

• Design costs increase due to increased time in design– Single chip design in high level design language

– Test and assembly costs• Functional testing cost is on a per device adder

– Single chip testing with built in JTAG• Assembly cost is on a per device adder

– Single chip stocking and assembly


Multi vs. Single Chip Cost Comparison

0

0.1

0.2

0.3

0.4

0.5

0.6

R&DTest

Assembly

Pin Count

AreaPower Consumption

CostDiscrete

Single Chip (CPLD)

Note: Estimated results normalized to one


Summary of Discrete Devices vs. CoolRunner-II

• Discrete devices– 3 devices– Total cost @ $18.22– Total area @ 220mm2

– Total usable pins 31 of 108

• CoolRunner-II– Single device– Total cost @ $8.00– Total area 196mm2

– Total usable pins 80 of 100– Lower power

• PLUS– Extra logic– Re-programmable

CoolRunner-II vs.

ASIC Cost

File Number Here


Product Unit Volume Dynamics

New products go to high volume quickly and have short product life cycles

1 Years in Production

1 millionunits

Cellular PC Games TVVolume

PDA

2


ASIC Development Takes Too Long!

• Short product life cycles limit ASIC usage– Multiple ASIC re-spins can leave little time to run in

production or completely miss the market window– ASICs are not re-programmable and do not allow last

minute design revision changes

• Smaller than expected run rates may not justify the ASIC development and NRE costs

CPLDs allow customers to address market and design changes quickly!


Short Product Life Limits ASICs

CPLDs are the quick Time To Market solution saving revenue

Years in Production

Volume

1

Cellular

PC

Games

TV

PDA

2

Short life cycle products need quick design times to meet tight market windows

ASIC development and re-spin delays can miss a major part of the production cycle resulting in lost revenue

ASICdelays

CoolRunner-II Quick Design

Tools

File Number Here


CoolRunner Reference Designs• Shorten design cycle time

– Eliminate code porting costs for next design cycle• Re-use of HDL is reliable and stable

• Minimize design risk by using reference designs– Availability of reference designs prepares you for unexpected system changes

• Update main processor but it does not incorporate correct bus interface

• Further improve customer’s Time To Market– Proven designs for quick turn requirements


Faster Designs with FREECoolRunner Reference Designs

Application Reference DesignReference

NumberLanguage Macrocell

Target Device

% Utilized

XPATH Module Design XAPP356 VHDL 225 XC2C384 58Springboard Module Design XAPP147 Pocket C, VHDL 67 XC2C128 528 Channel DVM Springboard XAPP146 Pocket C, VHDL 184 XC2C256 71

SECDED XAPP383 VHDL 66 XC2C128 52 N x N Crosspoint Switch XAPP380 VHDL 193 XC2C256 75

IrDA and UART XAPP345 VHDL or Verilog 87 XC2C128 67UARTs XAPP341 VHDL or Verilog 61 XC2C128 47

16b/20b Encoder/Decoder XAPP336 VHDL 76 XC2C128 59

SPI XAPP386 VHDL 128 XC2C256 50

Compact Flash Interface XAPPXXX VHDL XC2C128

I2C Bus Controller XAPP333 VHDL or Verilog 131 XC2C256 51

SMBus Controller XAPP353 VHDL 158 XC2C256 61

Manchester Encoder/Decoder XAPP339 VHDL or Verilog 55 XC2C64 85NAND Interface XAPP354 VHDL or Verilog 9 XC2C32 28

Interface to DDR SDRAM XAPP384 VHDL XC2C256Wireless Wireless Transceiver XAPP358 VHDL 156 XC2C256 60

Multimedia MP3 Player XAPP328 VHDL 219 XC2C256 868-bit Microcontroller XAPP387 VHDL & C 107 XC2C128 848-bit Microcontroller XAPP387 VHDL & C 212 XC2C256 83

8051 Microcontroller Interface XAPP349 VHDL 57 XC2C64 89Microcontroller

PDA

Datacom

Bus Interface

Memory

Free VHDL design code: www.xilinx.com/products/xaw/coolvhdlq.htm

Coming soon


CoolRunner-II Design Kit

• A complete, easy to use CoolRunner-II CPLD Design Kit– Logic designers new to CPLDs – CPLD designers new to Xilinx– ASIC designers not aware of CoolRunner-II advanced features

• Simple and inexpensive demo board ready to use– Battery or AC outlet power source– Inexpensive parallel printer cable for programming – LED's for simple testing– Dual in line I/O header for easy connections– Jumpers for easy modifications– Multiple device selection on a single board


CoolRunner-II Design Kit


Online Software Solutions

• Free WebFITTER™– Easily fit designs for all Xilinx CPLDs online– Accepts VHDL/verilog/abel & standard netlists– Simplepld & competitive conversions– Fitting & timing reports– Online price quotes for purchasing the best PLD silicon solution

• Free ISE 6.1i WebPACK™– Downloadable desktop solution– HDL / ABEL synthesis & simulation– JTAG & 3rd party EDA support– Supports all Xilinx CPLD families– Supports Spartan-II, IIE & 3, Virtex-E & II (up to 300K gates) FPGAs– Links to online purchasing


CoolRunner-II Cost Summary

• Lowest overall system cost• Single chip CPLD advantages over multiple

discrete chips• Re-programmable CPLD advantages over ASIC• Advanced features for free• Design faster using online software, reference

designs and design kits


One CPLD Solution for All Designs

Handheld, Portable Equipment

* Estimated 128 macrocell device,Eight 16-bit counters @ 50MHz

High Performance3.0ns tPD, fmax 385MHz

Improved features

Low Cost0.18µ = small die size

Lowest cost packaging

Lowest Power12mW*

~20uA typical stand-by

Storage Systems, Routers Set-Top Box, Cell Phone

coolrunner ™ -ii low cost solutions. quick start training introduction coolrunner-ii system level...

Documents

quick start training

max io slide

b coolrunner

space coolrunner

discrete device cost

single device

lattice ispmach coolrunner

discrete device area