cots journal september 2013

The Journal of Military Electronics & Computing

An RTC Group Publication

Volume 15 Number 9 September 2013 cotsjournalonline.com

Tech Focus: EBX, ETX and ITX SBC Roundup

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EXCLUSIVE: Designing at the System-to-System Level Part 1

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CONTENTS

COTS (kots), n. 1. Commercial off-the-shelf. Ter-minology popularized in 1994 within U.S. DoD by SECDEF Wm. Perrys Perry Memo that changed military industry purchasing and design guidelines, making Mil-Specs acceptable only by waiver. COTS is generally defined for technology, goods and services as: a) using commercial business practices and specifi-cations, b) not developed under government funding, c) offered for sale to the general market, d) still must meet the program ORD. 2. Commercial business practices include the accepted practice of customer-paid minor modification to standard COTS products to meet the customers unique requirements.

Ant. When applied to the procurement of electronics for the U.S. Military, COTS is a pro-curement philosophy and does not imply commer-cial, office environment or any other durability grade. E.g., rad-hard components designed and offered for sale to the general market are COTS if they were developed by the company and not under government funding.

The Journal of Military Electronics & ComputingThe Journal of Military Electronics & ComputingThe Journal of Military Electronics & Computing

Departments

Digital subscriptions available: cotsjournalonline.com

September 2013 Volume 15 Number 9

Coming in OctoberSee Page 48

6 Publishers Notebook Quantum Change on the Way

8 The Inside Track

44 COTS Products

50 Editorial Open Architectures Day in the Sun

TECHNOLOGY FOCUSEBX, ETX and ITX SBCs

38 Busless Embedded Form Factors Mean Tight SWaP Requirements Jeff Child

40 EBX, ETX and ITX Boards Roundup

SYSTEM DEVELOPMENTEXCLUSIVE: Designing at the System-to-System Level: The Industrys New Challenge

28 Innovative Systems and Standards Enable Efficient Ground Vehicle Networking Johnny Keggler

34 FACE Standard Brings Open Concepts to Airborne Platforms Jeff Child

TECH RECONVPX, VXS and VME FPGA Boards in Radar and SIGINT

24 Customized Approach Leverages OpenVPX Flexibility Brian Roberts, Dawn VME Products

SPECIAL FEATUREMilitary Storage Hierarchies: From RAID to SSDs

10 Military Demands a Whole Hierarchy of Storage Solutions Jeff Child

18 Cache Partitioning Enhances Multicore Performance Tim King, DDC-I

Military Storage Hierarchies: From RAID to SSDs10

On The Cover: Under development by the Air Force, Gorgon Stare is a video capture technology that makes use of many Terabytes worth of solid state disk storage. It is a spherical array of nine cameras attached to an MQ-9 Reaper UAV. The system is designed to do wide-area surveillance, which entails downloading many different images to a variety of military users for analysis. Shown here, an MQ-9 Reaper sits on the flightline at Creech Air Force Base. (U.S. Air Force photo/Lance Cheung)

COTS Journal | September 20134

PublisherPRESIDENT John Reardon, [email protected]

PUBLISHER Pete Yeatman, [email protected]

EditorialEDITOR-IN-CHIEF Jeff Child, [email protected]

SENIOR EDITOR Clarence Peckham, [email protected]

MANAGING EDITOR/ASSOCIATE PUBLISHER Sandra Sillion, [email protected]

COPY EDITOR Rochelle Cohn

Art/Production ART DIRECTOR Kirsten Wyatt, [email protected]

GRAPHIC DESIGNER Michael Farina, [email protected]

LEAD WEB DEVELOPER Justin Herter, [email protected]

Advertising WESTERN REGIONAL SALES MANAGER Stacy Mannik, [email protected] (949) 226-2024

MIDWEST REGIONAL AND INTERNATIONAL SALES MANAGER Mark Dunaway, [email protected] (949) 226-2023

EASTERN REGIONAL SALES MANAGER Jasmine Formanek, [email protected] (949) 226-2004

BILLING Cindy Muir, [email protected] (949) 226-2000

COTS Journal

HOME OFFICE

The RTC Group, 905 Calle Amanecer, Suite 250, San Clemente, CA 92673 Phone: (949) 226-2000 Fax: (949) 226-2050, www.rtcgroup.com

EDITORIAL OFFICE

Jeff Child, Editor-in-Chief 20A Northwest Blvd., PMB#137, Nashua, NH 03063 Phone: (603) 429-8301

Published by THE RTC GROUPCopyright 2013, The RTC Group. Printed in the United States. All rights reserved. All related graphics are trademarks of The RTC Group. All other brand and product names are the property of their holders.


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Untitled-14 1 9/3/13 9:54 AM


NOTEBOOKPublishers

Pete Yeatman, PublisherCOTS Journal

Apparently the overall economy has bottomed out and is s-l-o-w-l-y improving. And the military elec-tronics market is also starting to move ahead. This does not mean that the general budget for the military is improving, only that the reality of having fewer people means that in order for the military to perform its mission it needs to depend more on electronic systems. It will take a little time before there is a general positive feeling about the military electronics market, but unless our elected of-ficials decide to do something extremely stupid, the trend will continue.

The budget situation for the military electronics indus-try over the last two years has been a lot like a tornado going through a town; some suppliers were untouched and others completely devastated. Whether you were hit was dependent on the programs you were part of. From here on out we need to face the fact that the current U.S. budget climate is all about less money and getting more for what the military spends. The DoD will reduce the uniformed and civilian manpower as low as they reasonably can, and increase the use of less costly elec-tronics to replace the effectiveness lost by the manpower re-duction. Programs that will be seen in a more favorable light will be the ones that use available technology and limit costly development programs.

Whether creating new platforms or upgrading existing platforms, one fact is certain: gone are the days when elec-tronics and computing technologies were just a part of mili-tary deliverables functionality. From now on primes will start to partner with electronics systems suppliers, or may acquire companies that develop them. Vendor-supplied electronics systems will form the intelligent systems that are fundamen-tally tied to the capabilities and requirements of everything from radar systems to fire control systems to advanced com-munications gear.

The result is that high-level technical decision makersfrom DoD execs, to program managers (both uniformed and non-uniformed), to engineering managersneed to keep pace with the system-level technology issues along with the many global, big-picture trends that drive and affect technology de-cision making. The importance of technology as the military moves forward has even been part of every speech made by the

U.S. Secretary of Defense over the past year. But while the im-portance of electronics and computing technology in the mili-tary is far from new, the role its playing and the stakes involved have moved to a whole new plateau.

Until recently, our industry supplied modules, boards, boxes, preconfigured systems and in some cases complete sub-systems to a prime that integrated those electronics into a plat-form that ended up in a deliverable system. The responsibility of finding a supplier that used the technologies necessary to fulfill the requirements of the different elements within a platform or deliverable was on the shoulders of the prime contractors. In order to be successful as a supplier in the new budget climate, suppliers need to be conversant with the architecture of the plat-form and deliverable. They also need to tailor their offerings to be not just compatible, but also highly effective with the other elements within the platform and deliverable.

Whether the platform is a UAV, a manned aircraft, a ground combat vehicle or a warship, every platform has vary-ing requirements from basic SWaP reduction to highly sophis-ticated unique needs of a specific platform. Exploring different technology options and their different benefits is essential to every platform management teamfrom teams developing the smallest autonomous ground vehicle to those developing highly complex, large aerospace or marine platforms. Similar to what our industry did when the COTS philosophy was first introduced to the military, we now need to do the same with respect to platform architecture development and integration. This industry is at a point of experiencing a quantum change and any time we humans are faced with accepting a change, there is resistance. Our industry on both the supplier and user side will require some time before this imminent change is un-derstood and accepted.

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8 COTS Journal | September 20138

INSIDE TRACKThe

in Huntsville, AL. Guidance sections and guidance units will be built at the Raytheon Missile Systems Space Factory in Tucson, AZ.

Raytheon Waltham, MA. (781) 522-3000. [www.raytheon.com].

Lockheed Martin Com-pletes Long-Range Sur-veillance Radar Demo

Lockheed Martin success-fully operated its full-scale prototype long-range air sur-veillance radar during a recent capability demonstration to the U.S. Air Force. The Three-Dimensional Expeditionary Long-Range Radar (3DELRR) will serve as the principal Air Force long-range, ground-based sensor for detecting, identifying and reporting aerial targets. This next-

generation system will replace the Air Forces AN/TPS-75 air search radar.

During the event, the 3DELRR full-scale prototype showed its maturity, f lexibility, scalability and the benefits of its open technology design. More than 70 U.S. Air Force, U.S. Marine Corps and Office of Secretary of Defense per-sonnel attended the demon-stration either locally or via webcast. The radar detected required targets of opportunity launched from the Syracuse airport and surrounding areas. The company hired additional test aircraft for the event, putting the prototype through more advanced performance detection and tracking sce-narios expected of long-range radars.

Lockheed Martin Bethesda, MD. (301) 897-6000. [www.lockheedmartin.com].

Raytheon Receives $218 Million for Advanced SM-3 Missile Contract

Raytheon Company was awarded a $218,530,196 con-tract by the Missile Defense Agency to complete the assem-bly and delivery of 29 Standard Missile-3 Block IB missiles (Figure 2). Launched off U.S. Navy ships, SM-3 interceptors protect the U.S. and its allies by destroying incoming short-, medium- and intermediate-range ballistic missile threats by colliding with them in space.

The three back-to-back successful SM-3 Block IB f light tests have demonstrated the missiles advanced capabilities and reliability against various threats in a variety of mission scenarios. Combatant com-manders around the world are eager to build up their inven-tories in support of Phase 2 of the Phased Adaptive Approach

starting in 2015. Final assembly will take place in Raytheons new, state-of-the-art Redstone Missile Integration Facility

Figure 2

Launched off U.S. Navy ships, SM-3 interceptors protect the U.S. and its allies by destroying incoming short-, medium- and intermediate-range ballistic missile threats.

An E-2D Advanced Hawkeye assigned to Air Test and Evaluation Squadron (VX) 20 makes its first carrier takeoff aboard the aircraft carrier USS Harry S. Truman (CVN 75).

Figure 1

The U.S. Navy has awarded Northrop Grumman a $617 million con-tract for five full-rate production Lot 1 E-2D Advanced Hawkeye aircraft (Figure 1). The first E-2D Advanced Hawkeye took to the skies in 2007 over St. Augustine, FL. Since then, Northrop Grumman has delivered 10 new production E-2Ds to the U.S. Navy, on cost and on schedule. An ad-ditional 10 aircraft are in various stages of manufacturing and predelivery flight testing at the companys St. Augustine Aircraft Integration Center. Initial operational capability with the Navy remains on track for 2015.

The E-2D program continues to find ways to reduce costs and provide best value to the customer through improving aircraft delivery processes, standardizing repair methods and looking for opportunities to improve spares timing to increase the overall program affordability. According to Northrop Grumman, the Navys E-2D program of record at 75 aircraft, full-rate production enables the production of the remaining 55 aircraft over the next 10 years and provides the opportunity for a cost-effective, multi-year procurement.

Northrop Grumman, Los Angeles, CA. (310) 553-6262. [www.northropgrumman.com].

Northrop Grumman Awarded $617 Million Contract for E-2D Advanced Hawkeyes

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Military Storage Hierarchies: From RAID to SSDs

SPECIAL FEATURE

September 2013 | COTS Journal 11

High-bandwidth sensor platforms on UAVs, satellites and other system are bringing in a deluge of data. This is making military data storage a more mission-critical function than ever before. Memory arrays comprised of RAID module, rotating disks, SSD and sophisticated interfaces are being tasked to manage and store massive amounts of data. This section explores the key technology and product trends in military data storage. For their part, SSDs now have densities enabling system designers to store complete program and data storage all on rugged SSDs. This has interesting implications as storage media of significant densities can now reside in slot-card board-level systems or as mezzanines on SBCs.

There are two ends of the spectrum for todays military storage implementations. One is low-capacity, low-performance embedded storage boards. The other is higher-capacity, higher-performance, but physically much larger and heavier, external storage boxes or subsystems. However, current flash-based Solid State Drive (SSD) technologycombined with optimized stor-age controller architectureshas fueled the development of embedded storage blades that provide high levels of consistent performance, reliability and capacity. The latest crop of high-density, rugged solid state storage solutions is enabling military

Jeff ChildEditor-in-Chief

With a deluge of high-resolution data being captured constantly, the military now sees data storage as a key part of military platforms. Technology suppliers offer a mix of rugged solutions ranging from SSDs to RAID systems.

Military Demands a Whole Hierarchy of Storage Solutions


SPECIAL FEATURE

system developers to pack in system com-plexity without the burden of memory storage constraints.

Advanced Security TechnologyOne of the newest trends in SSDs is

the inclusion of more sophisticated se-curity technology. Along such lines, this summer STEC has expanded its s800 family of Serial Attached Storage (SAS) solid state drives (SSDs) with the intro-duction of the industrys first generally

available Micro SAS SSDs. Additionally, STEC announced that the new small form factor (1.8-inch) Micro SAS SSDs are available with stringent 256-bit AES-XTS encryption, enabling hardware-level security in cloud computing, data centers and web-based applications, as well as in government and defense environments where data protection is crucial (Figure 1). Uniquely designed for blade servers, caching and high-density computing en-vironments, the new Micro SAS drives

provide storage system developers with the smallest enterprise-class SAS SSD form factor yet. They meet the demand-ing performance, footprint and power re-quirements of todays enterprise-storage applications.

In addition to their corporate enter-prise system applications, the new Micro SAS SSDs and encryption address the rigorous demands of the federal sector. Government agencies face increasingly tighter requirements on computing and storage systems size and energy usageconcerns addressed by the Micro SAS drives small form factor and power draw thats 20 percent less than standard 2.5-inch SAS SSDs. Additionally, mobile/re-mote defense computing and storage sys-tems call for high levels of encryption in the field so that data is inaccessible should equipment fall into the wrong hands. The new STEC Micro SAS drives are available in 200 Gbyte and 400 Gbyte capacities.

New Capacity PointsMilitary embedded applications

have capacity needs that dont necessar-ily match to commercial needs. Virtium recently introduced its DecaStor line of solid state drives (SSDs) (Figure 2). De-signed to help embedded systems OEMs rely on a ready supply of SSDs in hard-to-find capacities, Virtium DecaStor 2.5- and 1.8-inch SSDs are ideal storage solu-tions for applications designed around 80, 160 and 300 Gbyte capacity points. DecaStor SSDs also feature 10-channel

Figure 1

The s800 family of Serial Attached Storage (SAS) solid state drives (SSDs) feature a small form factor (1.8 inches) and are available with stringent 256-bit AES-XTS encryption.

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SPECIAL FEATURE

controllers, which deliver compatible transfer speeds for a wide range of mili-tary networking and monitoring systems.

Virtium DecaStor products can be screened to extended temperatures and deliver security features with AES en-cryption, security erase and vtGUARD data protection in the event of an un-expected power interruption. DecaStor supports sequential read/write speeds of 410/375 Mbytes/s respectively, with read IOPS of 47,000 and 2,500 write IOPS. Vir-

tiums DecaStor SSDs are available now in 80, 160 and 300 Gbyte capacities.

High-Density RAID SolutionsExemplifying the modern use of

compact rugged RAID storage, Phoenix International Systems offers the mission-oriented RPC24 high-performance Fibre Channel RAID Subsystem (Figure 3). It features a capacity of twenty-four drives in two easily removable magazines con-taining up to twelve solid state disk or

hard disk drives, each housed in rugged 2U (3.5-inch) panel height, 19.5-inch deep enclosure. It provides up to eight host ports of 8 Gbit Fibre Channel (fol-lowed soon by 6 Gbit SAS and 10GigE iSCSI) to SAS, or SATA devices over a 12 Gbit SAS internal bus.

The unique design of the RPC24s rugged, cable-less, backplane-based, high-density 2U chassis provides a broad environmental operational envelope (-20 to +70C, 45,000 ft altitude with SSDs), redundant, hot-swap components and vast storage capacity, while assur-ing the highest level of data availability. Incorporating aluminum and steel in its rugged construction, the RPC24 weighs only 51 pounds with a full complement of 24 SSDs, is less than 20 inches deep, and is certified to military specifications MIL-STD-810G and MIL-STD-461E.

Transportable StorageAlso in the theme of purpose-built

removable storage, Winchester Systems offers the RR2P Series. Designed as trans-portable data storage for mobile field use aboard planes, ships and ground trans-port, the RR2P is a lightweight aluminum 2U RAID disk array, weighing 48 pounds fully loaded, featuring two secure, yet easily removable disk canisters (Figure 4). Each canister holds 10 compact 2.5-inch Small Form Factor (SFF) disk drives

Figure 2

The DecaStor 2.5- and 1.8-inch SSDs offer 80, 160 and 300 Gbyte capacity points. Sequential read/write speeds of 410/375 Mbyte/s respectively, with read IOPS of 47,000 and 2,500 write IOPS.

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SPECIAL FEATURE

with capacity up to 2 Terabytes each and total system capacity to 40 Terabytes. For speed, capacity and economy, a vari-ety of SAS and Solid State Disks (SSDs) are available in the 2.5-inch SFF size to meet varying needs. The RAID control-ler delivers up to 2,000 Mbytes/s write through-put for rapid data recording and up to 2,200 Mbytes/s for data reading and transfer from SAS disks.

In a typical surveillance application, the post-mission canisters with the criti-cal images are easily removed and plugged into a ground station. Fresh canisters are immediately loaded into the mobile unit for rapid redeployment. All 10 disks in a canister are carried as a single unit by a handle for safe transport. Each canister locks into place with a positive locking lever. Reliable canister connectors are military grade for field usage and rated for 5,000 insertion cycles. For personnel safety during deployment, the canisters are held by secure restraints for crash pro-tection impact to 200 Gbytes. The RR2P has four 8 Gbit Fiber Channel links that can be user configured as dual ports per

canister and offers options including AC or DC power supplies and a variety of disk and SSD storage alternatives. It is conve-niently only 17 inches wide to mount with a variety of standard rackmount rails and offers optional base plate mounting screws for secure lockdown to the ve-hicle. The RR2P is designed to facilitate

rapid data transfer from mobile vehicles to ground stations. Importantly, the RR2P will operate at 40C and at 10,000 foot pressurized attitudes. Variable speed fans provide cooling on demand while reducing noise and vibration at moderate ambient temperatures. A front-mounted LCD on each canister provides power, ac-tivity and status information.

Overlap with TelecomThe requirements of telecom have a

lot of overlap with rugged military needs. Thats why telco-based ratings like NEBS have relevance in the defense world. A new 2U RAID array has been certified to Network Equipment Building System (NEBS) Level 3. The 12-drive array from One Stop Systems supports up to 48 Tbyte data storage using twelve 4 Tbyte SATA drives. It connects to the host server with either PCIe x8 or SASx4 connectivity. The chassis includes dual redundant 500-watt power supplies, two removable blowers for superior cooling, and a removable NEBS filter and filter cover.

The RAID array boasts 2700 Mbyte/s

Figure 3

The RPC24 is a Fibre Channel RAID Subsystem that features a capacity of twenty-four drives in two easily removable magazines containing up to twelve solid state disk or hard disk drives, each housed in rugged 2U (3.5-inch) panel height, 19.5-inch deep enclosure.

Untitled-2 1 8/29/13 10:14 AM


SPECIAL FEATURE

data transfers from server to storage on a single PCIe x8 connection. A single SASx4 connection to the server provides 1900 Mbyte/s data transfers. PCIe is suitable for storage applications that require extremely fast read and write transfers. Because there is no software conversion from PCIe on the motherboard to another protocol, latency

is reduced, providing extremely fast data transfers. Two SASx4 input cable from one or two servers to the two SAS connectors on the rear of the RAID array. Both can be input connections from two servers or one can be an input and the other an output to connect another RAID array, thereby dou-bling the storage capacity and increasing

the performance. The 2U RAID array lists for $5,899 and is available immediately.

Phoenix InternationalOrange, CA.(800) 203-4800.[www.phenxint.com].

One Stop SystemsEscondido, CA.(877) 438-2724.[www.onestopsystems.com].

STECSanta Ana, CA.(949) 476-1180.[www.stec-inc.com].

VirtiumRancho Santa Margarita, CA.(949) 888-2444.[www.virtium.com].

Winchester SystemsBillerica, MA.(781) 265-0200.[www.winsys.com].

Figure 4

RR2P is a lightweight aluminum 2U RAID disk array, weighing 48 pounds fully loaded, featuring two secure, yet easily removable disk canisters.

Untitled-4 1 8/23/13 2:43 PM

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One of the biggest challenges that developers of military safety-critical software applications for multicore processors (MCPs) face is managing contention for shared re-sources such as cache. Benchmarks dem-onstrate that MCPs significantly increase cache contention, resulting in worst-case execution times (WCETs) that are typi-cally 100 percent (or more) greater than average-case execution times (ACETs). One way that developers can effectively manage this contention and boost mul-ticore performance is to utilize an RTOS with cache partitioning.

Multicore ComplicationsOn an MCP, applications running on

different cores compete for shared cache (L2, and/or L3 if present). This greatly increases the potential for interference whereby an application running on one core can significantly impact the execu-tion time of an application running on another core. Consequently, the impacted software may overrun its execution time budget and/or miss deadlines, resulting in unsafe failure conditions.

MCPs are designed to optimize aver-age-case execution times (ACETs), often at the expense of worst-case execution times (WCETs). But while optimized ACETs work well in non-critical applications, developers of certifiable, safety-critical software must design and budget application execution times for WCET behavior. Unfortunately, MCPs typically inflate the difference be-tween WCETs and ACETs by 100 percent or morein practice, some have been en-

countered with deltas exceeding 1000 per-cent. Consequently, on MCPs, applications require significantly higher execution time budgets (much of it often unused), resulting in significantly degraded CPU utilization.

Cache partitioning reduces WCET and increases CPU utilization by reducing cache competition and making it easier to bound and control interference patterns. By setting aside dedicated partitions for critical applications, developers can reduce

Tim King, Product Marketing ManagerDDC-I

For military safety-critical applications, its a tricky problem to manage the complications of multicore computer systems. Smart cache partitioning helps tame that beast.

Cache Partitioning Enhances Multicore Performance

Military Storage Hierarchies: From RAID to SSDs

SPECIAL FEATURE

Core 0 Core 1

CPU

L1 cache

CPU

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L2 cache

Figure 1

Shown here is a dual-core configuration without cache partitioning. Here each core has its own CPU and L1 cache and both cores share an L2 cache. Note that shared memory and optional L3 are not shown.

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Untitled-1 1 8/28/13 2:31 PM


SPECIAL FEATURE

interference from applications residing on other cores and provide timely, deter-ministic access to cache. This reduces the amount of time that must be budgeted for critical tasks, thereby shrinking the delta between ACET and WCET and boosting overall CPU utilization.

Cache PartitioningIn a simple dual-core processor con-

figuration (Figure 1), each core has its own CPU and L1 cache and both cores share an L2 cache. In this configuration, applications executing on Core 0 compete for the entire

L2 cache with applications executing on Core 1 (note that applications on the same core also compete with one another for L2; cache partitioning applies in this case as well). If application A on Core 0 uses data that maps to the same cache line(s) as appli-cation B on Core 1, then a collision occurs.

For example, suppose As data resides in L2; any accesses to that data will take very few processor cycles. Then, suppose B accesses data that happens to map to the same L2 cache line as As data. At that point, As data must be evicted from L2 (including a potential write-back to RAM), and Bs data must be brought into cache from RAM. The time required to handle this collision is typically charged to B. Then, suppose A accesses its data again. Since that data is no longer in L2 (Bs data is in its place), Bs data must be evicted from L2 (including a potential write-back to RAM), and As data must be brought back into cache from RAM. The time required to handle this col-lision is typically charged to A.

Most times, A and B will encounter such collisions infrequently. In those cases,

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Core 0cache

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Core 1

CPU

L1 cache

CPU

L1 cache

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Figure 2

Here again each core has its own CPU and L1 cache and both cores share an L2 cache. But in this case the RTOS partitions the L2 cache such that each core has its own segment of L2.

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SPECIAL FEATURE

their respective execution times can be con-sidered as average case (ACETs). How-ever, on occasion, their data accesses will collide at a high frequency. In these cases, their respective execution times must be considered as worst case (WCETs).

Designing for Worst CaseWhen developing certifiable, safety-

critical software, one must design and budget an applications execution time for worst-case behavior, since such soft-ware must have an adequate time budget to complete its intended function every time it executes, lest it cause an unsafe failure condition (note that a safety-crit-ical RTOS must enforce time partition-ing, wherein each application has a fixed amount of CPU time budget to execute).

With the potential for multiple appli-cations on multiple cores to generate con-tention for L2, WCETs on MCPs often are considerably higher than ACETs. And since certifiable, safety-critical applications must have time budgets to accommodate their WCETs, this situation leads to a great deal of

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Figure 3

Shown here are the results of the read-only test application that demonstrate the benefits of cache partitioning. These results are representative of the other three tests.

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SPECIAL FEATURE

budgeted but unused time, resulting in sig-nificantly degraded CPU utilization. Cache partitioning reduces WCET by reducing cache collisions among competing applica-tions residing on different cores. Again, in a simple dual-core processor configuration (Figure 2), each core has its own CPU and L1 cache and both cores share an L2 cache.

However, in this case, the RTOS parti-tions the L2 cache such that each core has its own segment of L2, meaning that data used by applications on Core 0 will only be cached in Core 0s L2 partition. Similarly, data used by applications on Core 1 will only be cached in Core 1s L2 partition. This partitioning eliminates the possibility of ap-plications on different cores interfering with one another via L2 collisions. Without such interference, the deltas between application WCETs and its ACETs are often consider-ably lower than is the case without cache partitioning. By bounding and controlling these interference patterns, application ex-ecution times are more deterministic and time budgets can be set far more tightly, thereby keeping processor utilization high.

Test Environment and Applications

Cache partitioning tests were per-formed on a 1.6 GHz Atom processor (x86) with 32 Kbyte of L1 data cache, 24 Kbyte of L1 instruction cache and a 512 Kbyte unified L2 cache. Note that while a single core x86 processor was used for these tests, this cache partitioning capability applies equally well to applications executing on the same core (which compete for L2). Fur-ther, it does not depend on any features that are special or unique to x86 processors and applies equally well to other processor types (such as ARM or PowerPC). Four memory-intensive test applications were used, all using a range of data/code sizes, sequential and random access strategies, and vari-ous working set sizes including read-only, write-only, copy and code execution.

Tests were run with and without a cache trasher application, which evicts test application data/code from L2 and dirties L2 with its own data/code. In effect, the cache trasher puts L2 into a worst-case state from a test applications

perspective. That is, the cache trasher mimics real-world scenarios, where dif-ferent applications run concurrently and compete for the shared L2 cache.

Each test application was executed under three scenarios: In scenario 1, with-out cache partitioning and without cache trashing, the test application competes for the entire 512 Kbyte L2 along with the RTOS kernel and a variety of debug tools. This test establishes baseline average per-formance, wherein each test executes with an average amount of L2 contention.

In scenario 2, without cache partition-ing and with cache trashing, the test appli-cation competes for the entire 512 Kbyte L2 along with the RTOS kernel, a variety of debug tools and the rogue cache trasher application. This test establishes baseline worst-case performance, wherein each test executes with a worst-case amount of L2 interference from other applications, pri-marily the cache trasher.

In Scenario 3, with cache partitioning and with cache trashing, three L2 partitions are created: a 256 Kbyte partition allocated to the test application; a 64 Kbyte partition

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SPECIAL FEATURE

allocated to the RTOS kernel and a variety of debug tools; and a 192 Kbyte partition allocated to the rogue cache trasher appli-cation. This scenario establishes optimized worst-case performance, wherein each test executes within its own L2 partition with no interference from other applications, in-cluding the cache trasher.

Benefits of Cache PartitioningResults of the read-only test appli-

cation demonstrate the benefits of cache partitioning (Figure 3). These results are representative of the other three tests. With no cache partitioning and no cache trashing (scenario 1, ACET), the read-only test averaged 105 usecs to execute given a working set size of 512 Kbyte. With no cache partitioning, but with cache trash-ing (scenario 2, WCET1), the test took roughly 400 usecs to execute given the same size working set (a 280% increase). However, with cache partitioning and cache trashing (scenario 3, WCET2), the average execution time drops back to 117 usecs, or just 11% higher than the ACET.

These results clearly demonstrate the efficacy of cache partitioning for an ap-plication that performs a large number of reads per period. Though difficult to discern here, the impact on bounding WCETs is more pronounced when the applications working set size fits within the cache partition that its using (in this case, 256 Kbytes). This result is expected due to the nature of cache. That said, em-bedded, real-time applications tend to have relatively small working set sizes, so we expect that cache partitioning will benefit most applications.

Write-Only Test ResultsResults for the write-only test were

similar to the read-only test, though more pronounced for smaller working sets. For larger working sets, results showed rela-tively small differences between WCETs with and without cache partitioning. Re-sults for the copy test were similar to the read-only test, though more pronounced for smaller working sets. For larger work-ing sets, results were less dramatic, but still showed significant improvement (roughly 2x) in WCETs with cache partitioning.

Note that it is possible for applica-tions executing in the same cache parti-

tion to interfere with each other. How-ever, such interference is much easier to analyze and bound than the unpredict-able interference patterns that may occur between applications executing on differ-ent cores with shared cache. In those situ-ations, applications could be mapped to separate cache partitions.

The benchmark results clearly dem-onstrate that cache partitioning technol-ogy provides an effective means of bound-ing and controlling interference patterns

in shared cache on an MCP. In particular, worst-case execution times are bounded and controlled much more tightly when the cache is partitioned. Consequently, application developers can set relatively tight, yet safe, execution time budgets thereby maximizing MCP utilization.

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Untitled-6 1 9/3/13 9:32 AM


OpenVPX is a robust embedded computing standard, developed to meet the needs of demand-ing defense and industrial applications. A primary goal during the definition of OpenVPX was that it facilitates mul-tivendor COTS system-level interoper-ability including modules, backplanes and development chassis. Since embed-ded defense systems must often be de-veloped and deployed rapidly, it is very important that potential conflicts are eliminated as quickly as possible during the design phase.

Established by the VITA Stan-dards Organization and formally des-ignated as ANSI/VITA 65.0, OpenVPX references other VITA standards to define a comprehensive systems archi-tecture including mechanical speci-fications for modules, connector de-scriptions, thermal characteristics, communications protocols, utility and power definitions. It also defines a multiplane architecture approach for communication between system components, including support for several high-bandwidth switch fabric protocols including 10 GbE, PCI Ex-press, Serial RapidIO and SATA for nonvolatile memory. New revisions of

these standards are pushing the limits of differential copper pairs; OpenVPX provides for coax and fiber optic con-nections to support higher-speed data

and other signal formats, but the cur-rent generation of systems must still rely on copper connections through-out the backplane.

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Backplane topologies are identified as Central or Star, Distributed or Mesh, and Hybrid, a combination of VME slots and VPX slots.

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TECH RECON

Many Topology OptionsAn OpenVPX backplane can be con-

figured into many network topologies such as mesh, star, dual-star, ring or daisy chain. These on-backplane networks per-mit multiple signals to be routed such that several cards can talk to each other simultaneously, achieving an aggregate bandwidth well over 100 Gbytes/s. Open-VPX uses a concept called profiles to define the choices for switch fabrics and other technologies. In a system chassis, there are slot profiles that define the map-ping of I/O onto the backplane connec-tors; Payload, Peripheral, Switch, Storage

and Bridge are types of slot profiles, with multiple unique and specific profiles or-ganized under each type. Profile param-eters are used to further describe proper-ties of a backplane profile.

An OpenVPX backplane profile is a physical definition of a backplane imple-mentation that includes details such as the number and type of slots that are im-plemented and the topologies used to in-terconnect them. Ultimately a backplane profile is a description of channels and buses that interconnect slots and other physical entities in a backplane, describ-ing the fabric interconnections from slot

to slot. Backplane topologies are identi-fied as Central or Star, Distributed or Mesh, and Hybrid, a combination of VME slots and VPX slots (Figure 1).

Components from different vendors that adhere to the same OpenVPX profile can be configured into functional sys-tems. This critical characteristic of Open-VPX delivers the benefits of interopera-bility, straightforward technical upgrades and competition-driven cost contain-ment to the end users of systems, such as the Department of Defense. However, the devil is in the details, as the large num-ber of parameters involved in each profile make matching component profiles a de-manding design function.

Mission-Critical SystemsThe flexibility offered by the wide

range of OpenVPX profiles allows de-signers to optimize the communication topology between slots within a sys-tems backplane, delivering tremendous improvements in the performance of real-time applications. Slots can be de-signed to accept the best I/O modules for a specific application and the num-ber of those slots also matched to ap-plication needs. Similarly, the number of processing modules is set to meet the performance requirements, and then the connections between all these modules are designed to match the applications processing style and deliver maximum sensor processing throughput.

However, implementing this level of optimized topology can be a complex and time-consuming task, constrained by a number of factors. In the defense arena, an example would be a computing system providing image processing on an unmanned aerial vehicle (UAV), us-ing a set of high-performance comput-ing modules and multiple input chan-nels from image sensors.

This computing system must de-liver real-time performance while stay-ing within clearly defined Size, Weight and Power (SWaP) constraints that are defined by both the characteristics of the UAV and type of missions it must perform. The system design must make optimal use of every slot and every com-munication link between the modules in the slots. OpenVPX profiles enable this

Figure 2

This advanced implementation improves the signal integrity between system cards beyond the requirements of the PCI Express, Serial Rapid I/O and 10Gbit (XAUI) Ethernet standards.

Target Slot Target Slot Source Slot

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4x (TX & RX) Link

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FMM

Data / Expansion / Custom Planecan be PCI Express, Serial Rapid IO,

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FMM micro-overlays also provide a natural migratory development environment for moving from the lab to the field with the high-speed backplanes.


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optimization, but a cookie cutter, one-size-fits-all approach is not going to work.

There is also the real-world challenge of design changes. To go back to the UAV example, it may be that after the system design is already underway, a high-level decision is made to utilize a new, ad-vanced type of sensor with a much greater input bandwidth. This, in turn, drives a change in the backplane profile to accom-modate the added bandwidth; somehow, the backplane must be adjusted in accor-dance with a new OpenVPX profile.

Customized BackplanesA long-standing approach to cus-

tomizing system backplanes is the use of PCB overlays, which fit over an existing backplane, linking backplane pins to the new, desired and optimized connection topology. This is an effective way to mod-ify an existing design quickly, saving time and money.

However, as communications fabrics move into the 5 GHz range, a new set of challenges arise. The impedance varia-tions imposed by the high-performance OpenVPX multi-gig differential connec-tor create significant issues when attached to a standard overlay. There are also cost issues involved in creating traditional overlays for complex OpenVPX designs, negating some of the savings that come from using a backplane overlay.

A new technology, connector-less mi-cro-overlays, presents a cost-effective so-lution that can also supply the necessary signal integrity to meet this challenge. Micro-overlays use BGA solder connec-tion technology to interface a PCB-based differential pair matrix with compat-ible backplanes. The micro nature of the overlay reduces the transmission line impedance variations and stubs associated with connector-based inter-faces by connecting directly to the main backplane via a solder interface. This ad-vanced technique improves the signal in-tegrity between system cards beyond the requirements of the PCI Express, Serial Rapid I/O and 10Gbit (XAUI) Ethernet standards (Figure 2).

A Practical ExampleDawn VME Products has enhanced

the micro-overlay approach with a patent-

pending Fabric Mapping Module (FMM) technology that simplifies and automates the optimization of backplane topologies in compliance with OpenVPX profiles. FMM allows designers to work with flex-ible configurations of high-speed links, so inter-slot communications can be cus-tomized to meet unique system require-ments. These micro-overlays can also facilitate rear transition modules and low profile connector interface systems when normal transition modules do not fit the system application envelope.

FMM micro-overlays allow off-the-shelf backplanes to be quickly custom-ized to mission requirements, without the time and expense required to spin a new backplane. This can be a critical ad-vantage when schedules are compressed by late design changes, as described in the example above. Dawns FMM micro-overlays also provide a natural migratory development environment for moving from the lab to the field with the high-speed backplanes due to the rugged , low mass, connector-less characteristics of the technology (Figure 3).

OpenVPX profiles enable system de-signers to confidently create systems us-ing components from multiple vendors, and the range of definable profiles allows a wide range of choices in connection standards and topologies. However, the profiles also introduce a new level of com-plexity to the design process, especially with regard to backplane profiles. Dur-ing a design, this complexity issue adds to the already time-consuming task of creating a system backplane. Backplane micro-overlays offer a cost-effective and time-efficient method for customizing an OpenVPX backplane. They support the interoperability of OpenVPX, while providing the flexibility to quickly mod-ify designs based on off-the-shelf back-planes.

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The proliferation of new tech-nologies and advancements in ground vehicle communications has spawned a host of programs designed to integrate communication subsystems into the larger picture of battlefield in-formation exchange. These projects are designed to make all levels of command omniscient in their communication awareness. Much technology and plat-form architectures for this have been leveraged from the U.S. Armys trou-

bledand ultimately canceledFuture Combat Systems (FCS) program.

Unfortunately, until the true essence of connectivity is implemented acr the board, such as can be found with the Victory stan-dard, near-sighted visions (in todays terms) of simply miniaturizing bolt-on solutions persevere (think SWaP). Vehicle space con-tinues to be eaten by upgraded network-ing equipment both inside and out, bringing with it the associated power demands and cabling and cooling obstacles.

The latest strategy designed to link the actual box with onboard assets is the Capability Set 13 (CS 13) program, which is being led by the U.S. Army with sup-port from a wide selection of industry members. CS 13 was validated through the Armys Network Integration Evaluations (NIE) pathway, and is designed as a fully integrated package of radios, satellite sys-tems, antennas, software applications and other elements that combine to provide communications connectivity through

Johnny KegglerExecutive Editor

Drawing on technology from the canceled FCS program, the U.S. Army has been developing and testing a slew of solutions that make the most efficient use of ground vehicle space and resources.

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SYSTEM DEVELOPMENT

Figure 1

Two views inside MRAPs that have been equipped with networked communication assets through the CS 13 program. Although covering a broad-spectrum gap in the communications sphere, the prototype vehicles were essentially subjected to bolt-on-type installations.

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Untitled-4 1 9/4/13 4:02 PM

SYSTEM DEVELOPMENT


a Tactical Operations Center to on-the-move Brigade commanders and down to the dismounted soldier (Figure 1).

Through the CS 13 upgrade, which began fielding in October on five Super Configuration MRAPs recently deliv-ered to the U.S. Armys 10th Mountain Division, the vehicles radios, sensors and all associated software have been inte-grated into one package, which is essen-tially an extension of the Warfighter In-formation Network - Tactical (WIN-T).

The full spectrum of battlefield com-munications capabilities is addressed and interconnected with CS 13, which features some well-known comms hard-hitters such as General Dynamics C4 Sys-tems ubiquitous AN/PRC-154 Rifleman Radio and the Harris AN/PRC-117G, the PRC-152A and the companys RF-7800W high-capacity line-of-sight radios.

To contrast this traditional equipment installation approach to the aforementioned Victory standard concept, one must consider

a few important factors. First, the current CS 13 vehicles are prototypes, and the Vic-tory standard still has a chance to be imple-mented on any new builds of that program.

Second, although an impressive list of converts have signed on to develop the Vehicular Integration for Command, Control, Communications, Computers, Intelligence, Surveillance and Reconnais-sance / Electronic Warfare (C4ISR/EW) Interoperability (VICTORY) initiative, including Curtiss-Wright Controls De-fense Solutions, GDC4S, SAIC, Raytheon and DRS Technologies, et al, this new ap-proach to connectivity is still an emerging

Figure 2

A new-build CS 13 prototype is prepared for delivery to the 3rd Brigade Combat Team, 10th Mountain Division at Fort Drum, NY on 1 October. The Victory initiative will release some of the outboard clutter and help clear some much-needed space within.

Figure 3

The TMR 200 offers the advanced networking features needed to interconnect with a vehicles electronic architecture and command, control, communication, computing and intelligence (C4I) systems.

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SYSTEM DEVELOPMENT

technology and slated for implementation only in future vehicle networking designs.

Whereas the game-changing SAT-COM-on-the-move concept somehow re-mains a bolt-on afterthought, and although miniaturization has been a godsend to this arena, Victory implementation will breathe new life into this and other vehicle network-ing elements, and to the vehicles themselves through the recovery of lost space, reduced weight requirements and power-saving attributes. Where a legacy vehicle would feature multiple GPS units, SPUs, anten-nas and displays, integration through Vic-tory would combine assets to enable shared antennas, terminals and other resources through designing connectivity to a set of standards found on the data bus (Figure 1).

Victory implementation allows systems to share information over an open architec-ture that allows future upgrades without requiring significant equipment or ergo-nomic redesigns. That architecture defines common terminology, components and in-terfaces through a set of standard specifica-tions and reference designs. The documents describe how the specifications could be deployed. The reference designs range from everything to automotive interfaces to com-mander display interfaces to Video/Imagery Situational Awareness interfaces and Shot Detection System Integration designs.

The Victory initiative began in May 2010 and was designed to overcome the

problems associated with the traditional bolt-on approach to U.S. Army vehicle upgrades, and in July 2011 the Victory 1.0 specification was released (currently on ver-sion 1.4). The Victory Standards Support Office releases phased sets of specifications addressing the required capabilities for in-tegrating C4ISR/EW mission equipment and platform applicationsstandards that are hardware and software agnostic. The overall standards specifications include:

a data bus-centric concept distributed hardware components

so software upgrades can be realized without affecting the actual boxes

physical and logical interfaces be-tween systems and components that are based on the Victory open stan-dard architecture

shared hardware and software IA components that will enable systems integrators to build security designs to protect and control access to pro-prietary information

a set of shared data bus services

Some subsystem vendors have al-ready understood that Victory compli-ance is a prerequisite for involvement in new tactical and combat vehicle pro-grams and are working toward that goal. Bringing the vehicle manufacturers and system-level developers around to this train of thought will close the circle and

Figure 4

Digital Beachhead is designed as an integrated Victory backbone solution that features GbE switching and routing, along with Victory data bus, and management and shared services.

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SYSTEM DEVELOPMENT


take the ground vehicle market to its next level.

Among the most interesting develop-ments feeding ground vehicle networking in the past year has been the emergence of subsystems purpose-built specifically aimed at that functionality. Along just such lines, earlier this year General Dy-namics Canada has introduced its next-generation Tactical Mobile Router, the TMR 200, a compact, modular and flex-ible router that can be easily configured

and integrated in a variety of platforms and wireless networks (Figure 3). With the ability to handle high-bandwidth applica-tions, it ensures reliable and secure com-munications even where wireless network infrastructures do not exist or when nodes are overloaded or off the network. It is ide-ally suited for tactical environments where network and vehicle electronic architec-tures are becoming more complex with high-definition cameras and sophisticated sensors streaming gigabits of information.

Engineered specifically for in-field communications, the TMR 200 allows de-fense and public safety personnel, mobile command centers and central commands to share high-bandwidth applications such as situational awareness information or battle management applications, along with critical voice and data. The TMR 200 offers the advanced networking features needed to interconnect with a vehicles electronic architecture and command, control, communication, computing and intelligence (C4I) systems. In addition, it can easily interface with other systems to enable remote control of communication devices in a tactical mobile network.

Aiming a solution specifically for Vic-tory-compliant platforms, Curtiss-Wright Controls Defense Solutions (CWCDS) of-fers a rugged Victory-compliant network-ing backbone called the Digital Beachhead system (Figure 4). It combines a 16-port Gigabit Ethernet Network Switch with a high-performance, power-efficient Ve-hicle Management Computer. Using the system, it is now possible to quickly in-tegrate a modern vehicle control system into a ground vehicle that previously had no embedded onboard electronics. Digital Beachheads ARM processor-based system computer runs the vehicles health man-agement (HUMS/CBM+) software and monitors the vehicles primary systems.

Digital Beachhead comes pre-in-stalled with Curtiss-Wright Controls Vehicle Management Framework (VMF) software. Vehicle Management Frame-work provides high-level logical access to common vehicle interfaces (CANbus, analog and digital I/O, camera, audio and so on). It has interfaces with HUMS logistic services, such as CBM+/CLOE and DDS. The system includes an event-driven framework for vetronics control and status. A local user interface is pro-vided via VGA/DVI and USB keyboard/mouse. With an extremely small foot-print 10 x 7 x 3), combined with less than 4 lb weight, the unit offers a low power, natural convection design. Power consumption is 30W max with less than 20W typical. It supports MIL-STD-1275-compliant 28 VDC power with op-tional Nuclear Event Detector (NED) and meets MIL-STD-810 and MIL-STD-461 environmental qualifications.

Untitled-4 1 3/28/13 1:32 PM

Untitled-3 1 9/3/13 9:22 AM

SYSTEM DEVELOPMENT


As the military moves to a more systems-level approach to de-liverable platform designs, the pressure is on to not reinvent the wheel for every software need. But open stan-dards have been slow to catch on. One of the more vivid success stories is the Fu-ture Airborne Capability Environment (FACE). The FACE Standard defines the software computing environment and interfaces designed to support the devel-opment of portable components across the general-purpose, safety and security profiles. FACE uses industry standards for distributed communications, pro-gramming languages, graphics, operat-ing systems and other areas. Its goal is to establish a common computing soft-ware infrastructure supporting portable, capability-specific software components across Department of Defense (DoD) avi-onics systems.

The FACE Consortium was formed in 2010 as a collaborative approach to develop a common operating environ-ment supporting portability and reuse of software components across Depart-ment of Defense (DoD) aviation systems. The FACE Consortium has developed a supplier-independent, standardized envi-ronment for DoD aviation systems allow-

ing software components to be rapidly migrated across systems conforming to the FACE Standard. The FACE Consor-tium provides a vendor-neutral forum for industry and the U.S. government to work together to develop and consolidate the open standards, best practices, guid-ance documents and business models

necessary to achieve these results.

Overcoming Adoption ResistanceOver the years, attempts at establish-

ing open systems standards have been tried in the military before with mixed success. There are a couple of reasons why FACE is finally catching on. First, current


While open architecture standards have been slow to catch on in the military, the Future Airborne Capability Environment (FACE) offers whole new levels of efficiency for airborne software computing implementations.

FACE Standard Brings Open Concepts to Airborne Platforms

Figure 1

U.S. Army UH-60L Black Hawk helicopters lift off at Cairo West Air Base. The UH-60L Cockpit Digitization Program is among those that Northrop Grumman plans to use the FACE Reference Architecture in.

COTS JOURNAL EXCLUSIVEDesigning at the System-to-System Level: The Industrys New Challenge

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SYSTEM DEVELOPMENT

aviation systems are typically developed for a unique set of requirements by a sin-gle vendor, causing longer lead times for urgent needs, platform-unique designs, limited portability of software compo-nents, increased costs, and creating bar-riers to competition within and across platforms.

Second, the military aviation com-munity has not created standardized architectural and software interface standards to sufficiently enable portabil-ity of software components across DoD aviation systems. Furthermore, contracts typically do not require conformance to a common set of open standards, and pro-gram managers are not funded to assume cost or schedule risks of multi-platform requirements.

FACE creates an open, modular soft-ware environment enabling portability and reuse of software components across multiple programs and platforms. This architecture expands the selection op-tions for military software components, reduces up-front procurement costs, re-

duces system integration cost and risk, reduces upgrade and technical refresh costs, and therefore reduces total life cy-cle costs. The FACE Consortium builds upon the tenets of Open Architecture (OA), IMA and Modular Open Systems Approach (MOSA) by defining a stan-dardized method of interface between software components and architectural segments. The consortium is currently comprised of 39 members including DoD and industry member organizations, their representatives and advisors. The Consortium was formed and is currently managed under the auspices of The Open Group.

Already Required in ProgramsThere are several programs with re-

quirements for FACE. Among these are the U.S. Navy C-130T, U.S. Navy ADDS, U.S. Navy Full Motion Video, Army Joint Multi-Role Technology Demonstrator, and the U.S. Navy BAA for the Autono-mous Aerial Cargo Utility System (AA-CUS) research program.

For its part, Northrop Grumman was an early advocate of establishing open architecture standards. The com-pany is actively using the FACE Reference Architecture and interfaces on existing avionics programs, including the effort to integrate third-party-developed FACE components inside Northrop Grum-mans embedded GPS/inertial navigation system for the Joint Precision Approach and Landing System program. Northrop Grumman is also pursuing the FACE Ref-erence Architecture for future programs, including the UH-60L Cockpit Digitiza-tion Program (Figure 1).

Additionally, software components supporting the FACE Technical Standard, such as the full-motion video application for the companys Integrated Avionics System, have been successfully demon-strated on various hardware platforms. Furthermore, Northrop Grummans Integrated Avionics System has already been rated exemplary by the U.S. Depart-ment of Defense via the Modular Open Systems Approach Program Assessment and Rating Tool, which measures the de-gree of implementation of open architec-ture standards within a program.

FACE in JMR/FVLAlso an early adopter of FACE,

Lockheed Martin last month said it will offer a universal, highly adaptable and affordable mission equipment package (MEP) to meet requirements for the Joint Multi-Role/Future Vertical Lift (JMR/FVL) rotary wing program, with poten-tial applications for other customers and platforms. The product will be an afford-able, dependable solution for multiple customers due to its open architecture and future airborne capability environ-ment (FACE) software design.

To improve the affordability and growth potential of the mission equip-ment package throughout its lifecycle, Lockheed Martin is incorporating the DoDs FACE-software standards into the cockpit and mission systems. The use of the FACE standard for the software de-sign will provide the U.S. Army unprec-edented flexibility for reuse across mul-tiple aviation platforms.

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While slot-card, backplane-based form factors like VME and cPCI enjoy a rich legacy in the military, none of those backplane-based standards suit particular, unique space, power and reliabil-ity constraints of small embedded systems. Thats why busless embedded form factors have risen in popularity in recent years. COM and COM Express modules cover the compute core only side of that equation. But form factors like EBX, ETX and the vari-ous versions of ITX target the more complete single board computer (SBC) needs of busless systems. A growing number of military ap-plications need just such technology, Small UAVs being just one example (Figure 1).

For its part, the Embedded Board, eX-pandable (EBX) standard is the result of a collaboration between industry leaders to unify the embedded computing industry on a small footprint embedded single board computer standard. The EBX combines a standard footprint with open interfaces. The EBX form factor is small enough for deeply embedded applications, yet large enough to contain the functions of a full embedded computer system: CPU, memory, mass stor-age interfaces, display controller, serial/par-allel ports and other system functions.

For expansion, EBX allows easy and modular addition of functions not con-

tained in standard product offerings via popular existing industry standardsPC/104, PCI, PC/104-Plus, PCI-104 and PCMCIA. PC/104 places the ISA bus on compact 3.6 x 3.8-inch modules with self-stacking capability. PC/104-Plus adds the speeds of PCI bus to the equation.

Meanwhile, ETX, which stands for Embedded Technology eXtended, is a highly integrated and compact (3.7 x 4.9 inch) (95 x 125 mm) computer-on-module (COM) form factor meant to be used much like an IC component. An ETX COM inte-grates core CPU and memory functional-ity, the common I/O of a PC/AT, USB, au-dio, graphics and Ethernet. All I/O signals as well as a full implementation of ISA and PCI buses are mapped to four high-density, low-profile connectors on the bottom side of the module. In April 2006, the members of the ETX Industrial Group released the latest generation of the ETX 3.0 specification. The

ETX Industrial Group (www.etx-ig.org) is an independent association of companies that support ETX and advance the standard.

Based on ATX, the ITX form fac-tor is more known recently for its spinoff versions such as Mini-ITX and Pico-ITX. Mini-ITX is a 17 x 17 cm (or 6.7 x 6.7 inch) low-power motherboard form factor de-veloped by VIA Technologies in 2001. They are commonly used in small form factor (SFF) computer systems. Mini-ITX boards can be passively cooled due to their low power consumption architecture. The four mounting holes in a Mini-ITX board line up with four of the holes in ATX-specification motherboards. Pico-ITX, meanwhile, is a PC motherboard form factor announced by VIA Technologies in January 2007. The form factor was trans-ferred over to SFF-SIG in 2008. The Pico-ITX form factor specifications call for the board to be 10 x 7.2 cm (3.9 2.8 inch).


For military platforms where the size and weight of a backplane isnt practical, busless embedded computer form factors such as EBX, ETX and Mini-ITX are gathering mindshare.

Busless Embedded Form Factors Mean Tight SWaP Requirements

EBX, ETX and ITX SBCs

TECHNOLOGY FOCUS

Figure 1

Small UAVs like Boeings RQ-21A Integrator are exactly the kind of platform suited for busless embedded computer form factors like ITX, EBX and ETX.

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The PPM-PS397-POE-1 accepts 42-57VDC and converts it to three isolated outputs: [email protected], +12VDC@ 1.0A, and [email protected]. Each output is short circuit protected and current limited. A minimum load is not needed to bring the supply into regulation.:LQ6\VWHPVDOVRRIIHUVWKLVPRGXOHFRQJured for PC/104 and standalone systems. No fans or heat sinks are required to meet its extended operating temperature range of -40 to +85C.

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cots journal september 2013

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