VHDL 360©

by: Mohamed Samy Samer El-Saadany

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VHDL 360 © 2

Module 1

Create your first model for a simple logic circuit

Objective

• Create your first VHDL model for simple logic circuits

• Skills gained:– Know the basic structure of a VHDL model

(entity, architecture)– Model simple combinational logic

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Outline

• Entity• Architecture• Internal Signals• Expressions & Operators• With-Select• When-Else

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VHDL Design Units

After understanding our first model*, let’s move forward & understand how to construct one

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*Module 0: Introduction to VHDL

VHDL Design Units

• A VHDL Model (Design unit) consists of:– Entity

• Define ports (inputs and outputs)

– Architecture• Define operation (input/output relation)

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Entity Description

entity <entity_name> isport ( <port_name> : <mode> <type>; <port_name> : <mode> <type>; … -- last port has no semicolon <port_name> : <mode> <type> );End entity;

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ENTITY model1 IS --VHDL is case insensitivePORT( a : IN std_logic;

b : IN std_logic; c : IN std_logic; d : IN std_logic; e : OUT std_logic );

END model1 ;

Example:

Syntax:• <mode>: port direction

– IN: Input that can only be read– OUT: Output that can only be written to– INOUT: Input or output can be read and

written to

Entity Description

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Types:• VHDL offers the following standard types:

– Integer: -231 to 231-1– Bit, Bit_vector– …

• IEEE Packages offer more types:– Std_logic, std_logic_vector– …

Require use of appropriate IEEE packages

Bit values:‘0’ -- Binary Zero‘1’ -- Binary OneStd_logic values‘U’ -- Uninitialized‘X’ -- Forcing Unknown‘0’ -- Forcing Zero‘1’ -- Forcing One‘Z’ -- High Impedance‘W’ -- Weak Unknown‘L’ -- Weak Zero‘H’ -- Weak One‘-’ -- Don’t Care

ENTITY model1 IS PORT( a : IN bit_vector(3 downto 0); b : IN bit; c : IN bit; d : IN bit; e : OUT bit );END model1 ;

Example: Using Standard Types

LIBRARY ieee; USE ieee.std_logic_1164.all;

ENTITY model1 IS PORT( a : IN std_logic;

b : IN std_logic; c : IN std_logic; d : IN std_logic; e : OUT std_logic_vector(7 downto 0)

);END model1 ;

Example: Using IEEE Types

Identifiers’ Name

• VHDL allows identifiers to be:– Any mix of printable characters and numbers

• No special characters allowed except the underscore

• An identifier can’t begin with a number• An identifier can’t begin/end with underscores• No two successive underscores• Should not be a VHDL keyword

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Identifiers example

• accum_1• 1mux• encoder*10• _AdderssBus• AddressBus_• Address__Bus• BH_z3a• data@bus

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Exercise 1

• Write the entity of the following:– 1-bit Full Adder

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Answer of Exercise 1

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LIBRARY ieee; USE ieee.std_logic_1164.all;

ENTITY fullAdder IS PORT( In1, In2, CarryIn : IN std_logic;

Sum : OUT std_logic; CarryOut : OUT std_logic);

END fullAdder;

Architecture Description

architecture <arch_name> of <entity_name> is -- architecture declarations begin -- architecture bodyend architecture;

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ARCHITECTURE rtl OF model1 IS SIGNAL x : std_logic; SIGNAL y : std_logic;

BEGIN x <= a AND b; y <= c AND d; e <= x OR y;

END rtl;

Example:

Syntax:• A given architecture represents one possible implementation for its associated entity– Architecture declaration: defines internal

signals, components, types …etc to be used in architecture body

– Architecture body: defines implementation details of input/output relationship

• Multiple architectures can exist for each entity

signal <sig_name> : <sig_type>;

Internal signals

Concurrent Assignments

Architecture Body

<target> <= <expression>;

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ARCHITECTURE expr OF example1 IS SIGNAL u, w, x, y, z : std_logic; SIGNAL a, b, c : integer;

BEGIN x <= y AND z; -- logical expression w <= NOT x; u <= w; -- direct assignment c <= a + b; -- arithmetic expression

END expr;

Example:

Syntax:

• Architecture body can only contain concurrent statements, in this module we will only focus on– Concurrent assignments– With-select– When-else

• Concurrent Assignments– LHS can be an internal signal or an output port– RHS is an expression that operates on internal signal

and/or input ports

Arithmetic Operators+ , - , * , /

Logical OperatorsNOTAND, NANDOR, NORXOR, XNOR

Internal signals

LIBRARY ieee; USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;ENTITY illegal IS PORT( A : IN std_logic; B : IN std_logic; C : IN std_logic; F : OUT std_logic; G : OUT std_logic); END illegal ;ARCHITECTURE struct OF illegal IS -- Internal signal declarations SIGNAL sig1 : std_logic; SIGNAL sig2 : std_logic; SIGNAL sig3 : std_logic; BEGIN F <= sig3 AND sig1 AND C; G <= F AND sig1 AND sig2; -- Reading Out port F is illegal sig3 <= NOT(A); sig1 <= NOT(B); sig2 <= NOT(C); END struct;

architecture <arch_name> of <entity_name> is -- architecture declarations signal <sig_name> : <sig_type>;begin -- assign to internal signal <sig_name> <= <expression>; -- read the internal signal <sig_name> <= <expression>;end architecture;

Syntax:

• We use Internal Signals for:– Internal connections in structural description– Intermediate calculations– Avoid illegal port usage situations:

• Read Output port

Illegal use of an output port(used as the “and” gate

input)

Example:

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Internal signalsLIBRARY ieee; USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;ENTITY legal IS PORT( A : IN std_logic; B : IN std_logic; C : IN std_logic; F : OUT std_logic; G : OUT std_logic); END legal ;ARCHITECTURE struct OF legal IS -- Internal signal declarations SIGNAL sig1 : std_logic; SIGNAL sig2 : std_logic; SIGNAL sig3 : std_logic; SIGNAL sig4 : std_logic;BEGIN sig4 <= sig3 AND sig1 AND C; -- using internal signal sig4 G <= sig4 AND sig1 AND sig2; F <= sig4; sig3 <= NOT(A); sig1 <= NOT(B); sig2 <= NOT(C); END struct;

Internal Signals used for intermediate relations

Example:

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Expressions & Operators

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Example:

• Each operator is defined for specific data type(s)– Arithmetic operators are defined for standard integer types– Logical operators are defined for the standard bit, bit_vector types– Logical & arithmetic operators are defined for std_logic & std_logic_vector

types in IEEE std_logic_* packages You need to use the appropriate package before applying an operator on a type

ARCHITECTURE struct OF expr IS -- Internal signal declarations SIGNAL x, y, z : integer; BEGIN -- Operators can be chained to form complex expressions F <= C AND (NOT(B)) AND (NOT(A)); -- parentheses control association of operators and operands -- use parentheses for readability G <= (C OR (NOT(A))) XOR (NOT(B) AND (B NOR C)); Z <= X + Y; -- using addition operator defined for integer typeEND struct;

Operators*

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Operation Package Comments

std_logic <= std_logic AND std_logic; ieee.std_logic_1164 Similarly NAND, OR, NOR, XOR…etc

std_logic_vector <= std_logic _vector AND std_logic_vector;

ieee.std_logic_1164 Similarly NAND, OR, NOR, XOR…etc

boolean <= std_logic_vector > std_logic_vector; ieee.std_logic_1164 Similarly < , >=, <=

boolean <= std_logic_vector /= std_logic_vector; ieee.std_logic_1164 Not Equal operator

std_logic_vector <= std_logic_vector +/- integer ieee.std_logic_unsigned Unsigned addition/subtraction

std_logic_vector <= std_logic_vector +/- integer ieee.std_logic_signed Signed addition/subtraction

std_logic_vector <= std_logic_vector +/- std_logic_vector

ieee.std_logic_unsigned Unsigned addition/subtraction

std_logic_vector <= std_logic_vector +/- std_logic ieee.std_logic_signed Signed addition/subtraction

*More operator will be presented throughout the course

Operators

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Example:

-- Library & package used for architecture scopeLIBRARY ieee; USE ieee.std_logic_unsigned.all; -- Need to use unsigned arithmetic operators

ARCHITECTURE expr OF example1 IS SIGNAL u, w : std_logic_vector(3 downto 0); SIGNAL a : integer;

BEGIN -- Adding an integer to an std_logic_vector returning std_logic_vector u <= w + a;

END expr;

Where’s the Carry Out?!

Exercise 2

• Write the architecture of the following:– 1-bit Full Adder

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Answer of Exercise 2

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LIBRARY ieee; USE ieee.std_logic_1164.all;

ENTITY fullAdder IS PORT( In1, In2, CarryIn : IN std_logic;

Sum : OUT std_logic;

CarryOut : OUT std_logic);END fullAdder; ARCHITECTURE expr OF fullAdder IS

signal temp : std_logic; BEGIN

temp <= In1 XOR In2; Sum <= temp XOR CarryIn;

CarryOut <= (In1 AND In2) OR (CarryIn AND temp);END expr;

Architecture Body

With <select_signal> select <target> <= <expression> when <value>, <expression> when <value>, ….

< expression> when others;

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Architecture behave of mux_with isBegin

With sel selectF <= a when "00", b when "01", c when "10", d when others; -- needed to cover missing “sel” values

End Architecture;

Example:

Syntax:

• With-Select– <select_signal> can be an internal signal or an

input port– <target> can be an internal signal or an output

port– <value> constants representing one of possible

<select_signal> values.– “When others” is a must if not all values of

<select_signal> are covered

Sel(1:0)

bF

a

cd

Architecture Body

<target> <= <expression> when <condition> else <expression> when <condition> else <expression> when <condition> … else <expression> ;

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Architecture behave of mux_when isBegin

F <= a when sel = "00" elseb when sel = "01" elsec when sel = "10" elsed; -- This is one statement with semicolon at the end only

End Architecture ;

Example:

Syntax:

• When-else– LHS can be an internal signal or an output port– RHS is an expression that operates on internal

signal and/or input ports when the branch condition is true

– Last “else” branch covers all missing conditions

Sel(1:0)

bF

a

cd

Exercise 3 • Write the entity and architecture of the

following (using with-select then using when-else):– 2x4 Decoder– 4x2 Encoder

Fa

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Decoder2x4

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Encoder4x2

Decoder 2x4(with-select)

library IEEE; use IEEE.std_logic_1164.all; entity decoder2x4 is port(a: in std_logic_vector(1 downto 0);

F: out std_logic_vector(3 downto 0)); end entity; Architecture behave of decoder2x4 is Begin

with A select F <= "0001" when "00", "0010" when "01", "0100" when "10", "1000" when others;

End Architecture;

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Decoder 2x4 (when-else)

library IEEE; use IEEE.std_logic_1164.all; entity decoder2x4 is

port(a: in std_logic_vector(1 downto 0); F: out std_logic_vector(3 downto 0) ); end entity; Architecture behave of decoder2x4 is Begin

F <= "0001" when a = "00" else "0010" when a = "01" else "0100" when a = "10" else "1000";

End Architecture;

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Encoder4x2 (with-select)library IEEE; use IEEE.std_logic_1164.all;

entity encoder4x2 is port(a: in std_logic_vector(3 downto 0); F: out std_logic_vector(1 downto 0) );

end entity;

Architecture behave of encoder4x2 is Begin

With a select F <= "00" when "0001", "01" when "0010", "10" when "0100", "11" when others;

End Architecture;

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4 2

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Next Module

• Module 2: Writing more complex Models

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Contacts

• You can contact us at:– http://www.embedded-tips.blogspot.com/

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