cs 362: computer design lecture 18: multipliers, registers, alu · 2019. 12. 5. · reading: an...
TRANSCRIPT
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CS 362: Computer DesignLecture 18: Multipliers, Registers,
ALU
Mitchell TheysUniversity of Illinois at Chicago
November 1st, 2018
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Multiplication
• Multiply by 1 bit to form a partial product• Add partial products together
010* 110‐‐‐‐‐‐‐‐
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In the following multiplication, what equation will give you c1?
A. a1b
B. a1 + b
C. a1b + a0b
D. None of the above
a2a1a0* b‐‐‐‐‐‐‐‐‐‐‐c2c1c0
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Forming a Partial Product
• AND each digit of a with the appropriate digit from b.
• Add the appropriate number of 0s
010* 110‐‐‐‐‐‐‐‐000010001000‐‐‐‐‐‐‐‐01100
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4‐bit Multiplier• Use AND gates to find each partial product
• Add partial products together to get the final product
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Assuming ripple‐carry adders, and only counting the 7‐bit adder and AND gates, what is the gate delay of this multiplier?
A. 8B. 11
C. 15D. 18
E. None of the above
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Questions on Multiplication?
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Recall: Datapath
• How to build the register file
• How to build the ALU
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261 Recall: Register File
• Set of registers that can be written/read by supplying a register number
• Write port• Two Read ports
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Recall: Decoder
• Interprets n inputs (ABC) as a n bit binary number
• Where ABC represents number x, sets output Dx to 1, all other outputs to 0
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Writing
• Use a decoder to select exactly one register to write to
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W_addr is 102, W_data is 12, and w_en is 1. What will the register values be in the next clock cycle?
Reg0 Reg1 Reg2 Reg3
current 5 6 7 8
A 0 0 12 0
B 5 6 12 8
C 5 6 7 8
D 5 12 7 8
E. None of the above
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Reading
• For each read port, use a multiplexor to choose the appropriate register to output
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Reading: An optimization
• Large multiplexers involve many wires and gates
• Scale poorly with high bit‐widths – i.e. 64 bits = 64 1‐bit multiplexers!
• Can use a more efficient option
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Tri‐State Buffer
• Has a control a, an input b, and an output y• If a is 1, the value of b is output• If a is 0, a “high impedance” state is output (neither high voltage (1) or low voltage (0)– Essentially acts like the wire is disconnected
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Tri‐State Buffer
• Assume we have multiple circuits attached to a single wire
• Buffers outputting high impedance will not affect the value of the shared wire
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Read with Tri‐State Buffers
• Use a decoder to set one tri‐state buffer to 1, rest to 0
• One buffer outputs a value, the rest output high impedance
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Complete Register File
• Decoders select write and two read registers
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Given the values below, what will the register values be on the next clock
cycle?R0 R1 R2 R3 RA
dataRBdata
curr 5 6 7 8
A 5 6 7 8
B 0 11 15 8
C 5 6 15 8 5
D 5 6 15 8 5 8
E. None of the above
W_addr W_en W_data RA_addr RA_en RB_addr RB_en
10 1 15 00 1 11 0
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Recall: Load Registers
• Send output back to input• Use mux to choose between loading the new value, or the previous value
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Multi‐Function Registers
• We want registers to have additional capabilities, like clearing (setting to 0)– Frequently used on startup
• Add a new multiplexer input hardcoded to 0
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Assume that input D is 110 and output Q is 010. Pick the register values for
each set of control signals
clr ld
0 0
1 0
0 1
A
000
010
110
B
010
110
000
C
010
000
110
D
110
000
010
E. None of the above
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261 Recall: Shift Instructions
• Shift amount specified as either immediate or in %cl
• sal k,D / shl k,D – left shift D by k• sar k,D – arithmetic right shift D by k
– Fills in with sign bit• shr k,D – logical right shift D by k
– Fills in with zeros
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Shift Registers
• Add ability to shift one to the right
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Assume shr_in = 1, shr = 1, ld = 0 and Q = 010. What will the register value
be next?
A. 000B. 001C. 010
D. 101E. None of the above
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Controlling Registers
• As registers have more functions, we need to be able to translate between inputs to control signals to multiplexers
• Add combinatorial logic to make this translation
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What is the equation for s1?
c l s s1 s0 func
0 0 0 0 0 maintain
1 0 0 1 0 clear
0 1 0 0 1 load
0 0 1 1 1 shift
mux mux
register register
0 0d1 d0
s1s0
shr_in
A. s1 = l’B. s1 = cl’C. s1 = cl’s’ + c’l’s
D. s1 = c’ls’ + c’l’sE. None of the above
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Questions about Registers?
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ALU
• Arithmetic‐logic unit
• Implements all mathematical/logical instructions– Add, inc, sub, dec, xor, and . . .
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ALU Design: Extending the Adder
• We can implement an ALU by extending an adder with appropriate inputs
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What will w and x be to implement a ‐ b?
A. w = 0, x = 0B. w = 0, x = 1C. w = 1, x = 0
D. w = 1, x = 1E. None of the above
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What will w and x be to implement a AND b?
A. w = 0, x = 0B. w = 0, x = 1C. w = 1, x = 0
D. w = 1, x = 1E. None of the above
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More Advanced ALU
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261 Recall: Instruction EncodingByte 0 1 2 3 4 5
pushq rA A 0 rA F
jXX Dest 7 fn Dest
popq rA B 0 rA F
call Dest 8 0 Dest
rrmovq rA, rB 2 0 rA rB
irmovq V, rB 3 0 F rB V
rmmovq rA, D(rB)4 0 rA rB D
mrmovq D(rB), rA5 0 rA rB D
OPq rA, rB 6 fn rA rB
ret 9 0
halt 0 0
nop 1 0
cmovXX rA, rB 2 fn rA rB
6 7 8 9
• Every instruction is encoded as a series of bytes
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Recall 261: Execute
• Icode & Function determine what ALU does• Set CC determines if control codes are set• ALU A, ALU B determine if inputs are from registers or a constant in instruction
CC ALU
ALUA
ALUB
ALUfun.
Cnd
icode ifun valC valBvalA
valE
SetCC
cond
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ALU Control
• Function code is sent through combinatorial control logic to become selector bits for the ALU
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Reading
• Next lecture: Complete Processor – 7.7 – 7.14
• 4‐page project write‐up due Nov. 9