cs m51a/ee m16 winter’05 section 1 logic design of digital systems lecture 15

Y. He @ 04/19/23 CSM51A/EEM16-Sec.1 W’05 L15.1

CS M51A/EE M16 Winter’05 Section 1 Logic Design of Digital Systems

Lecture 15

Yutao He

[email protected]

4532B Boelter Hall

http://courseweb.seas.ucla.edu/classView.php?term=05W&srs=187154200

March 9

W’05


Outline

• Recap - Combinational macro modules– Decoders– Encoders– Shifters

• Combinational macro modules– Multiplexers– Demultiplexers

• Chapter 11 Sequential Modules– Registers– Shift registers


Chapter 9 - OverviewCombinational Systems

Gate networks(AND, OR, NAND, etc.)

Chapters 2-6

Design Analysis

Module networks(DEC/ENC, MUX/DEMUX, Shifter.)

Chapter 9

• Basic Questions:– What are each module’s property?

* inputs, outputs, functions (high-level and binary level)

– How to implement it using logic gates?– How to design a comb. system using these modules?– How to analyze a comb. system using these modules?


Multiplexer (MUX)

EN

E

2n-I

np

ut

Mu

ltip

lexe

r

0

1

2n-1

x0

x1

x2n

-1

Data Inputs

n-1

sn-1

0

s0 Selection Inputs

z

Data Output


Multiplexer - Specification

High-Level

Binary-Level


Multiplexer - Implementation (1)

Implementation of MUX with AND/OR gates


Multiplexer - Implementation (2)

Implementation of MUX with transmission gates


Multiplexer (Tree) Networkss = 9 s3 s2 s1 s0 = 1001

10

01

z = x9


Applications of MUXes

n-bit Simple Shifter


Applications of MUXes (Cont’d)

4-bit Right-3 Unidirectional Shifter


Design Using MUXes• Key observations:

– A 2n-Input MUX corresponds to a n-input switching function.– Data outputs store output values of the switching function.– Selection inputs correspond to the inputs of the switching function.– A 2n-Input MUX stores the truth table of a n-input switching

function.

• Basic Idea:– MUXes are Universal Set

* assuming constants 0 and 1 are available

EN

E

2n-I

np

ut

Mu

ltip

lexe

r

01

2n-1

x0

x1

x2n

-1

n-1

sn-1

0

s0

z


Example 9.12 - One-Bit Full Adder

x 0 0 0 0 1 1 1 1

y 0 0 1 1 0 0 1 1

Cin 0 1 0 1 0 1 0 1

S 0 1 1 0 1 0 0 1

Cout 0 0 0 1 0 1 1 1

• Need two 8-Input MUXes

1-BitFull Adder

xy

carry_in

sumcarry-out


One-Bit Full Adder (Cont’d)

x 0 0 0 0 1 1 1 1

y 0 0 1 1 0 0 1 1

Cin 0 1 0 1 0 1 0 1

S 0 1 1 0 1 0 0 1

Cout 0 0 0 1 0 1 1 1

0

11

0

0

1

1

0

E = 1 E = 1

EN

8-In

pu

tM

ult

iple

xer

01

2

x

0

Cin

s

y

234567

1

EN

8-In

pu

tM

ult

iple

xer

01

2

x

0

Cin

Cout

y

234567

1

0

00

1

1

1

0

1


Design Using MUXes with Small Sizes

• Is it possible to design a n-input switching function using a 2m-input MUX, where m < n?• The answer is Yes!• How?

– Basic idea:* Use data inputs of a MUX to store variables

– Basic approaches:* Truth table* K-Map* Boolean algebra


1-Bit FA Revisited: Using Truth Table

Cin

C’inC’in

Cin

x y

EN

E = 1

4-In

pu

tM

UX

01

1

s23

0

x 0 0 0 0 1 1 1 1

y 0 0 1 1 0 0 1 1

Cin 0 1 0 1 0 1 0 1

S 0 1 1 0 1 0 0 1

Cin

C’in

C’in

Cin

• Uses 4-input Muxes


Using Truth Table (Cont’d)

0

CinCin

1

EN

E = 1

4-In

pu

tM

UX

01

1

x

Cout

y

23

0

x 0 0 0 0 1 1 1 1

y 0 0 1 1 0 0 1 1

Cin 0 1 0 1 0 1 0 1

Cout 0 0 0 1 0 1 1 1

0

Cin

Cin

1


1-Bit FA Revisited: Using K-Map

0 1 3 2

4 5 7 6x

Cin

y

0 1

1 0

0 1

1 0

Cin C’in

C’in Cinx

y

Cin

C’inC’in

Cin

EN

E = 1

4-In

pu

tM

UX

01

1

x

s

y

23

0


Using K-Map (Cont’d)

0

CinCin

1

EN

E = 1

4-In

pu

tM

UX

01

1

x

Cout

y

23

0

0 1 3 2

4 5 7 6x

Cin

y

0 0

0 1

1 0

1 1

0 Cin

Cin 1x

y


1-Bit FA: Using Boolean Algebra

Cin

C’inC’in

Cin

EN

E = 1

4-In

pu

tM

UX

01

1

x

s

y

23

0

S = x’y’Cin + x’yC’in + xy’C’in + xyCin = (x’y’)Cin + (x’y)C’in + (xy’)C’in + (xy)Cin

m0 m1 m2 m3


Using Boolean Algebra (Cont’d)

Cout = x’yCin + xy’Cin + xyC’in + xyCin = (x’y)Cin + (xy’)Cin + (xy)(C’in + Cin) = (x’y)Cin + (xy’)Cin + (xy)

m1 m2 m3

0

CinCin

1

EN

E = 1

4-In

pu

tM

UX

01

1

x

Cout

y

23

0


Design Using Network of 2-Input MUXes

z = x0s’+x1sEN

E

2-In

pu

tM

UX

0

1

s

z

0

x0

x1

EN

E = 1

2-In

pu

tM

UX

0

1

x

z

0

1

0

EN

E = 1

2-In

pu

tM

UX

0

1

x0

z

0

0

x1

NOT gate z = x’ AND gate z = x0 x1


Shannon Theorem• The Formula:

– f(xn-1, …, x1, x0) = f(xn-1, …, x1, 0) x’0+ f(xn-1, …, x1, 1) x0

• The idea:– A function with more inputs can be decomposed into two functions with fewer inputs.

• The Application:– A n-input switching function can be implemented with 2-input MUXes by repeatedly

applying the Shannon Theorem.

EN

E

2-In

pu

tM

UX

0

1

x0

f(xn-1, …, x1, x0)

0

f(xn-1, …, x1, 0)

f(xn-1, …, x1, 1)


Example 6.8

• Implement the following function with 2-Input MUXes:– f(x3, x2, x1, x0) = x3( x1+ x2x0)

• Decomposition:– The first level:

* f(x3, x2, x1, 0 ) = x3 x1

* f(x3, x2, x1, 1 ) = x3 ( x1 + x2)

– The second level:* f(x3, x2, 0, 0 ) = 0

* f(x3, x2, 0, 1 ) = x3x2

* f(x3, x2, 1, 0 ) = x3

* f(x3, x2, 1, 1 ) = x3


Example 6.8 (Cont’d)

• The third level:– f(x3, 0, 0, 0 ) = 0, f(x3, 1, 0, 0 ) = 0

– f(x3, 0, 0, 1 ) = 0, f(x3, 1, 0, 1 ) = x3

– f(x3, 0, 1, 0 ) = x3, f(x3, 1, 1, 0 ) = x3

– f(x3, 0, 1, 1 ) = x3, f(x3, 1, 1, 1 ) = x3

f

0

1

x1

0

0

0

1

x0

00

1

x1

0

0

1

x2

0x3

0

x3

x3

f0 0

1

x1

0

0

1

x0

00

1

x2

0x3 x3

0


Demultiplexer (DEMUX)

EN

E

2n -

Ou

tpu

tD

emu

ltip

lexe

r

0

1

2n-1

y0

y1

y2n

-1

Data Inputs

n-1

sn-1

0

s0 Selection Inputs

Data Output

x


Demultiplexer: High-Level Spec


Example 9.13: 4-Output DEMUX


4-Output DEMUX (Cont’d)


Application of DEMUXes


Chapter 11 Sequential ModulesSequential Systems

Flip-Flops(D, JK, SR, T FFs, etc.)

Chapters 7-8

Design Analysis

Module networks(Register, Shift Register, Counter)

Chapter 11

• Basic Questions:– What are each module’s property?

* inputs, outputs, functions (high-level and binary level)

– How to implement it using FFs and logic gates?

– How to design a sequential system using these modules?

– How to analyze a sequential system using these modules?


n-Bit Register


n-Bit Register - High-Level Spec


4-Bit Register - Implementation


Timing Behavior of Registers


Design Using Registers

• Example 11.1


Example 11.1 - Using FFs


Example 11.1- Using Register

0

LD

2-B

it R

egis

ter

CLK CLR

y0

y1

Y1

Y0

x

When x = 1


Shift Registers

Shift RegisterCLK

CTL

m

n

• Basic Types:– Serial In/Serial Out (SI/SO): m=n=1– Serial In/Parallel Out (SI/PO): m=1, n> 1– Parallel In/Serial Out (PI/SO): m>1, n=1– Parallel In/Parallel Out (PI/PO): m, n > 1


Serial-In/Serial-Out Shift Registers


Serial-In/Parallel-Out Shift Registers


Parallel-In/Serial-Out Shift Registers


Parallel-In/Parallel-Out Shift Registers


PI/PO Shift Registers: High-Level Spec


PI/PO Shift Register Control

• Present state s(t) = 0101, data input x(t)=1110


PI/PO Shift Register: Implementation


Applications of Shift Registers

• Serial interconnection of two systems


Applications of Shift Registers (Cont’d)

• Bit-serial operations


Design Using Shift Registers

• For finite-memory sequential systems, shift registers can be used as the state register:

• Example 11.2:– z(t) = 1 whenever x(t) • x(t-8) = 1


Design Using Shift Registers (Cont’d)

• Shift registers are handy for implementing pattern detectors

• Example 11.3– Design a pattern detector that detects 011101101


Networks of Shift Registers


Summary

• Combinational macro modules– MUXes– DEMUXes

• Sequential macro modules:– Registers– Shift Registers


Next Lecture

• Chapter 11– Counters

• Chapter 12– ROM

cs m51a/ee m16 winter’05 section 1 logic design of digital systems lecture 15

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