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CSCE 932, Spring 2007

Yield Analysis and Product Quality

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Yield Analysis & Product Quality

Yield, defect level, and manufacturing cost Clustered defects and yield modelTest data analysisExample: SEMATECH chipSummary

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Test Performance

Test

Good/Bad? Good/Bad?

PASSFAIL

GoodGoodBad Bad

ALL CHIPS

GoodBad TestedAs Good

Good TestedAs Bad

Bad(Yield)

(Yield Loss)(Overkill)

(Ybg)

(Reject Rate or DPM)

(Tester Yield)

These two items

determine the tester

performance

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Reject Rate (DPM) BasicsReject Rate or Defectives per million (DPM) is a measure of product quality

Zero DPM can be achieved by:Perfect yield (100% yield => no bad parts)

Perfect test (100% coverage => all bad parts eliminated in testing, all good parts passed)

Neither fabrication nor testing process is perfect hence non-zero DPM is a fact of life.

DPM minimization is an important goal of quality-conscious companies.

For commercial VLSI chips a DL greater than 500 dpm is considered unacceptable.

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Ways to Estimate DPM

Field-Return DataGet customers to return all defective parts, then analyze and sort them correctly to estimate DPM

DPM Modeling and ValidationAnalytical approach using yield and test parameters in the model to predict yield. Steps:1. Develop a model2. Calibrate it (Determine parameter values)3. Estimate the DPM4. Verify against actual measurements5. Recalibrate in time and for new designs or processes

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VLSI Chip Yield and Cost

Manufacturing Defect: Chip area with electrically malfunctioning circuitry caused by errors in the fabrication process.Good Chip: One without a manufacturing defect.Yield (Y): Fraction (or percentage) of good chips produced in a manufacturing process is called the yield. Chip Cost:

waferon the sites chip ofNumber Yield

wafera testingand gfabricatin ofCost

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Clustered VLSI Defects

WaferDefects

Faulty chips

Good chips

Unclustered defectsWafer yield = 12/22 = 0.55

Clustered defects (VLSI)Wafer yield = 17/22 = 0.77

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Yield Modeling

Statistical model, based on distribution of defects on a chip:

p(x) = Prob(number of defects on a chip = x)Yield = p(0)

Empirical evidence shows that defects are not uniformly randomly distributed but are clustered.A form of negative binomial pdf is found to track well with observed data.

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Binomial and Negative Binomial pdf

Bernoulli trials: A biased coin with success probability = p is tossed repeatedly.Binomial: If the coin is tossed n times what is the probability of x successes?Negative Binomial: What is the probability of x failures occurring before the r-th success?

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Mathematical Definitions

Binomial:

Negative Binomial*:

,...,n,xqpx

n)p,n|x(p )x(x 10for 1

-p) (q ,, ..., x

qpx

xr

qpx

xrp)p,r|x(p

xr

xr

1 where,10for

1

1 1

* “Negative” comes from the fact the the distribution can also be written as ( 1) ( )r r xrp q

x

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Generalized Negative Binomial Distribution

When r is a non-integer, the above interpretation breaks down but the form is useful in modeling count data:

-p) (q ,, ..., x

qp)p,r|x(p xr

1 where,10for

1)(x(r)

x)(r

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For modeling the defect distribution we make the following substitutions in the above eqn:

where,

/Adp

/Ad

/Adq,r

1

1 ,

1

d = Defect density = Average number of defects per unit of chip area

A = Chip area

= Clustering parameter

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x

x

)/Ad(

)/Ad(

)x()(

)x(

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p(x) = Prob(number of defects on chip =x)

Defect Distribution Equation

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Yield Equation

Y = Prob ( zero defect on a chip ) = p (0)

Y = ( 1 + Ad / )

Example: Ad = 1.0, = 0.5, Y = 0.58

Unclustered defects: = , Y = e - Ad

Example: Ad = 1.0, = , Y = 0.37

too pessimistic !

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Determination of DL from Test Data (Basic Idea)

Combine tester data:#chips passing vs. test-pattern number

with the fault coverage data:cum. fault coverage vs. test-pattern number to derive the data:#chips passing vs. fault coverage

Extend the defect model to a fault model (yield of chips vs. fault coverage) and determine its parameters by curve fitting.

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Modified Yield EquationThree parameters:

Fault density, f = average number of stuck-at faults per unit chip areaFault clustering parameter, Stuck-at fault coverage, T

The modified yield equation:

Y (T ) = (1 + TAf / ) -

Assuming that tests with 100% fault coverage(T =1.0) remove all faulty chips,

Y = Y (1) = (1 + Af / ) -

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Defect Level Y (T ) - Y (1)DL (T ) = -------------------- Y (T )

( + TAf )

= 1 - --------------------

( + Af )

Where T is the fault coverage of tests,Af is the average number of faults on thechip of area A, is the fault clusteringparameter. Af and are determined bytest data analysis.

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Example: SEMATECH ChipBus interface controller ASIC fabricated and tested at IBM, Burlington, Vermont116,000 equivalent (2-input NAND) gates304-pin package, 249 I/OClock: 40MHz, some parts 50MHz0.45 CMOS, 3.3V, 9.4mm x 8.8mm areaFull scan, 99.79% fault coverageAdvantest 3381 ATE, 18,466 chips tested at 2.5MHz test clockData obtained courtesy of Phil Nigh (IBM)

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Test Coverage from Fault Simulator

Stu

ck-a

t fa

ult

covera

ge

Vector number

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Measured Chip Fallout

Vector number

Measu

red

ch

ip f

allou

t

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Model Fitting

Y (T ) for Af = 2.1 and = 0.083

Measured chip fallout

Y (1) = 0.7623

Ch

ip f

allou

t an

d c

om

pu

ted

1

-Y (T ) Chip fallout vs. fault coverage

Stuck-at fault coverage, T

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Computed DL

Stuck-at fault coverage (%)

Defe

ct

level in

pp

m

237,700 ppm (Y = 76.23%)

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SummaryVLSI yield depends on two process parameters, defect density (d ) and clustering parameter ()Yield drops as chip area increases; low yield means high costFault coverage measures the test qualityDefect level (DL) or reject ratio is a measure of chip qualityDL can be determined by an analysis of test dataFor high quality: DL < 500 ppm, fault coverage ~ 99%