csd19538q2 100-v n-channel nexfet™ power mosfet
TRANSCRIPT
Qg - Gate Charge (nC)
VG
S -
Gat
e-to
-Sou
rce
Vol
tage
(V
)
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50
1
2
3
4
5
6
7
8
9
10
D004
ID = 5 AVDS = 50 V
VGS - Gate-to-Source Voltage (V)
RD
S(o
n) -
On-
Sta
te R
esis
tanc
e (m:
)
0 2 4 6 8 10 12 14 16 18 200
20
40
60
80
100
120
140
160
180
200
D007
TC = 25qC, ID = 5 ATC = 125qC, ID = 5 A
1D
2
D
D
3
D
4
D 5
G
6
SS
P0108-01
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Folder
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD19538Q2SLPS582A –JULY 2016–REVISED JANUARY 2017
CSD19538Q2 100-V N-Channel NexFET™ Power MOSFET
1
1 Features1• Ultra-Low Qg and Qgd
• Low-Thermal Resistance• Avalanche Rated• Lead Free• RoHS Compliant• Halogen Free• SON 2-mm × 2-mm Plastic Package
2 Applications• Power Over Ethernet (PoE)• Power Sourcing Equipment (PSE)• Motor Control
3 DescriptionThis 100-V, 49-mΩ, SON 2-mm × 2-mm NexFET™power MOSFET is designed to minimize losses inpower conversion applications.
Top View
.
.
Product SummaryTA = 25°C TYPICAL VALUE UNIT
VDS Drain-to-Source Voltage 100 V
Qg Gate Charge Total (10 V) 4.3 nC
Qgd Gate Charge Gate-to-Drain 0.8 nC
RDS(on) Drain-to-Source On ResistanceVGS = 6 V 58
mΩVGS = 10 V 49
VGS(th) Threshold Voltage 3.2 V
Device Information(1)
DEVICE QTY MEDIA PACKAGE SHIP
CSD19538Q2 30007-Inch Reel
SON2.00-mm x 2.00-mm
Plastic Package
TapeandReelCSD19538Q2T 250
(1) For all available packages, see the orderable addendum atthe end of the data sheet.
Absolute Maximum RatingsTA = 25°C VALUE UNIT
VDS Drain-to-Source Voltage 100 V
VGS Gate-to-Source Voltage ±20 V
ID
Continuous Drain Current (Package Limited) 14.4
AContinuous Drain Current (Silicon Limited),TC = 25°C 13.1
Continuous Drain Current(1) 4.6
IDM Pulsed Drain Current(2) 34.4 A
PDPower Dissipation(1) 2.5
WPower Dissipation, TC = 25°C 20.2
TJ,Tstg
Operating Junction Temperature,Storage Temperature –55 to 150 °C
EASAvalanche Energy, Single PulseID = 12.6 A, L = 0.1 mH, RG = 25 Ω 8 mJ
(1) Typical RθJA = 50°C/W on a 1-in2, 2-oz Cu pad on a 0.06-inthick FR4 PCB.
(2) Max RθJC = 6.2°C/W, pulse duration ≤ 100 μs, duty cycle ≤1%.
RDS(on) vs VGS Gate Charge
2
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Table of Contents1 Features .................................................................. 12 Applications ........................................................... 13 Description ............................................................. 14 Revision History..................................................... 25 Specifications......................................................... 3
5.1 Electrical Characteristics........................................... 35.2 Thermal Information .................................................. 35.3 Typical MOSFET Characteristics.............................. 4
6 Device and Documentation Support.................... 7
6.1 Receiving Notification of Documentation Updates.... 76.2 Community Resources.............................................. 76.3 Trademarks ............................................................... 76.4 Electrostatic Discharge Caution................................ 76.5 Glossary .................................................................... 7
7 Mechanical, Packaging, and OrderableInformation ............................................................. 87.1 Q2 Package Dimensions .......................................... 87.2 Q2 Tape and Reel Information................................ 11
4 Revision History
Changes from Original (July 2016) to Revision A Page
• Changed test voltage VDS from 100 V : to 50 V in Gate Charge curve.................................................................................. 1• Changed test voltage VDS from 100 V : to 50 V in Figure 4 ................................................................................................... 4
3
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5 Specifications
5.1 Electrical CharacteristicsTA = 25°C (unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITSTATIC CHARACTERISTICSBVDSS Drain-to-source voltage VGS = 0 V, ID = 250 μA 100 VIDSS Drain-to-source leakage current VGS = 0 V, VDS = 80 V 1 μAIGSS Gate-to-source leakage current VDS = 0 V, VGS = 20 V 100 nAVGS(th) Gate-to-source threshold voltage VDS = VGS, ID = 250 μA 2.8 3.2 3.8 V
RDS(on) Drain-to-source on resistanceVGS = 6 V, ID = 5 A 58 72
mΩVGS = 10 V, ID = 5 A 49 59
gfs Transconductance VDS = 10 V, ID = 5 A 19 SDYNAMIC CHARACTERISTICSCiss Input capacitance
VGS = 0 V, VDS = 50 V, ƒ = 1 MHz349 454 pF
Coss Output capacitance 69 90 pFCrss Reverse transfer capacitance 12.6 16.4 pFRG Series gate resistance 4.6 9.2 ΩQg Gate charge total (10 V)
VDS = 50 V, ID = 5 A
4.3 5.6 nCQgd Gate charge gate-to-drain 0.8 nCQgs Gate charge gate-to-source 1.6 nCQg(th) Gate charge at Vth 1.0 nCQoss Output charge VDS = 50 V, VGS = 0 V 12.3 nCtd(on) Turnon delay time
VDS = 50 V, VGS = 10 V,IDS = 5 A, RG = 0 Ω
5 nstr Rise time 3 nstd(off) Turnoff delay time 7 nstf Fall time 2 nsDIODE CHARACTERISTICSVSD Diode forward voltage ISD = 5 A, VGS = 0 V 0.85 1.0 VQrr Reverse recovery charge VDS= 50 V, IF = 5 A,
di/dt = 300 A/μs94 nC
trr Reverse recovery time 32 ns
(1) RθJC is determined with the device mounted on a 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in (3.81-cm × 3.81-cm), 0.06-in (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
(2) Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu.
5.2 Thermal InformationTA = 25°C (unless otherwise stated)
THERMAL METRIC MIN TYP MAX UNITRθJC Junction-to-case thermal resistance (1) 6.2 °C/WRθJA Junction-to-ambient thermal resistance (1) (2) 65 °C/W
GATE Source
DRAIN
M0161-01
GATE Source
DRAIN
M0161-02
4
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Max RθJA = 65°C/Wwhen mounted on 1 in2
(6.45 cm2) of 2-oz(0.071-mm) thick Cu.
Max RθJA = 250°C/Wwhen mounted on aminimum pad area of2-oz (0.071-mm) thickCu.
5.3 Typical MOSFET CharacteristicsTA = 25°C (unless otherwise stated)
Figure 1. Transient Thermal Impedance
TC - Case Temperature (qC)
VG
S(t
h) -
Thr
esho
ld V
olta
ge (
V)
-75 -50 -25 0 25 50 75 100 125 150 1752.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
D006VGS - Gate-to-Source Voltage (V)
RD
S(o
n) -
On-
Sta
te R
esis
tanc
e (m:
)
0 2 4 6 8 10 12 14 16 18 200
20
40
60
80
100
120
140
160
180
200
D007
TC = 25qC, ID = 5 ATC = 125qC, ID = 5 A
Qg - Gate Charge (nC)
VG
S -
Gat
e-to
-Sou
rce
Vol
tage
(V
)
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50
1
2
3
4
5
6
7
8
9
10
D004VDS - Drain-to-Source Voltage (V)
C -
Cap
acita
nce
(pF
)
0 10 20 30 40 50 60 70 80 90 1001
10
100
1000
10000
D005
Ciss = Cgd + CgsCoss = Cds + CgdCrss = Cgd
VDS - Drain-to-Source Voltage (V)
I DS -
Dra
in-t
o-S
ourc
e C
urre
nt (
A)
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50
3
6
9
12
15
18
21
24
27
30
D002
VGS = 6 VVGS = 8 VVGS = 10 V
VGS - Gate-to-Source Voltage (V)
I DS -
Dra
in-t
o-S
ourc
e C
urre
nt (
A)
1 2 3 4 5 6 70
3
6
9
12
15
18
21
24
27
30
D003
TC = 125° CTC = 25° CTC = -55° C
5
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Typical MOSFET Characteristics (continued)TA = 25°C (unless otherwise stated)
Figure 2. Saturation Characteristics
VDS = 5 V
Figure 3. Transfer Characteristics
ID = 5 A VDS = 50 V
Figure 4. Gate Charge Figure 5. Capacitance
ID = 250 µA
Figure 6. Threshold Voltage vs Temperature Figure 7. On-State Resistance vs Gate-to-Source Voltage
TC - Case Temperature (qC)
I DS -
Dra
in-t
o-S
ourc
e C
urre
nt (
A)
-50 -25 0 25 50 75 100 125 150 1750
2
4
6
8
10
12
14
16
D012
VDS - Drain-to-Source Voltage (V)
I DS -
Dra
in-t
o-S
ourc
e C
urre
nt (
A)
0.1 1 10 100 10000.01
0.1
1
10
100
D010
DC10 ms1 ms
100 µs10 µs
TAV - Time in Avalanche (ms)
I AV -
Pea
k A
vala
nche
Cur
rent
(A
)
0.01 0.1 11
10
100
D011
TC = 25q CTC = 125q C
VSD - Source-to-Drain Voltage (V)
I SD -
Sou
rce-
to-D
rain
Cur
rent
(A
)
0 0.2 0.4 0.6 0.8 1 1.20.0001
0.001
0.01
0.1
1
10
100
D009
TC = 25° CTC = 125° C
TC - Case Temperature (° C)
Nor
mal
ized
On-
Sta
te R
esis
tanc
e
-75 -50 -25 0 25 50 75 100 125 150 1750.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
D008
VGS = 6 VVGS = 10 V
6
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Typical MOSFET Characteristics (continued)TA = 25°C (unless otherwise stated)
ID = 5 A
Figure 8. Normalized On-State Resistance vs Temperature Figure 9. Typical Diode Forward Voltage
Single pulse, max RθJC = 6.2°C/W
Figure 10. Maximum Safe Operating Area Figure 11. Single Pulse Unclamped Inductive Switching
Figure 12. Maximum Drain Current vs Temperature
7
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6 Device and Documentation Support
6.1 Receiving Notification of Documentation UpdatesTo receive notification of documentation updates, navigate to the device product folder on ti.com. In the upperright corner, click on Alert me to register and receive a weekly digest of any product information that haschanged. For change details, review the revision history included in any revised document.
6.2 Community ResourcesThe following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaborationamong engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and helpsolve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools andcontact information for technical support.
6.3 TrademarksNexFET, E2E are trademarks of Texas Instruments.All other trademarks are the property of their respective owners.
6.4 Electrostatic Discharge CautionThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
6.5 GlossarySLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
C
6X 0.350.25
0.95±0.1
6X 0.30.2
2X
1.3
0.3±0.05
4X
0.65
0.8 MAX
0.050.00
0.75±0.1
1±0.1
A2.11.9
B
2.11.9
(0.47)(0.2)
(0.2)
(0.2) TYP
(0.5)
PIN 1 INDEX AREA
SEATING PLANE
1
34
6
X0.3)(45PIN 1 ID
0.1 C A B
0.05 C
8
7
PKG
PKG
8
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7 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 Q2 Package Dimensions
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioningand tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.3. The package thermal pads must be soldered to the printed circuit board for thermal and mechanical
performance.
0.05 MINALL AROUND
0.05 MAXALL AROUND
SOLDER MASKOPENING
METAL UNDERSOLDER MASK
SOLDER MASKDEFINED
METALSOLDER MASKOPENING
NON SOLDER MASKDEFINED
(PREFERRED)
(0.95)
4X (0.65)
(1)
(0.75)
(0.3)
6X (0.45)
6X (0.3)
(1.95)
(R ) TYP0.05
(0.325)
(0.65)
(0.095)
PKG
1
3 4
6
PKG
8
7
9
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Q2 Package Dimensions (continued)7.1.1 Recommended PCB Pattern
1. For recommended circuit layout for PCB designs, see Reducing Ringing Through PCB Layout Techniques(SLPA005).
2. This package is designed to be soldered to a thermal pad on the board. For more information, see QFN/SONPCB Attachment (SLUA271).
6X (0.45)
6X (0.3)
4X (0.65)
(0.86)
(1.95)
(0.9)
(0.7)
(0.29)
(0.325)
(0.65)
(0.095)(R ) TYP0.05
PKG
1
3 4
6
PKG
METALALL AROUND, TYP
8
7
10
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Q2 Package Dimensions (continued)7.1.2 Recommended Stencil Pattern
1. All linear dimensions are in millimeters.2. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525
may have alternate design recommendations.
2.00 ±0.05 Ø 1.50 ±0.10
1.7
5 ±
0.1
0
Ø 1.00 ±0.25
M0168-01
8.0
0+
0.3
0
–0.1
0
4.00 ±0.10
4.00 ±0.10
3.5
0 ±
0.0
5
10° Max
10° Max
0.254 ±0.021.00 ±0.05
2.30 ±0.05
2.3
0 ±
0.0
5
11
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7.2 Q2 Tape and Reel Information
Notes: 1. Measured from centerline of sprocket hole to centerline of pocket.2. Cumulative tolerance of 10 sprocket holes is ±0.2.3. Other material available.4. Typical SR of form tape Max 109 OHM/SQ.5. All dimensions are in mm, unless otherwise specified.
PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device Status(1)
Package Type PackageDrawing
Pins PackageQty
Eco Plan(2)
Lead finish/Ball material
(6)
MSL Peak Temp(3)
Op Temp (°C) Device Marking(4/5)
Samples
CSD19538Q2 ACTIVE WSON DQK 6 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 150 1958
CSD19538Q2T ACTIVE WSON DQK 6 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 150 1958
(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
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